diff options
Diffstat (limited to 'target-mips/gdbstub.c')
| -rw-r--r-- | target-mips/gdbstub.c | 56 |
1 files changed, 29 insertions, 27 deletions
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c index f65fec23cc..9845d880ae 100644 --- a/target-mips/gdbstub.c +++ b/target-mips/gdbstub.c @@ -29,8 +29,13 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); } - if (env->CP0_Config1 & (1 << CP0C1_FP)) { - if (n >= 38 && n < 70) { + if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { + switch (n) { + case 70: + return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31); + case 71: + return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); + default: if (env->CP0_Status & (1 << CP0St_FR)) { return gdb_get_regl(mem_buf, env->active_fpu.fpr[n - 38].d); @@ -39,12 +44,6 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); } } - switch (n) { - case 70: - return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31); - case 71: - return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); - } } switch (n) { case 32: @@ -64,8 +63,10 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return gdb_get_regl(mem_buf, 0); /* fp */ case 89: return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid); - } - if (n >= 73 && n <= 88) { + default: + if (n > 89) { + return 0; + } /* 16 embedded regs. */ return gdb_get_regl(mem_buf, 0); } @@ -73,10 +74,6 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -#define RESTORE_ROUNDING_MODE \ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \ - &env->active_fpu.fp_status) - int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { MIPSCPU *cpu = MIPS_CPU(cs); @@ -89,30 +86,33 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->active_tc.gpr[n] = tmp; return sizeof(target_ulong); } - if (env->CP0_Config1 & (1 << CP0C1_FP) - && n >= 38 && n < 73) { - if (n < 70) { - if (env->CP0_Status & (1 << CP0St_FR)) { - env->active_fpu.fpr[n - 38].d = tmp; - } else { - env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; - } - } + if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { switch (n) { case 70: env->active_fpu.fcr31 = tmp & 0xFF83FFFF; /* set rounding mode */ - RESTORE_ROUNDING_MODE; + restore_rounding_mode(env); + /* set flush-to-zero mode */ + restore_flush_mode(env); break; case 71: - env->active_fpu.fcr0 = tmp; + /* FIR is read-only. Ignore writes. */ + break; + default: + if (env->CP0_Status & (1 << CP0St_FR)) { + env->active_fpu.fpr[n - 38].d = tmp; + } else { + env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; + } break; } return sizeof(target_ulong); } switch (n) { case 32: - env->CP0_Status = tmp; +#ifndef CONFIG_USER_ONLY + cpu_mips_store_status(env, tmp); +#endif break; case 33: env->active_tc.LO[0] = tmp; @@ -124,7 +124,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->CP0_BadVAddr = tmp; break; case 36: - env->CP0_Cause = tmp; +#ifndef CONFIG_USER_ONLY + cpu_mips_store_cause(env, tmp); +#endif break; case 37: env->active_tc.PC = tmp & ~(target_ulong)1; |