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-rw-r--r--target-mips/cpu.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 17ac4ac875..2736614cd4 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -258,9 +258,11 @@ struct CPUMIPSState {
#define MIPS_HFLAG_TMASK 0x007F
#define MIPS_HFLAG_MODE 0x001F /* execution modes */
#define MIPS_HFLAG_UM 0x0001 /* user mode */
-#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
-#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
-#define MIPS_HFLAG_64 0x0020 /* 64-bit instructions enabled */
+#define MIPS_HFLAG_DM 0x0002 /* Debug mode */
+#define MIPS_HFLAG_SM 0x0004 /* Supervisor mode */
+#define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
+#define MIPS_HFLAG_FPU 0x0010 /* FPU enabled */
+#define MIPS_HFLAG_F64 0x0020 /* 64-bit FPU enabled */
#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
/* If translation is interrupted between the branch instruction and
* the delay slot, record what type of branch it is so that we can