diff options
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu-qom.h | 97 | ||||
| -rw-r--r-- | target-i386/cpu.h | 98 |
2 files changed, 98 insertions, 97 deletions
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 2ca7b9ed99..5dde658ac4 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -67,101 +67,6 @@ typedef struct X86CPUClass { void (*parent_reset)(CPUState *cpu); } X86CPUClass; -/** - * X86CPU: - * @env: #CPUX86State - * @migratable: If set, only migratable flags will be accepted when "enforce" - * mode is used, and only migratable flags will be included in the "host" - * CPU model. - * - * An x86 CPU. - */ -typedef struct X86CPU { - /*< private >*/ - CPUState parent_obj; - /*< public >*/ - - CPUX86State env; - - bool hyperv_vapic; - bool hyperv_relaxed_timing; - int hyperv_spinlock_attempts; - char *hyperv_vendor_id; - bool hyperv_time; - bool hyperv_crash; - bool hyperv_reset; - bool hyperv_vpindex; - bool hyperv_runtime; - bool hyperv_synic; - bool hyperv_stimer; - bool check_cpuid; - bool enforce_cpuid; - bool expose_kvm; - bool migratable; - bool host_features; - int64_t apic_id; - - /* if true the CPUID code directly forward host cache leaves to the guest */ - bool cache_info_passthrough; - - /* Features that were filtered out because of missing host capabilities */ - uint32_t filtered_features[FEATURE_WORDS]; - - /* Enable PMU CPUID bits. This can't be enabled by default yet because - * it doesn't have ABI stability guarantees, as it passes all PMU CPUID - * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel - * capabilities) directly to the guest. - */ - bool enable_pmu; - - /* in order to simplify APIC support, we leave this pointer to the - user */ - struct DeviceState *apic_state; - struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; - Notifier machine_done; -} X86CPU; - -static inline X86CPU *x86_env_get_cpu(CPUX86State *env) -{ - return container_of(env, X86CPU, env); -} - -#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) - -#define ENV_OFFSET offsetof(X86CPU, env) - -#ifndef CONFIG_USER_ONLY -extern struct VMStateDescription vmstate_x86_cpu; -#endif - -/** - * x86_cpu_do_interrupt: - * @cpu: vCPU the interrupt is to be handled by. - */ -void x86_cpu_do_interrupt(CPUState *cpu); -bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); - -int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); -int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); -int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); -int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - -void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, - Error **errp); - -void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, - int flags); - -hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); - -int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); - -void x86_cpu_exec_enter(CPUState *cpu); -void x86_cpu_exec_exit(CPUState *cpu); +typedef struct X86CPU X86CPU; #endif diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 0e113245e6..93b5cd0e05 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -20,6 +20,7 @@ #define CPU_I386_H #include "qemu-common.h" +#include "cpu-qom.h" #include "standard-headers/asm-x86/hyperv.h" #ifdef TARGET_X86_64 @@ -1028,7 +1029,102 @@ typedef struct CPUX86State { TPRAccess tpr_access_type; } CPUX86State; -#include "cpu-qom.h" +/** + * X86CPU: + * @env: #CPUX86State + * @migratable: If set, only migratable flags will be accepted when "enforce" + * mode is used, and only migratable flags will be included in the "host" + * CPU model. + * + * An x86 CPU. + */ +struct X86CPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUX86State env; + + bool hyperv_vapic; + bool hyperv_relaxed_timing; + int hyperv_spinlock_attempts; + char *hyperv_vendor_id; + bool hyperv_time; + bool hyperv_crash; + bool hyperv_reset; + bool hyperv_vpindex; + bool hyperv_runtime; + bool hyperv_synic; + bool hyperv_stimer; + bool check_cpuid; + bool enforce_cpuid; + bool expose_kvm; + bool migratable; + bool host_features; + int64_t apic_id; + + /* if true the CPUID code directly forward host cache leaves to the guest */ + bool cache_info_passthrough; + + /* Features that were filtered out because of missing host capabilities */ + uint32_t filtered_features[FEATURE_WORDS]; + + /* Enable PMU CPUID bits. This can't be enabled by default yet because + * it doesn't have ABI stability guarantees, as it passes all PMU CPUID + * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel + * capabilities) directly to the guest. + */ + bool enable_pmu; + + /* in order to simplify APIC support, we leave this pointer to the + user */ + struct DeviceState *apic_state; + struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; + Notifier machine_done; +}; + +static inline X86CPU *x86_env_get_cpu(CPUX86State *env) +{ + return container_of(env, X86CPU, env); +} + +#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(X86CPU, env) + +#ifndef CONFIG_USER_ONLY +extern struct VMStateDescription vmstate_x86_cpu; +#endif + +/** + * x86_cpu_do_interrupt: + * @cpu: vCPU the interrupt is to be handled by. + */ +void x86_cpu_do_interrupt(CPUState *cpu); +bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); + +int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); +int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); +int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); +int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + +void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, + Error **errp); + +void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, + int flags); + +hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + +int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + +void x86_cpu_exec_enter(CPUState *cpu); +void x86_cpu_exec_exit(CPUState *cpu); X86CPU *cpu_x86_init(const char *cpu_model); X86CPU *cpu_x86_create(const char *cpu_model, Error **errp); |