diff options
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.h | 5 | ||||
| -rw-r--r-- | target-i386/helper.c | 18 | ||||
| -rw-r--r-- | target-i386/op_helper.c | 43 |
3 files changed, 66 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index dd57abcecc..d1deda7197 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -242,6 +242,8 @@ #define MSR_MCG_STATUS 0x17a #define MSR_MCG_CTL 0x17b +#define MSR_IA32_PERF_STATUS 0x198 + #define MSR_PAT 0x277 #define MSR_EFER 0xc0000080 @@ -341,6 +343,9 @@ #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ +#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ +#define CPUID_MWAIT_EMX (0 << 1) /* enumeration supported */ + #define EXCP00_DIVZ 0 #define EXCP01_SSTP 1 #define EXCP02_NMI 2 diff --git a/target-i386/helper.c b/target-i386/helper.c index 2dae1e3dfe..f7ad5844fb 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -165,6 +165,24 @@ static x86_def_t x86_defs[] = { .xlevel = 0x8000000A, .model_id = "QEMU Virtual CPU version " QEMU_VERSION, }, + { + .name = "core2duo", + /* original is on level 10 */ + .level = 5, + .family = 6, + .model = 15, + .stepping = 11, + /* the original CPU does have many more features that are + * not implemented yet */ + .features = PPRO_FEATURES | + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | + CPUID_PSE36, + .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, + .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .xlevel = 0x8000000A, + .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", + }, #endif { .name = "qemu32", diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index 23f3080905..c423ca05d4 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -1919,6 +1919,43 @@ void helper_cpuid(void) ECX = 0; EDX = 0x2c307d; break; + case 4: + /* cache info: needed for Core compatibility */ + switch (ECX) { + case 0: /* L1 dcache info */ + EAX = 0x0000121; + EBX = 0x1c0003f; + ECX = 0x000003f; + EDX = 0x0000001; + break; + case 1: /* L1 icache info */ + EAX = 0x0000122; + EBX = 0x1c0003f; + ECX = 0x000003f; + EDX = 0x0000001; + break; + case 2: /* L2 cache info */ + EAX = 0x0000143; + EBX = 0x3c0003f; + ECX = 0x0000fff; + EDX = 0x0000001; + break; + default: /* end of info */ + EAX = 0; + EBX = 0; + ECX = 0; + EDX = 0; + break; + } + + break; + case 5: + /* mwait info: needed for Core compatibility */ + EAX = 0; /* Smallest monitor-line size in bytes */ + EBX = 0; /* Largest monitor-line size in bytes */ + ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; + EDX = 0; + break; case 0x80000000: EAX = env->cpuid_xlevel; EBX = env->cpuid_vendor1; @@ -3089,6 +3126,12 @@ void helper_wrmsr(void) case MSR_VM_HSAVE_PA: env->vm_hsave = val; break; + case MSR_IA32_PERF_STATUS: + /* tsc_increment_by_tick */ + val = 1000ULL; + /* CPU multiplier */ + val |= (((uint64_t)4ULL) << 40); + break; #ifdef TARGET_X86_64 case MSR_LSTAR: env->lstar = val; |