diff options
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 6d764f5353..6cf2c487b8 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1,6 +1,6 @@ /* * i386 virtual CPU header - * + * * Copyright (c) 2003 Fabrice Bellard * * This library is free software; you can redistribute it and/or @@ -116,7 +116,7 @@ #define NT_MASK 0x00004000 #define RF_MASK 0x00010000 #define VM_MASK 0x00020000 -#define AC_MASK 0x00040000 +#define AC_MASK 0x00040000 #define VIF_MASK 0x00080000 #define VIP_MASK 0x00100000 #define ID_MASK 0x00200000 @@ -476,7 +476,7 @@ typedef struct CPUX86State { int i32; int64_t i64; } fp_convert; - + float_status sse_status; uint32_t mxcsr; XMMReg xmm_regs[CPU_NB_REGS]; @@ -504,7 +504,7 @@ typedef struct CPUX86State { uint32_t saved_esp; int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ #endif - + /* exception/interrupt handling */ jmp_buf jmp_env; int exception_index; @@ -513,7 +513,7 @@ typedef struct CPUX86State { target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers */ uint32_t smbase; - int interrupt_request; + int interrupt_request; int user_mode_only; /* user mode only simulation */ int old_exception; /* exception in flight */ @@ -531,7 +531,7 @@ typedef struct CPUX86State { uint32_t cpuid_model[12]; uint32_t cpuid_ext2_features; uint32_t cpuid_apic_id; - + #ifdef USE_KQEMU int kqemu_enabled; int last_io_time; @@ -550,15 +550,15 @@ void cpu_set_ferr(CPUX86State *s); /* this function must always be used to load data in the segment cache: it synchronizes the hflags with the segment cache values */ -static inline void cpu_x86_load_seg_cache(CPUX86State *env, +static inline void cpu_x86_load_seg_cache(CPUX86State *env, int seg_reg, unsigned int selector, target_ulong base, - unsigned int limit, + unsigned int limit, unsigned int flags) { SegmentCache *sc; unsigned int new_hflags; - + sc = &env->segs[seg_reg]; sc->selector = selector; sc->base = base; @@ -573,7 +573,7 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env, /* long mode */ env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; env->hflags &= ~(HF_ADDSEG_MASK); - } else + } else #endif { /* legacy / compatibility case */ @@ -587,7 +587,7 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env, >> (DESC_B_SHIFT - HF_SS32_SHIFT); if (env->hflags & HF_CS64_MASK) { /* zero base assumed for DS, ES and SS in long mode */ - } else if (!(env->cr[0] & CR0_PE_MASK) || + } else if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || !(env->hflags & HF_CS32_MASK)) { /* XXX: try to avoid this test. The problem comes from the @@ -597,12 +597,12 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env, translate-i386.c. */ new_hflags |= HF_ADDSEG_MASK; } else { - new_hflags |= ((env->segs[R_DS].base | + new_hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | - env->segs[R_SS].base) != 0) << + env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; } - env->hflags = (env->hflags & + env->hflags = (env->hflags & ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; } } @@ -630,7 +630,7 @@ void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero is returned if the signal was handled by the virtual CPU. */ -int cpu_x86_signal_handler(int host_signum, void *pinfo, +int cpu_x86_signal_handler(int host_signum, void *pinfo, void *puc); void cpu_x86_set_a20(CPUX86State *env, int a20_state); |