diff options
Diffstat (limited to 'target-i386/cpu.c')
| -rw-r--r-- | target-i386/cpu.c | 36 |
1 files changed, 33 insertions, 3 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 445274c97d..880cfea3f8 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -31,6 +31,8 @@ #include "hyperv.h" +#include "hw/hw.h" + /* feature flags taken from "Intel Processor Identification and the CPUID * Instruction" and AMD's "CPUID Specification". In cases of disagreement * between feature naming conventions, aliases may be added. @@ -50,7 +52,7 @@ static const char *ext_feature_name[] = { "ds_cpl", "vmx", "smx", "est", "tm2", "ssse3", "cid", NULL, "fma", "cx16", "xtpr", "pdcm", - NULL, NULL, "dca", "sse4.1|sse4_1", + NULL, "pcid", "dca", "sse4.1|sse4_1", "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", "tsc-deadline", "aes", "xsave", "osxsave", "avx", NULL, NULL, "hypervisor", @@ -77,7 +79,7 @@ static const char *ext3_feature_name[] = { }; static const char *kvm_feature_name[] = { - "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL, + "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1303,7 +1305,7 @@ void x86_cpudef_setup(void) builtin_x86_defs[i].flags = 1; /* Look for specific "cpudef" models that */ - /* have the QEmu version in .model_id */ + /* have the QEMU version in .model_id */ for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) { if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) { pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version "); @@ -1686,8 +1688,31 @@ static void x86_cpu_reset(CPUState *s) env->dr[7] = DR7_FIXED_1; cpu_breakpoint_remove_all(env, BP_CPU); cpu_watchpoint_remove_all(env, BP_CPU); + +#if !defined(CONFIG_USER_ONLY) + /* We hard-wire the BSP to the first CPU. */ + if (env->cpu_index == 0) { + apic_designate_bsp(env->apic_state); + } + + env->halted = !cpu_is_bsp(cpu); +#endif } +#ifndef CONFIG_USER_ONLY +bool cpu_is_bsp(X86CPU *cpu) +{ + return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP; +} + +/* TODO: remove me, when reset over QOM tree is implemented */ +static void x86_cpu_machine_reset_cb(void *opaque) +{ + X86CPU *cpu = opaque; + cpu_reset(CPU(cpu)); +} +#endif + static void mce_init(X86CPU *cpu) { CPUX86State *cenv = &cpu->env; @@ -1708,8 +1733,13 @@ void x86_cpu_realize(Object *obj, Error **errp) { X86CPU *cpu = X86_CPU(obj); +#ifndef CONFIG_USER_ONLY + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); +#endif + mce_init(cpu); qemu_init_vcpu(&cpu->env); + cpu_reset(CPU(cpu)); } static void x86_cpu_initfn(Object *obj) |