diff options
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate-a64.c | 6 | ||||
| -rw-r--r-- | target-arm/translate.c | 7 |
2 files changed, 7 insertions, 6 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 6a66ac019a..4670941084 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11104,8 +11104,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -11120,7 +11121,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->is_jmp = DISAS_EXC; @@ -11139,7 +11140,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && diff --git a/target-arm/translate.c b/target-arm/translate.c index 83488486b9..cd889977c6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11349,9 +11349,11 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(dc->pc); + num_insns++; - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); + } if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. @@ -11364,7 +11366,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); goto done_generating; @@ -11400,7 +11402,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * Otherwise the subsequent code could get translated several times. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns ++; } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && |