diff options
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 7b50c8c308..6db4c50df4 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9911,6 +9911,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, TranslationBlock *tb, bool search_pc) { + CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; @@ -9930,7 +9931,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; - dc->singlestep_enabled = env->singlestep_enabled; + dc->singlestep_enabled = cs->singlestep_enabled; dc->condjmp = 0; dc->thumb = ARM_TBFLAG_THUMB(tb->flags); dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags); @@ -10080,7 +10081,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * ensures prefetch aborts occur at the right place. */ num_insns ++; } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end && - !env->singlestep_enabled && + !cs->singlestep_enabled && !singlestep && dc->pc < next_page_start && num_insns < max_insns); @@ -10097,7 +10098,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ - if (unlikely(env->singlestep_enabled)) { + if (unlikely(cs->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (dc->condjmp) { gen_set_condexec(dc); |