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-rw-r--r--target-arm/cpu.h6
-rw-r--r--target-arm/nwfpe/double_cpdo.c8
-rw-r--r--target-arm/nwfpe/extended_cpdo.c18
-rw-r--r--target-arm/nwfpe/fpa11.c56
-rw-r--r--target-arm/nwfpe/fpa11.h2
-rw-r--r--target-arm/nwfpe/fpa11_cpdo.c16
-rw-r--r--target-arm/nwfpe/fpa11_cpdt.c46
-rw-r--r--target-arm/nwfpe/fpa11_cprt.c36
-rw-r--r--target-arm/nwfpe/fpopcode.c22
-rw-r--r--target-arm/nwfpe/fpopcode.h6
-rw-r--r--target-arm/nwfpe/single_cpdo.c6
-rw-r--r--target-arm/op.c8
-rw-r--r--target-arm/translate.c24
13 files changed, 127 insertions, 127 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 19ce68b4f1..76fdbb26bf 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -64,11 +64,11 @@ typedef struct CPUARMState {
uint32_t banked_spsr[6];
uint32_t banked_r13[6];
uint32_t banked_r14[6];
-
+
/* These hold r8-r12. */
uint32_t usr_regs[5];
uint32_t fiq_regs[5];
-
+
/* cpsr flag cache for faster execution */
uint32_t CF; /* 0 or 1 */
uint32_t VF; /* V is the bit 31. All other bits are undefined */
@@ -134,7 +134,7 @@ typedef struct CPUARMState {
/* Temporary variables if we don't have spare fp regs. */
float32 tmp0s, tmp1s;
float64 tmp0d, tmp1d;
-
+
float_status fp_status;
} vfp;
diff --git a/target-arm/nwfpe/double_cpdo.c b/target-arm/nwfpe/double_cpdo.c
index afc86aa417..dbd496ea67 100644
--- a/target-arm/nwfpe/double_cpdo.c
+++ b/target-arm/nwfpe/double_cpdo.c
@@ -42,14 +42,14 @@ unsigned int DoubleCPDO(const unsigned int opcode)
unsigned int Fd, Fm, Fn, nRc = 1;
//printk("DoubleCPDO(0x%08x)\n",opcode);
-
+
Fm = getFm(opcode);
if (CONSTANT_FM(opcode))
{
rFm = getDoubleConstant(Fm);
}
else
- {
+ {
switch (fpa11->fType[Fm])
{
case typeSingle:
@@ -85,7 +85,7 @@ unsigned int DoubleCPDO(const unsigned int opcode)
case typeDouble:
rFn = fpa11->fpreg[Fn].fDouble;
break;
-
+
default: return 0;
}
}
@@ -220,7 +220,7 @@ unsigned int DoubleCPDO(const unsigned int opcode)
case NRM_CODE:
break;
-
+
default:
{
nRc = 0;
diff --git a/target-arm/nwfpe/extended_cpdo.c b/target-arm/nwfpe/extended_cpdo.c
index caacdf2288..05e32b0734 100644
--- a/target-arm/nwfpe/extended_cpdo.c
+++ b/target-arm/nwfpe/extended_cpdo.c
@@ -42,14 +42,14 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
unsigned int Fd, Fm, Fn, nRc = 1;
//printk("ExtendedCPDO(0x%08x)\n",opcode);
-
+
Fm = getFm(opcode);
if (CONSTANT_FM(opcode))
{
rFm = getExtendedConstant(Fm);
}
else
- {
+ {
switch (fpa11->fType[Fm])
{
case typeSingle:
@@ -59,15 +59,15 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
case typeDouble:
rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble, &fpa11->fp_status);
break;
-
+
case typeExtended:
rFm = fpa11->fpreg[Fm].fExtended;
break;
-
+
default: return 0;
}
}
-
+
if (!MONADIC_INSTRUCTION(opcode))
{
Fn = getFn(opcode);
@@ -80,11 +80,11 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
case typeDouble:
rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);
break;
-
+
case typeExtended:
rFn = fpa11->fpreg[Fn].fExtended;
break;
-
+
default: return 0;
}
}
@@ -204,13 +204,13 @@ unsigned int ExtendedCPDO(const unsigned int opcode)
case NRM_CODE:
break;
-
+
default:
{
nRc = 0;
}
}
-
+
if (0 != nRc) fpa11->fType[Fd] = typeExtended;
return nRc;
}
diff --git a/target-arm/nwfpe/fpa11.c b/target-arm/nwfpe/fpa11.c
index 7fe6ed3f9c..6b435002e5 100644
--- a/target-arm/nwfpe/fpa11.c
+++ b/target-arm/nwfpe/fpa11.c
@@ -43,16 +43,16 @@ void resetFPA11(void)
{
int i;
FPA11 *fpa11 = GET_FPA11();
-
+
/* initialize the register type array */
for (i=0;i<=7;i++)
{
fpa11->fType[i] = typeNone;
}
-
+
/* FPSR: set system id to FP_EMULATOR, set AC, clear all other bits */
fpa11->fpsr = FP_EMULATOR | BIT_AC;
-
+
/* FPCR: set SB, AB and DA bits, clear all others */
#if MAINTAIN_FPCR
fpa11->fpcr = MASK_RESET;
@@ -66,36 +66,36 @@ void SetRoundingMode(const unsigned int opcode)
#if MAINTAIN_FPCR
fpa11->fpcr &= ~MASK_ROUNDING_MODE;
-#endif
+#endif
switch (opcode & MASK_ROUNDING_MODE)
{
default:
case ROUND_TO_NEAREST:
rounding_mode = float_round_nearest_even;
-#if MAINTAIN_FPCR
+#if MAINTAIN_FPCR
fpa11->fpcr |= ROUND_TO_NEAREST;
-#endif
+#endif
break;
-
+
case ROUND_TO_PLUS_INFINITY:
rounding_mode = float_round_up;
-#if MAINTAIN_FPCR
+#if MAINTAIN_FPCR
fpa11->fpcr |= ROUND_TO_PLUS_INFINITY;
-#endif
+#endif
break;
-
+
case ROUND_TO_MINUS_INFINITY:
rounding_mode = float_round_down;
-#if MAINTAIN_FPCR
+#if MAINTAIN_FPCR
fpa11->fpcr |= ROUND_TO_MINUS_INFINITY;
-#endif
+#endif
break;
-
+
case ROUND_TO_ZERO:
rounding_mode = float_round_to_zero;
-#if MAINTAIN_FPCR
+#if MAINTAIN_FPCR
fpa11->fpcr |= ROUND_TO_ZERO;
-#endif
+#endif
break;
}
set_float_rounding_mode(rounding_mode, &fpa11->fp_status);
@@ -107,30 +107,30 @@ void SetRoundingPrecision(const unsigned int opcode)
FPA11 *fpa11 = GET_FPA11();
#if MAINTAIN_FPCR
fpa11->fpcr &= ~MASK_ROUNDING_PRECISION;
-#endif
+#endif
switch (opcode & MASK_ROUNDING_PRECISION)
{
case ROUND_SINGLE:
rounding_precision = 32;
-#if MAINTAIN_FPCR
+#if MAINTAIN_FPCR
fpa11->fpcr |= ROUND_SINGLE;
-#endif
+#endif
break;
-
+
case ROUND_DOUBLE:
rounding_precision = 64;
-#if MAINTAIN_FPCR
+#if MAINTAIN_FPCR
fpa11->fpcr |= ROUND_DOUBLE;
-#endif
+#endif
break;
-
+
case ROUND_EXTENDED:
rounding_precision = 80;
-#if MAINTAIN_FPCR
+#if MAINTAIN_FPCR
fpa11->fpcr |= ROUND_EXTENDED;
-#endif
+#endif
break;
-
+
default: rounding_precision = 80;
}
set_floatx80_rounding_precision(rounding_precision, &fpa11->fp_status);
@@ -147,7 +147,7 @@ unsigned int EmulateAll(unsigned int opcode, FPA11* qfpa, CPUARMState* qregs)
qemufpa=qfpa;
user_registers=qregs;
-
+
#if 0
fprintf(stderr,"emulating FP insn 0x%08x, PC=0x%08x\n",
opcode, qregs[REG_PC]);
@@ -222,14 +222,14 @@ unsigned int EmulateAll1(unsigned int opcode)
}
}
break;
-
+
case 0xe:
if (opcode & 0x10)
return EmulateCPDO(opcode);
else
return EmulateCPRT(opcode);
break;
-
+
default: return 0;
}
}
diff --git a/target-arm/nwfpe/fpa11.h b/target-arm/nwfpe/fpa11.h
index f1fdfbddae..4fc0b3b886 100644
--- a/target-arm/nwfpe/fpa11.h
+++ b/target-arm/nwfpe/fpa11.h
@@ -1,7 +1,7 @@
/*
NetWinder Floating Point Emulator
(c) Rebel.com, 1998-1999
-
+
Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
diff --git a/target-arm/nwfpe/fpa11_cpdo.c b/target-arm/nwfpe/fpa11_cpdo.c
index 3d5cc93106..777963728f 100644
--- a/target-arm/nwfpe/fpa11_cpdo.c
+++ b/target-arm/nwfpe/fpa11_cpdo.c
@@ -30,16 +30,16 @@ unsigned int EmulateCPDO(const unsigned int opcode)
{
FPA11 *fpa11 = GET_FPA11();
unsigned int Fd, nType, nDest, nRc = 1;
-
+
//printk("EmulateCPDO(0x%08x)\n",opcode);
/* Get the destination size. If not valid let Linux perform
an invalid instruction trap. */
nDest = getDestinationSize(opcode);
if (typeNone == nDest) return 0;
-
+
SetRoundingMode(opcode);
-
+
/* Compare the size of the operands in Fn and Fm.
Choose the largest size and perform operations in that size,
in order to make use of all the precision of the operands.
@@ -49,7 +49,7 @@ unsigned int EmulateCPDO(const unsigned int opcode)
nType = nDest;
else
nType = fpa11->fType[getFn(opcode)];
-
+
if (!CONSTANT_FM(opcode))
{
register unsigned int Fm = getFm(opcode);
@@ -86,7 +86,7 @@ unsigned int EmulateCPDO(const unsigned int opcode)
floatx80_to_float32(fpa11->fpreg[Fd].fExtended, &fpa11->fp_status);
}
break;
-
+
case typeDouble:
{
if (typeSingle == nType)
@@ -97,7 +97,7 @@ unsigned int EmulateCPDO(const unsigned int opcode)
floatx80_to_float64(fpa11->fpreg[Fd].fExtended, &fpa11->fp_status);
}
break;
-
+
case typeExtended:
{
if (typeSingle == nType)
@@ -109,9 +109,9 @@ unsigned int EmulateCPDO(const unsigned int opcode)
}
break;
}
-
+
fpa11->fType[Fd] = nDest;
}
-
+
return nRc;
}
diff --git a/target-arm/nwfpe/fpa11_cpdt.c b/target-arm/nwfpe/fpa11_cpdt.c
index e1a67c71cf..cae2922e0d 100644
--- a/target-arm/nwfpe/fpa11_cpdt.c
+++ b/target-arm/nwfpe/fpa11_cpdt.c
@@ -52,7 +52,7 @@ void loadDouble(const unsigned int Fn,const unsigned int *pMem)
p[0] = tget32(addr + 4);
p[1] = tget32(addr); /* sign & exponent */
#endif
-}
+}
static inline
void loadExtended(const unsigned int Fn,const unsigned int *pMem)
@@ -65,7 +65,7 @@ void loadExtended(const unsigned int Fn,const unsigned int *pMem)
p[0] = tget32(addr); /* sign & exponent */
p[1] = tget32(addr + 8); /* ls bits */
p[2] = tget32(addr + 4); /* ms bits */
-}
+}
static inline
void loadMultiple(const unsigned int Fn,const unsigned int *pMem)
@@ -78,7 +78,7 @@ void loadMultiple(const unsigned int Fn,const unsigned int *pMem)
p = (unsigned int*)&(fpa11->fpreg[Fn]);
x = tget32(addr);
fpa11->fType[Fn] = (x >> 14) & 0x00000003;
-
+
switch (fpa11->fType[Fn])
{
case typeSingle:
@@ -89,12 +89,12 @@ void loadMultiple(const unsigned int Fn,const unsigned int *pMem)
p[2] = 0; /* empty */
}
break;
-
+
case typeExtended:
{
p[1] = tget32(addr + 8);
p[2] = tget32(addr + 4); /* msw */
- p[0] = (x & 0x80003fff);
+ p[0] = (x & 0x80003fff);
}
break;
}
@@ -107,7 +107,7 @@ void storeSingle(const unsigned int Fn,unsigned int *pMem)
FPA11 *fpa11 = GET_FPA11();
float32 val;
register unsigned int *p = (unsigned int*)&val;
-
+
switch (fpa11->fType[Fn])
{
case typeDouble:
@@ -120,9 +120,9 @@ void storeSingle(const unsigned int Fn,unsigned int *pMem)
default: val = fpa11->fpreg[Fn].fSingle;
}
-
+
tput32(addr, p[0]);
-}
+}
static inline
void storeDouble(const unsigned int Fn,unsigned int *pMem)
@@ -151,7 +151,7 @@ void storeDouble(const unsigned int Fn,unsigned int *pMem)
tput32(addr, p[1]); /* msw */
tput32(addr + 4, p[0]); /* lsw */
#endif
-}
+}
static inline
void storeExtended(const unsigned int Fn,unsigned int *pMem)
@@ -160,7 +160,7 @@ void storeExtended(const unsigned int Fn,unsigned int *pMem)
FPA11 *fpa11 = GET_FPA11();
floatx80 val;
register unsigned int *p = (unsigned int*)&val;
-
+
switch (fpa11->fType[Fn])
{
case typeSingle:
@@ -173,11 +173,11 @@ void storeExtended(const unsigned int Fn,unsigned int *pMem)
default: val = fpa11->fpreg[Fn].fExtended;
}
-
+
tput32(addr, p[0]); /* sign & exp */
tput32(addr + 8, p[1]);
tput32(addr + 4, p[2]); /* msw */
-}
+}
static inline
void storeMultiple(const unsigned int Fn,unsigned int *pMem)
@@ -185,10 +185,10 @@ void storeMultiple(const unsigned int Fn,unsigned int *pMem)
target_ulong addr = (target_ulong)(long)pMem;
FPA11 *fpa11 = GET_FPA11();
register unsigned int nType, *p;
-
+
p = (unsigned int*)&(fpa11->fpreg[Fn]);
nType = fpa11->fType[Fn];
-
+
switch (nType)
{
case typeSingle:
@@ -199,7 +199,7 @@ void storeMultiple(const unsigned int Fn,unsigned int *pMem)
tput32(addr, nType << 14);
}
break;
-
+
case typeExtended:
{
tput32(addr + 4, p[2]); /* msw */
@@ -239,7 +239,7 @@ unsigned int PerformLDF(const unsigned int opcode)
case TRANSFER_EXTENDED: loadExtended(getFd(opcode),pAddress); break;
default: nRc = 0;
}
-
+
if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
return nRc;
}
@@ -248,10 +248,10 @@ unsigned int PerformSTF(const unsigned int opcode)
{
unsigned int *pBase, *pAddress, *pFinal, nRc = 1,
write_back = WRITE_BACK(opcode);
-
+
//printk("PerformSTF(0x%08x), Fd = 0x%08x\n",opcode,getFd(opcode));
SetRoundingMode(ROUND_TO_NEAREST);
-
+
pBase = (unsigned int*)readRegister(getRn(opcode));
if (REG_PC == getRn(opcode))
{
@@ -274,7 +274,7 @@ unsigned int PerformSTF(const unsigned int opcode)
case TRANSFER_EXTENDED: storeExtended(getFd(opcode),pAddress); break;
default: nRc = 0;
}
-
+
if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
return nRc;
}
@@ -315,14 +315,14 @@ unsigned int PerformSFM(const unsigned int opcode)
{
unsigned int i, Fd, *pBase, *pAddress, *pFinal,
write_back = WRITE_BACK(opcode);
-
+
pBase = (unsigned int*)readRegister(getRn(opcode));
if (REG_PC == getRn(opcode))
{
pBase += 2;
write_back = 0;
}
-
+
pFinal = pBase;
if (BIT_UP_SET(opcode))
pFinal += getOffset(opcode);
@@ -349,7 +349,7 @@ unsigned int EmulateCPDT(const unsigned int opcode)
unsigned int nRc = 0;
//printk("EmulateCPDT(0x%08x)\n",opcode);
-
+
if (LDF_OP(opcode))
{
nRc = PerformLDF(opcode);
@@ -370,7 +370,7 @@ unsigned int EmulateCPDT(const unsigned int opcode)
{
nRc = 0;
}
-
+
return nRc;
}
#endif
diff --git a/target-arm/nwfpe/fpa11_cprt.c b/target-arm/nwfpe/fpa11_cprt.c
index 68c4ff192d..04eae8c6fc 100644
--- a/target-arm/nwfpe/fpa11_cprt.c
+++ b/target-arm/nwfpe/fpa11_cprt.c
@@ -55,7 +55,7 @@ unsigned int EmulateCPRT(const unsigned int opcode)
{
case FLT_CODE >> 20: nRc = PerformFLT(opcode); break;
case FIX_CODE >> 20: nRc = PerformFIX(opcode); break;
-
+
case WFS_CODE >> 20: writeFPSR(readRegister(getRd(opcode))); break;
case RFS_CODE >> 20: writeRegister(getRd(opcode),readFPSR()); break;
@@ -67,14 +67,14 @@ unsigned int EmulateCPRT(const unsigned int opcode)
default: nRc = 0;
}
-
+
return nRc;
}
unsigned int PerformFLT(const unsigned int opcode)
{
FPA11 *fpa11 = GET_FPA11();
-
+
unsigned int nRc = 1;
SetRoundingMode(opcode);
@@ -95,7 +95,7 @@ unsigned int PerformFLT(const unsigned int opcode)
int32_to_float64(readRegister(getRd(opcode)), &fpa11->fp_status);
}
break;
-
+
case ROUND_EXTENDED:
{
fpa11->fType[getFn(opcode)] = typeExtended;
@@ -103,10 +103,10 @@ unsigned int PerformFLT(const unsigned int opcode)
int32_to_floatx80(readRegister(getRd(opcode)), &fpa11->fp_status);
}
break;
-
+
default: nRc = 0;
}
-
+
return nRc;
}
@@ -115,7 +115,7 @@ unsigned int PerformFIX(const unsigned int opcode)
FPA11 *fpa11 = GET_FPA11();
unsigned int nRc = 1;
unsigned int Fn = getFm(opcode);
-
+
SetRoundingMode(opcode);
switch (fpa11->fType[Fn])
@@ -134,21 +134,21 @@ unsigned int PerformFIX(const unsigned int opcode)
float64_to_int32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status));
}
break;
-
+
case typeExtended:
{
writeRegister(getRd(opcode),
floatx80_to_int32(fpa11->fpreg[Fn].fExtended, &fpa11->fp_status));
}
break;
-
+
default: nRc = 0;
}
-
+
return nRc;
}
-
+
static unsigned int __inline__
PerformComparisonOperation(floatx80 Fn, floatx80 Fm)
{
@@ -160,7 +160,7 @@ PerformComparisonOperation(floatx80 Fn, floatx80 Fm)
{
flags |= CC_NEGATIVE;
}
-
+
/* test for equal condition */
if (floatx80_eq(Fn,Fm, &fpa11->fp_status))
{
@@ -172,13 +172,13 @@ PerformComparisonOperation(floatx80 Fn, floatx80 Fm)
{
flags |= CC_CARRY;
}
-
+
writeConditionCodes(flags);
return 1;
}
/* This instruction sets the flags N, Z, C, V in the FPSR. */
-
+
static unsigned int PerformComparison(const unsigned int opcode)
{
FPA11 *fpa11 = GET_FPA11();
@@ -213,14 +213,14 @@ static unsigned int PerformComparison(const unsigned int opcode)
goto unordered;
rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status);
break;
-
+
case typeExtended:
//printk("extended.\n");
if (floatx80_is_nan(fpa11->fpreg[Fn].fExtended))
goto unordered;
rFn = fpa11->fpreg[Fn].fExtended;
break;
-
+
default: return 0;
}
@@ -249,14 +249,14 @@ static unsigned int PerformComparison(const unsigned int opcode)
goto unordered;
rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble, &fpa11->fp_status);
break;
-
+
case typeExtended:
//printk("extended.\n");
if (floatx80_is_nan(fpa11->fpreg[Fm].fExtended))
goto unordered;
rFm = fpa11->fpreg[Fm].fExtended;
break;
-
+
default: return 0;
}
}
diff --git a/target-arm/nwfpe/fpopcode.c b/target-arm/nwfpe/fpopcode.c
index efee406fb0..a733a1d1de 100644
--- a/target-arm/nwfpe/fpopcode.c
+++ b/target-arm/nwfpe/fpopcode.c
@@ -35,7 +35,7 @@ const floatx80 floatx80Constant[] = {
{ 0xa000000000000000ULL, 0x4001}, /* extended 5.0 */
{ 0x8000000000000000ULL, 0x3ffe}, /* extended 0.5 */
{ 0xa000000000000000ULL, 0x4002} /* extended 10.0 */
-};
+};
const float64 float64Constant[] = {
0x0000000000000000ULL, /* double 0.0 */
@@ -46,7 +46,7 @@ const float64 float64Constant[] = {
0x4014000000000000ULL, /* double 5.0 */
0x3fe0000000000000ULL, /* double 0.5 */
0x4024000000000000ULL /* double 10.0 */
-};
+};
const float32 float32Constant[] = {
0x00000000, /* single 0.0 */
@@ -57,12 +57,12 @@ const float32 float32Constant[] = {
0x40a00000, /* single 5.0 */
0x3f000000, /* single 0.5 */
0x41200000 /* single 10.0 */
-};
+};
unsigned int getTransferLength(const unsigned int opcode)
{
unsigned int nRc;
-
+
switch (opcode & MASK_TRANSFER_LENGTH)
{
case 0x00000000: nRc = 1; break; /* single precision */
@@ -70,14 +70,14 @@ unsigned int getTransferLength(const unsigned int opcode)
case 0x00400000: nRc = 3; break; /* extended precision */
default: nRc = 0;
}
-
+
return(nRc);
}
unsigned int getRegisterCount(const unsigned int opcode)
{
unsigned int nRc;
-
+
switch (opcode & MASK_REGISTER_COUNT)
{
case 0x00000000: nRc = 4; break;
@@ -86,14 +86,14 @@ unsigned int getRegisterCount(const unsigned int opcode)
case 0x00408000: nRc = 3; break;
default: nRc = 0;
}
-
+
return(nRc);
}
unsigned int getRoundingPrecision(const unsigned int opcode)
{
unsigned int nRc;
-
+
switch (opcode & MASK_ROUNDING_PRECISION)
{
case 0x00000000: nRc = 1; break;
@@ -101,14 +101,14 @@ unsigned int getRoundingPrecision(const unsigned int opcode)
case 0x00080000: nRc = 3; break;
default: nRc = 0;
}
-
+
return(nRc);
}
unsigned int getDestinationSize(const unsigned int opcode)
{
unsigned int nRc;
-
+
switch (opcode & MASK_DESTINATION_SIZE)
{
case 0x00000000: nRc = typeSingle; break;
@@ -116,7 +116,7 @@ unsigned int getDestinationSize(const unsigned int opcode)
case 0x00080000: nRc = typeExtended; break;
default: nRc = typeNone;
}
-
+
return(nRc);
}
diff --git a/target-arm/nwfpe/fpopcode.h b/target-arm/nwfpe/fpopcode.h
index e16e47af6d..6c51067b6c 100644
--- a/target-arm/nwfpe/fpopcode.h
+++ b/target-arm/nwfpe/fpopcode.h
@@ -35,7 +35,7 @@ ARM Floating Point Instruction Classes
CPDT data transfer instructions
LDF, STF, LFM, SFM
-
+
CPDO dyadic arithmetic instructions
ADF, MUF, SUF, RSF, DVF, RDF,
POW, RPW, RMF, FML, FDV, FRD, POL
@@ -43,7 +43,7 @@ CPDO dyadic arithmetic instructions
CPDO monadic arithmetic instructions
MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
-
+
CPRT joint arithmetic/data transfer instructions
FIX (arithmetic followed by load/store)
FLT (load/store followed by arithmetic)
@@ -57,7 +57,7 @@ U up/down bit: 0 = stack grows down, 1 = stack grows up
W write back bit: 1 = update base register (Rn)
L load/store bit: 0 = store, 1 = load
Rn base register
-Rd destination/source register
+Rd destination/source register
Fd floating point destination register
Fn floating point source register
Fm floating point source register or floating point constant
diff --git a/target-arm/nwfpe/single_cpdo.c b/target-arm/nwfpe/single_cpdo.c
index 4f2ca6ade3..1482f47120 100644
--- a/target-arm/nwfpe/single_cpdo.c
+++ b/target-arm/nwfpe/single_cpdo.c
@@ -47,13 +47,13 @@ unsigned int SingleCPDO(const unsigned int opcode)
rFm = getSingleConstant(Fm);
}
else
- {
+ {
switch (fpa11->fType[Fm])
{
case typeSingle:
rFm = fpa11->fpreg[Fm].fSingle;
break;
-
+
default: return 0;
}
}
@@ -186,7 +186,7 @@ unsigned int SingleCPDO(const unsigned int opcode)
case NRM_CODE:
break;
-
+
default:
{
nRc = 0;
diff --git a/target-arm/op.c b/target-arm/op.c
index b282173184..e8a536c1ab 100644
--- a/target-arm/op.c
+++ b/target-arm/op.c
@@ -774,7 +774,7 @@ void OPPROTO op_addl_T0_T1_saturate(void)
}
else
T0 = res;
-
+
FORCE_RET();
}
@@ -792,7 +792,7 @@ void OPPROTO op_subl_T0_T1_saturate(void)
}
else
T0 = res;
-
+
FORCE_RET();
}
@@ -1127,7 +1127,7 @@ void OPPROTO op_vfp_msr(void)
void OPPROTO op_vfp_mrrd(void)
{
CPU_DoubleU u;
-
+
u.d = FT0d;
T0 = u.l.lower;
T1 = u.l.upper;
@@ -1136,7 +1136,7 @@ void OPPROTO op_vfp_mrrd(void)
void OPPROTO op_vfp_mdrr(void)
{
CPU_DoubleU u;
-
+
u.l.lower = T0;
u.l.upper = T1;
FT0d = u.d;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index a6647d4f7b..bb01f2f340 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -116,7 +116,7 @@ const uint8_t table_logic_cc[16] = {
1, /* bic */
1, /* mvn */
};
-
+
static GenOpFunc1 *gen_shift_T1_im[4] = {
gen_op_shll_T1_im,
gen_op_shrl_T1_im,
@@ -390,7 +390,7 @@ static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
int extra)
{
int val, rm;
-
+
if (insn & (1 << 22)) {
/* immediate */
val = (insn & 0xf) | ((insn >> 4) & 0xf0);
@@ -1784,7 +1784,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
delta_m = 0;
delta_d = 0;
bank_mask = 0;
-
+
if (veclen > 0) {
if (dp)
bank_mask = 0xc;
@@ -2205,10 +2205,10 @@ static void gen_exception_return(DisasContext *s)
static void disas_arm_insn(CPUState * env, DisasContext *s)
{
unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
-
+
insn = ldl_code(s->pc);
s->pc += 4;
-
+
cond = insn >> 28;
if (cond == 0xf){
/* Unconditional instructions. */
@@ -2403,7 +2403,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
(insn & 0x00000090) != 0x90) ||
((insn & 0x0e000000) == (1 << 25))) {
int set_cc, logic_cc, shiftop;
-
+
op1 = (insn >> 21) & 0xf;
set_cc = (insn >> 20) & 1;
logic_cc = table_logic_cc[op1] & set_cc;
@@ -2626,7 +2626,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
} else {
/* SWP instruction */
rm = (insn) & 0xf;
-
+
gen_movl_T0_reg(s, rm);
gen_movl_T1_reg(s, rn);
if (insn & (1 << 22)) {
@@ -2799,7 +2799,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
}
rn = (insn >> 16) & 0xf;
gen_movl_T1_reg(s, rn);
-
+
/* compute total size */
loaded_base = 0;
n = 0;
@@ -2897,7 +2897,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
case 0xb:
{
int32_t offset;
-
+
/* branch (and link) */
val = (int32_t)s->pc;
if (insn & (1 << 24)) {
@@ -3500,7 +3500,7 @@ static void disas_thumb_insn(DisasContext *s)
val = (uint32_t)s->pc + 2;
gen_op_movl_T1_im(val | 1);
gen_movl_reg_T1(s, 14);
-
+
val += offset << 1;
if (insn & (1 << 12)) {
/* bl */
@@ -3532,10 +3532,10 @@ static inline int gen_intermediate_code_internal(CPUState *env,
int j, lj;
target_ulong pc_start;
uint32_t next_page_start;
-
+
/* generate intermediate code */
pc_start = tb->pc;
-
+
dc->tb = tb;
gen_opc_ptr = gen_opc_buf;
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-24 23:45:40 +0000