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-rw-r--r--target-arm/translate.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index ef529eb161..8669e9422c 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -205,6 +205,9 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
#define gen_sxtb16(var) tcg_gen_helper_1_1(HELPER_ADDR(sxtb16), var, var)
#define gen_uxtb16(var) tcg_gen_helper_1_1(HELPER_ADDR(uxtb16), var, var)
+#define gen_op_clz_T0(var) \
+ tcg_gen_helper_1_1(HELPER_ADDR(clz), cpu_T[0], cpu_T[0])
+
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
tmp = (t0 ^ t1) & 0x8000;
t0 &= ~0x8000;