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-rw-r--r--target-arm/helper.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fe642df748..9866e50ab7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3696,6 +3696,8 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
target_ulong page_size;
int prot;
int ret, is_user;
+ uint32_t syn;
+ bool same_el = (arm_current_pl(env) != 0);
is_user = mmu_idx == MMU_USER_IDX;
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
@@ -3708,14 +3710,24 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
return 0;
}
+ /* AArch64 syndrome does not have an LPAE bit */
+ syn = ret & ~(1 << 9);
+
+ /* For insn and data aborts we assume there is no instruction syndrome
+ * information; this is always true for exceptions reported to EL1.
+ */
if (access_type == 2) {
+ syn = syn_insn_abort(same_el, 0, 0, syn);
cs->exception_index = EXCP_PREFETCH_ABORT;
} else {
+ syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
ret |= (1 << 11);
}
cs->exception_index = EXCP_DATA_ABORT;
}
+
+ env->exception.syndrome = syn;
env->exception.vaddress = address;
env->exception.fsr = ret;
return 1;