1 files changed, 54 insertions, 0 deletions
diff --git a/pc-bios/bios-pq/0008_kvm-bios-switch-mtrrs-to-cover-only-the-pci-range-and--default-to-wb.patch b/pc-bios/bios-pq/0008_kvm-bios-switch-mtrrs-to-cover-only-the-pci-range-and--default-to-wb.patch
new file mode 100644
index 0000000000..caf9aee994
--- /dev/null
+++ b/pc-bios/bios-pq/0008_kvm-bios-switch-mtrrs-to-cover-only-the-pci-range-and--default-to-wb.patch
@@ -0,0 +1,54 @@
+switch MTRRs to cover only the PCI range and  default to WB (Alex Williamson)
+
+This matches how some bare metal machines report MTRRs and avoids
+the problem of running out of MTRRs to cover all of RAM.
+    
+Signed-off-by: Alex Williamson <alex.williamson@hp.com>
+Signed-off-by: Avi Kivity <avi@redhat.com>
+Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
+
+Index: bochs/bios/rombios32.c
+===================================================================
+--- bochs.orig/bios/rombios32.c
++++ bochs/bios/rombios32.c
+@@ -525,7 +525,6 @@ void setup_mtrr(void)
+         uint8_t valb[8];
+         uint64_t val;
+     } u;
+-    uint64_t vbase, vmask;
+
+     mtrr_cap = rdmsr(MSR_MTRRcap);
+     vcnt = mtrr_cap & 0xff;
+@@ -552,25 +551,10 @@ void setup_mtrr(void)
+     wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
+     wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
+     wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
+-    vbase = 0;
+-    --vcnt; /* leave one mtrr for VRAM */
+-    for (i = 0; i < vcnt && vbase < ram_size; ++i) {
+-        vmask = (1ull << 40) - 1;
+-        while (vbase + vmask + 1 > ram_size)
+-            vmask >>= 1;
+-        wrmsr_smp(MTRRphysBase_MSR(i), vbase | 6);
+-        wrmsr_smp(MTRRphysMask_MSR(i), (~vmask & 0xfffffff000ull) | 0x800);
+-        vbase += vmask + 1;
+-    }
+-    for (vbase = 1ull << 32; i < vcnt && vbase < ram_end; ++i) {
+-        vmask = (1ull << 40) - 1;
+-        while (vbase + vmask + 1 > ram_end)
+-            vmask >>= 1;
+-        wrmsr_smp(MTRRphysBase_MSR(i), vbase | 6);
+-        wrmsr_smp(MTRRphysMask_MSR(i), (~vmask & 0xfffffff000ull) | 0x800);
+-        vbase += vmask + 1;
+-    }
+-    wrmsr_smp(MSR_MTRRdefType, 0xc00);
++    /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
++    wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
++    wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
++    wrmsr_smp(MSR_MTRRdefType, 0xc06);
+ }
+
+ void ram_probe(void)
+
+
+