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-rw-r--r--include/hw/compat.h16
-rw-r--r--include/hw/ide/internal.h1
-rw-r--r--include/hw/pci/pci.h2
-rw-r--r--include/hw/pci/pcie.h5
4 files changed, 24 insertions, 0 deletions
diff --git a/include/hw/compat.h b/include/hw/compat.h
index b7db43803c..90606f9fdb 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -18,6 +18,22 @@
.driver = "pci-bridge",\
.property = "shpc",\
.value = "on",\
+ },{\
+ .driver = TYPE_PCI_DEVICE,\
+ .property = "x-pcie-extcap-init",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "x-pcie-deverr-init",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "x-pcie-lnkctl-init",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "x-pcie-pm-init",\
+ .value = "off",\
},
#define HW_COMPAT_2_7 \
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
index 88dc11808b..482a9512be 100644
--- a/include/hw/ide/internal.h
+++ b/include/hw/ide/internal.h
@@ -607,6 +607,7 @@ int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
uint32_t cylinders, uint32_t heads, uint32_t secs,
int chs_trans);
void ide_init2(IDEBus *bus, qemu_irq irq);
+void ide_exit(IDEState *s);
void ide_init_ioport(IDEBus *bus, ISADevice *isa, int iobase, int iobase2);
void ide_register_restart_cb(IDEBus *bus);
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 713ede00bf..a37a2d5cb6 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -183,6 +183,8 @@ enum {
/* Link active status in endpoint capability is always set */
#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
+#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
+ QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
};
#define TYPE_PCI_DEVICE "pci-device"
diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
index 163c5195b6..3d8f24b007 100644
--- a/include/hw/pci/pcie.h
+++ b/include/hw/pci/pcie.h
@@ -63,6 +63,8 @@ typedef enum {
struct PCIExpressDevice {
/* Offset of express capability in config space */
uint8_t exp_cap;
+ /* Offset of Power Management capability in config space */
+ uint8_t pm_cap;
/* SLOT */
bool hpev_notified; /* Logical AND of conditions for hot plug event.
@@ -96,6 +98,9 @@ uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
void pcie_cap_deverr_init(PCIDevice *dev);
void pcie_cap_deverr_reset(PCIDevice *dev);
+void pcie_cap_lnkctl_init(PCIDevice *dev);
+void pcie_cap_lnkctl_reset(PCIDevice *dev);
+
void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
void pcie_cap_slot_reset(PCIDevice *dev);
void pcie_cap_slot_write_config(PCIDevice *dev,