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-rw-r--r--include/exec/exec-all.h2
-rw-r--r--include/exec/tb-hash.h12
-rw-r--r--include/hw/i386/pc.h42
-rw-r--r--include/qemu/atomic.h34
-rw-r--r--include/qom/cpu.h2
-rw-r--r--include/sysemu/numa.h1
6 files changed, 62 insertions, 31 deletions
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index bcde1e6a14..87ae10bcc9 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -368,6 +368,8 @@ struct TranslationBlock {
void tb_free(TranslationBlock *tb);
void tb_flush(CPUState *cpu);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
+TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
+ target_ulong cs_base, uint32_t flags);
#if defined(USE_DIRECT_JUMP)
diff --git a/include/exec/tb-hash.h b/include/exec/tb-hash.h
index 2c27490cb8..b1fe2d0161 100644
--- a/include/exec/tb-hash.h
+++ b/include/exec/tb-hash.h
@@ -22,6 +22,8 @@
#include "exec/tb-hash-xx.h"
+#ifdef CONFIG_SOFTMMU
+
/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
addresses on the same page. The top bits are the same. This allows
TLB invalidation to quickly clear a subset of the hash table. */
@@ -45,6 +47,16 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
| (tmp & TB_JMP_ADDR_MASK));
}
+#else
+
+/* In user-mode we can get better hashing because we do not have a TLB */
+static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
+{
+ return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
+}
+
+#endif /* CONFIG_SOFTMMU */
+
static inline
uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t flags)
{
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index e447f5d8f4..d071c9c0e9 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -566,75 +566,75 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.value = "off",\
},{\
.driver = "qemu64" "-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(4),\
},{\
.driver = "kvm64" "-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(5),\
},{\
.driver = "pentium3" "-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(2),\
},{\
.driver = "n270" "-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(5),\
},{\
.driver = "Conroe" "-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(4),\
},{\
.driver = "Penryn" "-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(4),\
},{\
.driver = "Nehalem" "-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(4),\
},{\
.driver = "n270" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Penryn" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Conroe" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Nehalem" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Westmere" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "SandyBridge" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "IvyBridge" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Haswell" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Broadwell" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
+ .property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = TYPE_X86_CPU,\
@@ -860,7 +860,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.value = stringify(2),\
},{\
.driver = "Conroe-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(2),\
},{\
.driver = "Penryn-" TYPE_X86_CPU,\
@@ -868,7 +868,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.value = stringify(2),\
},{\
.driver = "Penryn-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(2),\
},{\
.driver = "Nehalem-" TYPE_X86_CPU,\
@@ -876,7 +876,7 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.value = stringify(2),\
},{\
.driver = "Nehalem-" TYPE_X86_CPU,\
- .property = "level",\
+ .property = "min-level",\
.value = stringify(2),\
},{\
.driver = "virtio-net-pci",\
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index 878fa0700d..e07c7972ab 100644
--- a/include/qemu/atomic.h
+++ b/include/qemu/atomic.h
@@ -88,6 +88,24 @@
#define smp_read_barrier_depends() barrier()
#endif
+/* Sanity check that the size of an atomic operation isn't "overly large".
+ * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
+ * want to use them because we ought not need them, and this lets us do a
+ * bit of sanity checking that other 32-bit hosts might build.
+ *
+ * That said, we have a problem on 64-bit ILP32 hosts in that in order to
+ * sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
+ * We'd prefer not want to pull in everything else TCG related, so handle
+ * those few cases by hand.
+ *
+ * Note that x32 is fully detected with __x64_64__ + _ILP32, and that for
+ * Sparc we always force the use of sparcv9 in configure.
+ */
+#if defined(__x86_64__) || defined(__sparc__)
+# define ATOMIC_REG_SIZE 8
+#else
+# define ATOMIC_REG_SIZE sizeof(void *)
+#endif
/* Weak atomic operations prevent the compiler moving other
* loads/stores past the atomic operation load/store. However there is
@@ -104,7 +122,7 @@
#define atomic_read(ptr) \
({ \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
atomic_read__nocheck(ptr); \
})
@@ -112,7 +130,7 @@
__atomic_store_n(ptr, i, __ATOMIC_RELAXED)
#define atomic_set(ptr, i) do { \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
atomic_set__nocheck(ptr, i); \
} while(0)
@@ -130,27 +148,27 @@
#define atomic_rcu_read(ptr) \
({ \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
typeof_strip_qual(*ptr) _val; \
atomic_rcu_read__nocheck(ptr, &_val); \
_val; \
})
#define atomic_rcu_set(ptr, i) do { \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
__atomic_store_n(ptr, i, __ATOMIC_RELEASE); \
} while(0)
#define atomic_load_acquire(ptr) \
({ \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
typeof_strip_qual(*ptr) _val; \
__atomic_load(ptr, &_val, __ATOMIC_ACQUIRE); \
_val; \
})
#define atomic_store_release(ptr, i) do { \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
__atomic_store_n(ptr, i, __ATOMIC_RELEASE); \
} while(0)
@@ -162,7 +180,7 @@
})
#define atomic_xchg(ptr, i) ({ \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
atomic_xchg__nocheck(ptr, i); \
})
@@ -175,7 +193,7 @@
})
#define atomic_cmpxchg(ptr, old, new) ({ \
- QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+ QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
atomic_cmpxchg__nocheck(ptr, old, new); \
})
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 55214ce131..89ddb686fb 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -265,7 +265,6 @@ struct qemu_work_item;
* @cpu_index: CPU index (informative).
* @nr_cores: Number of cores within this CPU package.
* @nr_threads: Number of threads within this CPU.
- * @numa_node: NUMA node this CPU is belonging to.
* @host_tid: Host thread ID.
* @running: #true if CPU is currently running (lockless).
* @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
@@ -314,7 +313,6 @@ struct CPUState {
int nr_cores;
int nr_threads;
- int numa_node;
struct QemuThread *thread;
#ifdef _WIN32
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 7ffde5b119..610eece211 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -35,4 +35,5 @@ void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
int nb_nodes, ram_addr_t size);
void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
int nb_nodes, ram_addr_t size);
+void numa_cpu_pre_plug(const CPUArchId *slot, DeviceState *dev, Error **errp);
#endif
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-05 04:44:58 +0000