diff options
Diffstat (limited to 'include/hw/ppc/spapr.h')
| -rw-r--r-- | include/hw/ppc/spapr.h | 194 |
1 files changed, 104 insertions, 90 deletions
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 59073a7579..2b4c05a2ec 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -8,16 +8,16 @@ #include "hw/mem/pc-dimm.h" #include "hw/ppc/spapr_ovec.h" #include "hw/ppc/spapr_irq.h" -#include "hw/ppc/spapr_xive.h" /* For sPAPRXive */ +#include "hw/ppc/spapr_xive.h" /* For SpaprXive */ #include "hw/ppc/xics.h" /* For ICSState */ -struct VIOsPAPRBus; -struct sPAPRPHBState; -struct sPAPRNVRAM; +struct SpaprVioBus; +struct SpaprPhbState; +struct SpaprNvram; -typedef struct sPAPREventLogEntry sPAPREventLogEntry; -typedef struct sPAPREventSource sPAPREventSource; -typedef struct sPAPRPendingHPT sPAPRPendingHPT; +typedef struct SpaprEventLogEntry SpaprEventLogEntry; +typedef struct SpaprEventSource SpaprEventSource; +typedef struct SpaprPendingHpt SpaprPendingHpt; #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL #define SPAPR_ENTRY_POINT 0x100 @@ -27,32 +27,32 @@ typedef struct sPAPRPendingHPT sPAPRPendingHPT; #define TYPE_SPAPR_RTC "spapr-rtc" #define SPAPR_RTC(obj) \ - OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) + OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) -typedef struct sPAPRRTCState sPAPRRTCState; -struct sPAPRRTCState { +typedef struct SpaprRtcState SpaprRtcState; +struct SpaprRtcState { /*< private >*/ DeviceState parent_obj; int64_t ns_offset; }; -typedef struct sPAPRDIMMState sPAPRDIMMState; -typedef struct sPAPRMachineClass sPAPRMachineClass; +typedef struct SpaprDimmState SpaprDimmState; +typedef struct SpaprMachineClass SpaprMachineClass; #define TYPE_SPAPR_MACHINE "spapr-machine" #define SPAPR_MACHINE(obj) \ - OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) + OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) #define SPAPR_MACHINE_GET_CLASS(obj) \ - OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) + OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) #define SPAPR_MACHINE_CLASS(klass) \ - OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) + OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) typedef enum { SPAPR_RESIZE_HPT_DEFAULT = 0, SPAPR_RESIZE_HPT_DISABLED, SPAPR_RESIZE_HPT_ENABLED, SPAPR_RESIZE_HPT_REQUIRED, -} sPAPRResizeHPT; +} SpaprResizeHpt; /** * Capabilities @@ -74,8 +74,12 @@ typedef enum { #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 /* Nested KVM-HV */ #define SPAPR_CAP_NESTED_KVM_HV 0x07 +/* Large Decrementer */ +#define SPAPR_CAP_LARGE_DECREMENTER 0x08 +/* Count Cache Flush Assist HW Instruction */ +#define SPAPR_CAP_CCF_ASSIST 0x09 /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_KVM_HV + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) /* * Capability Values @@ -83,22 +87,27 @@ typedef enum { /* Bool Caps */ #define SPAPR_CAP_OFF 0x00 #define SPAPR_CAP_ON 0x01 + /* Custom Caps */ + +/* Generic */ #define SPAPR_CAP_BROKEN 0x00 #define SPAPR_CAP_WORKAROUND 0x01 #define SPAPR_CAP_FIXED 0x02 +/* SPAPR_CAP_IBS (cap-ibs) */ #define SPAPR_CAP_FIXED_IBS 0x02 #define SPAPR_CAP_FIXED_CCD 0x03 +#define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ -typedef struct sPAPRCapabilities sPAPRCapabilities; -struct sPAPRCapabilities { +typedef struct SpaprCapabilities SpaprCapabilities; +struct SpaprCapabilities { uint8_t caps[SPAPR_CAP_NUM]; }; /** - * sPAPRMachineClass: + * SpaprMachineClass: */ -struct sPAPRMachineClass { +struct SpaprMachineClass { /*< private >*/ MachineClass parent_class; @@ -110,33 +119,33 @@ struct sPAPRMachineClass { bool pre_2_10_has_unused_icps; bool legacy_irq_allocation; - void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, + void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, hwaddr *mmio32, hwaddr *mmio64, unsigned n_dma, uint32_t *liobns, Error **errp); - sPAPRResizeHPT resize_hpt_default; - sPAPRCapabilities default_caps; - sPAPRIrq *irq; + SpaprResizeHpt resize_hpt_default; + SpaprCapabilities default_caps; + SpaprIrq *irq; }; /** - * sPAPRMachineState: + * SpaprMachineState: */ -struct sPAPRMachineState { +struct SpaprMachineState { /*< private >*/ MachineState parent_obj; - struct VIOsPAPRBus *vio_bus; - QLIST_HEAD(, sPAPRPHBState) phbs; - struct sPAPRNVRAM *nvram; + struct SpaprVioBus *vio_bus; + QLIST_HEAD(, SpaprPhbState) phbs; + struct SpaprNvram *nvram; ICSState *ics; - sPAPRRTCState rtc; + SpaprRtcState rtc; - sPAPRResizeHPT resize_hpt; + SpaprResizeHpt resize_hpt; void *htab; uint32_t htab_shift; uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ - sPAPRPendingHPT *pending_hpt; /* in-progress resize */ + SpaprPendingHpt *pending_hpt; /* in-progress resize */ hwaddr rma_size; int vrma_adjust; @@ -155,15 +164,15 @@ struct sPAPRMachineState { uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ Notifier epow_notifier; - QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; + QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; bool use_hotplug_event_source; - sPAPREventSource *event_sources; + SpaprEventSource *event_sources; /* ibm,client-architecture-support option negotiation */ bool cas_reboot; bool cas_legacy_guest_workaround; - sPAPROptionVector *ov5; /* QEMU-supported option vectors */ - sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ + SpaprOptionVector *ov5; /* QEMU-supported option vectors */ + SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ uint32_t max_compat_pvr; /* Migration state */ @@ -174,7 +183,7 @@ struct sPAPRMachineState { /* Pending DIMM unplug cache. It is populated when a LMB * unplug starts. It can be regenerated if a migration * occurs during the unplug process. */ - QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; + QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; /*< public >*/ char *kvm_type; @@ -183,12 +192,12 @@ struct sPAPRMachineState { int32_t irq_map_nr; unsigned long *irq_map; - sPAPRXive *xive; - sPAPRIrq *irq; + SpaprXive *xive; + SpaprIrq *irq; qemu_irq *qirqs; bool cmd_line_caps[SPAPR_CAP_NUM]; - sPAPRCapabilities def, eff, mig; + SpaprCapabilities def, eff, mig; }; #define H_SUCCESS 0 @@ -337,9 +346,11 @@ struct sPAPRMachineState { #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) +#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) +#define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) /* Each control block has to be on a 4K boundary */ #define H_CB_ALIGNMENT 4096 @@ -492,16 +503,16 @@ struct sPAPRMachineState { #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT -typedef struct sPAPRDeviceTreeUpdateHeader { +typedef struct SpaprDeviceTreeUpdateHeader { uint32_t version_id; -} sPAPRDeviceTreeUpdateHeader; +} SpaprDeviceTreeUpdateHeader; #define hcall_dprintf(fmt, ...) \ do { \ qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ } while (0) -typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, +typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, target_ulong opcode, target_ulong *args); @@ -655,16 +666,16 @@ static inline void rtas_st(target_ulong phys, int n, uint32_t val) stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); } -typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, +typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets); void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); -target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, +target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, uint32_t token, uint32_t nargs, target_ulong args, uint32_t nret, target_ulong rets); void spapr_dt_rtas_tokens(void *fdt, int rtas); -void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); +void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); #define SPAPR_TCE_PAGE_SHIFT 12 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) @@ -691,17 +702,17 @@ static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) intspec[1] = is_lsi ? cpu_to_be32(1) : 0; } -typedef struct sPAPRTCETable sPAPRTCETable; +typedef struct SpaprTceTable SpaprTceTable; #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" #define SPAPR_TCE_TABLE(obj) \ - OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) + OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" #define SPAPR_IOMMU_MEMORY_REGION(obj) \ OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) -struct sPAPRTCETable { +struct SpaprTceTable { DeviceState parent; uint32_t liobn; uint32_t nb_table; @@ -712,76 +723,77 @@ struct sPAPRTCETable { uint64_t *mig_table; bool bypass; bool need_vfio; + bool skipping_replay; int fd; MemoryRegion root; IOMMUMemoryRegion iommu; - struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ - QLIST_ENTRY(sPAPRTCETable) list; + struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ + QLIST_ENTRY(SpaprTceTable) list; }; -sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); +SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); -struct sPAPREventLogEntry { +struct SpaprEventLogEntry { uint32_t summary; uint32_t extended_length; void *extended_log; - QTAILQ_ENTRY(sPAPREventLogEntry) next; + QTAILQ_ENTRY(SpaprEventLogEntry) next; }; -void spapr_events_init(sPAPRMachineState *sm); -void spapr_dt_events(sPAPRMachineState *sm, void *fdt); -int spapr_h_cas_compose_response(sPAPRMachineState *sm, +void spapr_events_init(SpaprMachineState *sm); +void spapr_dt_events(SpaprMachineState *sm, void *fdt); +int spapr_h_cas_compose_response(SpaprMachineState *sm, target_ulong addr, target_ulong size, - sPAPROptionVector *ov5_updates); -void close_htab_fd(sPAPRMachineState *spapr); -void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); -void spapr_free_hpt(sPAPRMachineState *spapr); -sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); -void spapr_tce_table_enable(sPAPRTCETable *tcet, + SpaprOptionVector *ov5_updates); +void close_htab_fd(SpaprMachineState *spapr); +void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); +void spapr_free_hpt(SpaprMachineState *spapr); +SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); +void spapr_tce_table_enable(SpaprTceTable *tcet, uint32_t page_shift, uint64_t bus_offset, uint32_t nb_table); -void spapr_tce_table_disable(sPAPRTCETable *tcet); -void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); +void spapr_tce_table_disable(SpaprTceTable *tcet); +void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); -MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); +MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); int spapr_dma_dt(void *fdt, int node_off, const char *propname, uint32_t liobn, uint64_t window, uint32_t size); int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, - sPAPRTCETable *tcet); + SpaprTceTable *tcet); void spapr_pci_switch_vga(bool big_endian); -void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); -void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); -void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, +void spapr_hotplug_req_add_by_index(SpaprDrc *drc); +void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); +void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, uint32_t count); -void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, +void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, uint32_t count); -void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, +void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, uint32_t count, uint32_t index); -void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, +void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, uint32_t count, uint32_t index); int spapr_hpt_shift_for_ramsize(uint64_t ramsize); -void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, +void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); -void spapr_clear_pending_events(sPAPRMachineState *spapr); -int spapr_max_server_number(sPAPRMachineState *spapr); +void spapr_clear_pending_events(SpaprMachineState *spapr); +int spapr_max_server_number(SpaprMachineState *spapr); /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); -int spapr_core_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, +int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, void *fdt, int *fdt_start_offset, Error **errp); void spapr_lmb_release(DeviceState *dev); -int spapr_lmb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, +int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, void *fdt, int *fdt_start_offset, Error **errp); void spapr_phb_release(DeviceState *dev); -int spapr_phb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, +int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, void *fdt, int *fdt_start_offset, Error **errp); -void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); -int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); +void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); +int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); #define TYPE_SPAPR_RNG "spapr-rng" -#define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ +#define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ /* * This defines the maximum number of DIMM slots we can have for sPAPR @@ -828,19 +840,21 @@ extern const VMStateDescription vmstate_spapr_cap_cfpc; extern const VMStateDescription vmstate_spapr_cap_sbbc; extern const VMStateDescription vmstate_spapr_cap_ibs; extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; +extern const VMStateDescription vmstate_spapr_cap_large_decr; +extern const VMStateDescription vmstate_spapr_cap_ccf_assist; -static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap) +static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) { return spapr->eff.caps[cap]; } -void spapr_caps_init(sPAPRMachineState *spapr); -void spapr_caps_apply(sPAPRMachineState *spapr); -void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu); -void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); -int spapr_caps_post_migration(sPAPRMachineState *spapr); +void spapr_caps_init(SpaprMachineState *spapr); +void spapr_caps_apply(SpaprMachineState *spapr); +void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); +void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp); +int spapr_caps_post_migration(SpaprMachineState *spapr); -void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, +void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, Error **errp); /* * XIVE definitions |