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path: root/include/hw/pci-host/pnv_phb3.h
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Diffstat (limited to 'include/hw/pci-host/pnv_phb3.h')
-rw-r--r--include/hw/pci-host/pnv_phb3.h20
1 files changed, 13 insertions, 7 deletions
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index 75b787867a..182f29d681 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -13,6 +13,7 @@
#include "hw/pci/pcie_host.h"
#include "hw/pci/pcie_port.h"
#include "hw/ppc/xics.h"
+#include "qom/object.h"
typedef struct PnvPHB3 PnvPHB3;
@@ -20,18 +21,20 @@ typedef struct PnvPHB3 PnvPHB3;
* PHB3 XICS Source for MSIs
*/
#define TYPE_PHB3_MSI "phb3-msi"
-#define PHB3_MSI(obj) OBJECT_CHECK(Phb3MsiState, (obj), TYPE_PHB3_MSI)
+typedef struct Phb3MsiState Phb3MsiState;
+DECLARE_INSTANCE_CHECKER(Phb3MsiState, PHB3_MSI,
+ TYPE_PHB3_MSI)
#define PHB3_MAX_MSI 2048
-typedef struct Phb3MsiState {
+struct Phb3MsiState {
ICSState ics;
qemu_irq *qirqs;
PnvPHB3 *phb;
uint64_t rba[PHB3_MAX_MSI / 64];
uint32_t rba_sum;
-} Phb3MsiState;
+};
void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
uint32_t count);
@@ -69,9 +72,11 @@ typedef struct PnvPhb3DMASpace {
* PHB3 Power Bus Common Queue
*/
#define TYPE_PNV_PBCQ "pnv-pbcq"
-#define PNV_PBCQ(obj) OBJECT_CHECK(PnvPBCQState, (obj), TYPE_PNV_PBCQ)
+typedef struct PnvPBCQState PnvPBCQState;
+DECLARE_INSTANCE_CHECKER(PnvPBCQState, PNV_PBCQ,
+ TYPE_PNV_PBCQ)
-typedef struct PnvPBCQState {
+struct PnvPBCQState {
DeviceState parent;
uint32_t nest_xbase;
@@ -96,7 +101,7 @@ typedef struct PnvPBCQState {
MemoryRegion xscom_nest_regs;
MemoryRegion xscom_pci_regs;
MemoryRegion xscom_spci_regs;
-} PnvPBCQState;
+};
/*
* PHB3 PCIe Root port
@@ -113,7 +118,8 @@ typedef struct PnvPHB3RootPort {
* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
*/
#define TYPE_PNV_PHB3 "pnv-phb3"
-#define PNV_PHB3(obj) OBJECT_CHECK(PnvPHB3, (obj), TYPE_PNV_PHB3)
+DECLARE_INSTANCE_CHECKER(PnvPHB3, PNV_PHB3,
+ TYPE_PNV_PHB3)
#define PNV_PHB3_NUM_M64 16
#define PNV_PHB3_NUM_REGS (0x1000 >> 3)