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-rw-r--r--include/hw/intc/allwinner-a10-pic.h6
-rw-r--r--include/hw/intc/arm_gic.h6
-rw-r--r--include/hw/intc/arm_gic_common.h11
-rw-r--r--include/hw/intc/arm_gicv3.h6
-rw-r--r--include/hw/intc/arm_gicv3_common.h6
-rw-r--r--include/hw/intc/arm_gicv3_its_common.h3
-rw-r--r--include/hw/intc/armv7m_nvic.h6
-rw-r--r--include/hw/intc/aspeed_vic.h6
-rw-r--r--include/hw/intc/bcm2835_ic.h6
-rw-r--r--include/hw/intc/bcm2836_control.h6
-rw-r--r--include/hw/intc/heathrow_pic.h6
-rw-r--r--include/hw/intc/ibex_plic.h6
-rw-r--r--include/hw/intc/imx_avic.h6
-rw-r--r--include/hw/intc/imx_gpcv2.h6
-rw-r--r--include/hw/intc/intc.h5
-rw-r--r--include/hw/intc/mips_gic.h3
-rw-r--r--include/hw/intc/realview_gic.h6
-rw-r--r--include/hw/intc/rx_icu.h1
-rw-r--r--include/hw/intc/xlnx-pmu-iomod-intc.h6
-rw-r--r--include/hw/intc/xlnx-zynqmp-ipi.h6
20 files changed, 75 insertions, 38 deletions
diff --git a/include/hw/intc/allwinner-a10-pic.h b/include/hw/intc/allwinner-a10-pic.h
index a5895401d1..692d2a88d0 100644
--- a/include/hw/intc/allwinner-a10-pic.h
+++ b/include/hw/intc/allwinner-a10-pic.h
@@ -2,8 +2,10 @@
#define ALLWINNER_A10_PIC_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_AW_A10_PIC "allwinner-a10-pic"
+typedef struct AwA10PICState AwA10PICState;
#define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC)
#define AW_A10_PIC_VECTOR 0
@@ -19,7 +21,7 @@
#define AW_A10_PIC_INT_NR 95
#define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32)
-typedef struct AwA10PICState {
+struct AwA10PICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@@ -37,6 +39,6 @@ typedef struct AwA10PICState {
uint32_t enable[AW_A10_PIC_REG_NUM];
uint32_t mask[AW_A10_PIC_REG_NUM];
/*priority setting here*/
-} AwA10PICState;
+};
#endif
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index 303b9748cb..704ef2b751 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -65,6 +65,7 @@
#define HW_ARM_GIC_H
#include "arm_gic_common.h"
+#include "qom/object.h"
/* Number of SGI target-list bits */
#define GIC_TARGETLIST_BITS 8
@@ -72,6 +73,7 @@
#define GIC_MIN_PRIORITY_BITS 4
#define TYPE_ARM_GIC "arm_gic"
+typedef struct ARMGICClass ARMGICClass;
#define ARM_GIC(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
#define ARM_GIC_CLASS(klass) \
@@ -79,12 +81,12 @@
#define ARM_GIC_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
-typedef struct ARMGICClass {
+struct ARMGICClass {
/*< private >*/
ARMGICCommonClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
-} ARMGICClass;
+};
#endif
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index 6e0d6b8a88..2cbde9b7a9 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -22,6 +22,7 @@
#define HW_ARM_GIC_COMMON_H
#include "hw/sysbus.h"
+#include "qom/object.h"
/* Maximum number of possible interrupts, determined by the GIC architecture */
#define GIC_MAXIRQ 1020
@@ -61,7 +62,7 @@ typedef struct gic_irq_state {
uint8_t group;
} gic_irq_state;
-typedef struct GICState {
+struct GICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@@ -143,9 +144,11 @@ typedef struct GICState {
bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
int dev_fd; /* kvm device fd if backed by kvm vgic support */
Error *migration_blocker;
-} GICState;
+};
+typedef struct GICState GICState;
#define TYPE_ARM_GIC_COMMON "arm_gic_common"
+typedef struct ARMGICCommonClass ARMGICCommonClass;
#define ARM_GIC_COMMON(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
#define ARM_GIC_COMMON_CLASS(klass) \
@@ -153,14 +156,14 @@ typedef struct GICState {
#define ARM_GIC_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
-typedef struct ARMGICCommonClass {
+struct ARMGICCommonClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
void (*pre_save)(GICState *s);
void (*post_load)(GICState *s);
-} ARMGICCommonClass;
+};
void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
const MemoryRegionOps *ops,
diff --git a/include/hw/intc/arm_gicv3.h b/include/hw/intc/arm_gicv3.h
index 4a6fd85e22..58e9131a33 100644
--- a/include/hw/intc/arm_gicv3.h
+++ b/include/hw/intc/arm_gicv3.h
@@ -13,20 +13,22 @@
#define HW_ARM_GICV3_H
#include "arm_gicv3_common.h"
+#include "qom/object.h"
#define TYPE_ARM_GICV3 "arm-gicv3"
+typedef struct ARMGICv3Class ARMGICv3Class;
#define ARM_GICV3(obj) OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3)
#define ARM_GICV3_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMGICv3Class, (klass), TYPE_ARM_GICV3)
#define ARM_GICV3_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICv3Class, (obj), TYPE_ARM_GICV3)
-typedef struct ARMGICv3Class {
+struct ARMGICv3Class {
/*< private >*/
ARMGICv3CommonClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
-} ARMGICv3Class;
+};
#endif
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 31ec9a1ae4..86fb060320 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -26,6 +26,7 @@
#include "hw/sysbus.h"
#include "hw/intc/arm_gic_common.h"
+#include "qom/object.h"
/*
* Maximum number of possible interrupts, determined by the GIC architecture.
@@ -279,6 +280,7 @@ GICV3_BITMAP_ACCESSORS(level)
GICV3_BITMAP_ACCESSORS(edge_trigger)
#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
+typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
#define ARM_GICV3_COMMON(obj) \
OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
#define ARM_GICV3_COMMON_CLASS(klass) \
@@ -286,14 +288,14 @@ GICV3_BITMAP_ACCESSORS(edge_trigger)
#define ARM_GICV3_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
-typedef struct ARMGICv3CommonClass {
+struct ARMGICv3CommonClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
void (*pre_save)(GICv3State *s);
void (*post_load)(GICv3State *s);
-} ARMGICv3CommonClass;
+};
void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
const MemoryRegionOps *ops, Error **errp);
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
index fd1fe64c03..03a0fa335b 100644
--- a/include/hw/intc/arm_gicv3_its_common.h
+++ b/include/hw/intc/arm_gicv3_its_common.h
@@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "hw/intc/arm_gicv3_common.h"
+#include "qom/object.h"
#define ITS_CONTROL_SIZE 0x10000
#define ITS_TRANS_SIZE 0x10000
@@ -64,6 +65,7 @@ typedef struct GICv3ITSState GICv3ITSState;
void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
+typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
#define ARM_GICV3_ITS_COMMON(obj) \
OBJECT_CHECK(GICv3ITSState, (obj), TYPE_ARM_GICV3_ITS_COMMON)
#define ARM_GICV3_ITS_COMMON_CLASS(klass) \
@@ -81,6 +83,5 @@ struct GICv3ITSCommonClass {
void (*post_load)(GICv3ITSState *s);
};
-typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
#endif
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index a472c9b8f0..63098822fa 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -13,9 +13,11 @@
#include "target/arm/cpu.h"
#include "hw/sysbus.h"
#include "hw/timer/armv7m_systick.h"
+#include "qom/object.h"
#define TYPE_NVIC "armv7m_nvic"
+typedef struct NVICState NVICState;
#define NVIC(obj) \
OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
@@ -35,7 +37,7 @@ typedef struct VecInfo {
uint8_t level; /* exceptions <=15 never set level */
} VecInfo;
-typedef struct NVICState {
+struct NVICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@@ -88,6 +90,6 @@ typedef struct NVICState {
qemu_irq sysresetreq;
SysTickState systick[M_REG_NUM_BANKS];
-} NVICState;
+};
#endif
diff --git a/include/hw/intc/aspeed_vic.h b/include/hw/intc/aspeed_vic.h
index 107ff17c3b..f8844b3327 100644
--- a/include/hw/intc/aspeed_vic.h
+++ b/include/hw/intc/aspeed_vic.h
@@ -14,13 +14,15 @@
#define ASPEED_VIC_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_ASPEED_VIC "aspeed.vic"
+typedef struct AspeedVICState AspeedVICState;
#define ASPEED_VIC(obj) OBJECT_CHECK(AspeedVICState, (obj), TYPE_ASPEED_VIC)
#define ASPEED_VIC_NR_IRQS 51
-typedef struct AspeedVICState {
+struct AspeedVICState {
/*< private >*/
SysBusDevice parent_obj;
@@ -43,6 +45,6 @@ typedef struct AspeedVICState {
/* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
uint64_t event;
-} AspeedVICState;
+};
#endif /* ASPEED_VIC_H */
diff --git a/include/hw/intc/bcm2835_ic.h b/include/hw/intc/bcm2835_ic.h
index 392ded1cb3..4a9f093025 100644
--- a/include/hw/intc/bcm2835_ic.h
+++ b/include/hw/intc/bcm2835_ic.h
@@ -9,14 +9,16 @@
#define BCM2835_IC_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_BCM2835_IC "bcm2835-ic"
+typedef struct BCM2835ICState BCM2835ICState;
#define BCM2835_IC(obj) OBJECT_CHECK(BCM2835ICState, (obj), TYPE_BCM2835_IC)
#define BCM2835_IC_GPU_IRQ "gpu-irq"
#define BCM2835_IC_ARM_IRQ "arm-irq"
-typedef struct BCM2835ICState {
+struct BCM2835ICState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
@@ -30,6 +32,6 @@ typedef struct BCM2835ICState {
uint8_t arm_irq_level, arm_irq_enable;
bool fiq_enable;
uint8_t fiq_select;
-} BCM2835ICState;
+};
#endif
diff --git a/include/hw/intc/bcm2836_control.h b/include/hw/intc/bcm2836_control.h
index 2c22405686..7d8a51fc72 100644
--- a/include/hw/intc/bcm2836_control.h
+++ b/include/hw/intc/bcm2836_control.h
@@ -17,16 +17,18 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
+#include "qom/object.h"
/* 4 mailboxes per core, for 16 total */
#define BCM2836_NCORES 4
#define BCM2836_MBPERCORE 4
#define TYPE_BCM2836_CONTROL "bcm2836-control"
+typedef struct BCM2836ControlState BCM2836ControlState;
#define BCM2836_CONTROL(obj) \
OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
-typedef struct BCM2836ControlState {
+struct BCM2836ControlState {
/*< private >*/
SysBusDevice busdev;
/*< public >*/
@@ -56,6 +58,6 @@ typedef struct BCM2836ControlState {
/* outputs to CPU cores */
qemu_irq irq[BCM2836_NCORES];
qemu_irq fiq[BCM2836_NCORES];
-} BCM2836ControlState;
+};
#endif
diff --git a/include/hw/intc/heathrow_pic.h b/include/hw/intc/heathrow_pic.h
index b163e27ab9..bd9fc115a8 100644
--- a/include/hw/intc/heathrow_pic.h
+++ b/include/hw/intc/heathrow_pic.h
@@ -27,8 +27,10 @@
#define HW_INTC_HEATHROW_PIC_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_HEATHROW "heathrow"
+typedef struct HeathrowState HeathrowState;
#define HEATHROW(obj) OBJECT_CHECK(HeathrowState, (obj), TYPE_HEATHROW)
typedef struct HeathrowPICState {
@@ -38,13 +40,13 @@ typedef struct HeathrowPICState {
uint32_t level_triggered;
} HeathrowPICState;
-typedef struct HeathrowState {
+struct HeathrowState {
SysBusDevice parent_obj;
MemoryRegion mem;
HeathrowPICState pics[2];
qemu_irq irqs[1];
-} HeathrowState;
+};
#define HEATHROW_NUM_IRQS 64
diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
index d8eb09b258..0125b36267 100644
--- a/include/hw/intc/ibex_plic.h
+++ b/include/hw/intc/ibex_plic.h
@@ -20,12 +20,14 @@
#define HW_IBEX_PLIC_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_IBEX_PLIC "ibex-plic"
+typedef struct IbexPlicState IbexPlicState;
#define IBEX_PLIC(obj) \
OBJECT_CHECK(IbexPlicState, (obj), TYPE_IBEX_PLIC)
-typedef struct IbexPlicState {
+struct IbexPlicState {
/*< private >*/
SysBusDevice parent_obj;
@@ -59,6 +61,6 @@ typedef struct IbexPlicState {
uint32_t threshold_base;
uint32_t claim_base;
-} IbexPlicState;
+};
#endif /* HW_IBEX_PLIC_H */
diff --git a/include/hw/intc/imx_avic.h b/include/hw/intc/imx_avic.h
index 1b80769018..124f29f763 100644
--- a/include/hw/intc/imx_avic.h
+++ b/include/hw/intc/imx_avic.h
@@ -18,8 +18,10 @@
#define IMX_AVIC_H
#include "hw/sysbus.h"
+#include "qom/object.h"
#define TYPE_IMX_AVIC "imx.avic"
+typedef struct IMXAVICState IMXAVICState;
#define IMX_AVIC(obj) OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
#define IMX_AVIC_NUM_IRQS 64
@@ -36,7 +38,7 @@
#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
-typedef struct IMXAVICState{
+struct IMXAVICState {
/*< private >*/
SysBusDevice parent_obj;
@@ -50,6 +52,6 @@ typedef struct IMXAVICState{
qemu_irq irq;
qemu_irq fiq;
uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
-} IMXAVICState;
+};
#endif /* IMX_AVIC_H */
diff --git a/include/hw/intc/imx_gpcv2.h b/include/hw/intc/imx_gpcv2.h
index ed978b24bb..66befda3fd 100644
--- a/include/hw/intc/imx_gpcv2.h
+++ b/include/hw/intc/imx_gpcv2.h
@@ -2,19 +2,21 @@
#define IMX_GPCV2_H
#include "hw/sysbus.h"
+#include "qom/object.h"
enum IMXGPCv2Registers {
GPC_NUM = 0xE00 / sizeof(uint32_t),
};
-typedef struct IMXGPCv2State {
+struct IMXGPCv2State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t regs[GPC_NUM];
-} IMXGPCv2State;
+};
+typedef struct IMXGPCv2State IMXGPCv2State;
#define TYPE_IMX_GPCV2 "imx-gpcv2"
#define IMX_GPCV2(obj) OBJECT_CHECK(IMXGPCv2State, (obj), TYPE_IMX_GPCV2)
diff --git a/include/hw/intc/intc.h b/include/hw/intc/intc.h
index fb3e8e621f..b51c0ac0f4 100644
--- a/include/hw/intc/intc.h
+++ b/include/hw/intc/intc.h
@@ -5,6 +5,7 @@
#define TYPE_INTERRUPT_STATS_PROVIDER "intctrl"
+typedef struct InterruptStatsProviderClass InterruptStatsProviderClass;
#define INTERRUPT_STATS_PROVIDER_CLASS(klass) \
OBJECT_CLASS_CHECK(InterruptStatsProviderClass, (klass), \
TYPE_INTERRUPT_STATS_PROVIDER)
@@ -17,7 +18,7 @@
typedef struct InterruptStatsProvider InterruptStatsProvider;
-typedef struct InterruptStatsProviderClass {
+struct InterruptStatsProviderClass {
InterfaceClass parent;
/* The returned pointer and statistics must remain valid until
@@ -26,6 +27,6 @@ typedef struct InterruptStatsProviderClass {
bool (*get_statistics)(InterruptStatsProvider *obj, uint64_t **irq_counts,
unsigned int *nb_irqs);
void (*print_info)(InterruptStatsProvider *obj, Monitor *mon);
-} InterruptStatsProviderClass;
+};
#endif
diff --git a/include/hw/intc/mips_gic.h b/include/hw/intc/mips_gic.h
index 8428287bf9..5670421e62 100644
--- a/include/hw/intc/mips_gic.h
+++ b/include/hw/intc/mips_gic.h
@@ -15,6 +15,7 @@
#include "hw/timer/mips_gictimer.h"
#include "hw/sysbus.h"
#include "cpu.h"
+#include "qom/object.h"
/*
* GIC Specific definitions
*/
@@ -170,13 +171,13 @@
#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
#define TYPE_MIPS_GIC "mips-gic"
+typedef struct MIPSGICState MIPSGICState;
#define MIPS_GIC(obj) OBJECT_CHECK(MIPSGICState, (obj), TYPE_MIPS_GIC)
/* Support up to 32 VPs and 256 IRQs */
#define GIC_MAX_VPS 32
#define GIC_MAX_INTRS 256
-typedef struct MIPSGICState MIPSGICState;
typedef struct MIPSGICIRQState MIPSGICIRQState;
typedef struct MIPSGICVPState MIPSGICVPState;
diff --git a/include/hw/intc/realview_gic.h b/include/hw/intc/realview_gic.h
index 1783ea11b9..e633992b9c 100644
--- a/include/hw/intc/realview_gic.h
+++ b/include/hw/intc/realview_gic.h
@@ -12,17 +12,19 @@
#include "hw/sysbus.h"
#include "hw/intc/arm_gic.h"
+#include "qom/object.h"
#define TYPE_REALVIEW_GIC "realview_gic"
+typedef struct RealViewGICState RealViewGICState;
#define REALVIEW_GIC(obj) \
OBJECT_CHECK(RealViewGICState, (obj), TYPE_REALVIEW_GIC)
-typedef struct RealViewGICState {
+struct RealViewGICState {
SysBusDevice parent_obj;
MemoryRegion container;
GICState gic;
-} RealViewGICState;
+};
#endif
diff --git a/include/hw/intc/rx_icu.h b/include/hw/intc/rx_icu.h
index 7176015cd9..5660cb4e7f 100644
--- a/include/hw/intc/rx_icu.h
+++ b/include/hw/intc/rx_icu.h
@@ -22,6 +22,7 @@
#define HW_INTC_RX_ICU_H
#include "hw/sysbus.h"
+#include "qom/object.h"
enum TRG_MODE {
TRG_LEVEL = 0,
diff --git a/include/hw/intc/xlnx-pmu-iomod-intc.h b/include/hw/intc/xlnx-pmu-iomod-intc.h
index 0bd118884a..fce35ac941 100644
--- a/include/hw/intc/xlnx-pmu-iomod-intc.h
+++ b/include/hw/intc/xlnx-pmu-iomod-intc.h
@@ -27,16 +27,18 @@
#include "hw/sysbus.h"
#include "hw/register.h"
+#include "qom/object.h"
#define TYPE_XLNX_PMU_IO_INTC "xlnx.pmu_io_intc"
+typedef struct XlnxPMUIOIntc XlnxPMUIOIntc;
#define XLNX_PMU_IO_INTC(obj) \
OBJECT_CHECK(XlnxPMUIOIntc, (obj), TYPE_XLNX_PMU_IO_INTC)
/* This is R_PIT3_CONTROL + 1 */
#define XLNXPMUIOINTC_R_MAX (0x78 + 1)
-typedef struct XlnxPMUIOIntc {
+struct XlnxPMUIOIntc {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -52,6 +54,6 @@ typedef struct XlnxPMUIOIntc {
uint32_t regs[XLNXPMUIOINTC_R_MAX];
RegisterInfo regs_info[XLNXPMUIOINTC_R_MAX];
-} XlnxPMUIOIntc;
+};
#endif /* HW_INTC_XLNX_PMU_IOMOD_INTC_H */
diff --git a/include/hw/intc/xlnx-zynqmp-ipi.h b/include/hw/intc/xlnx-zynqmp-ipi.h
index 866c719c6f..9044ca5afe 100644
--- a/include/hw/intc/xlnx-zynqmp-ipi.h
+++ b/include/hw/intc/xlnx-zynqmp-ipi.h
@@ -27,9 +27,11 @@
#include "hw/sysbus.h"
#include "hw/register.h"
+#include "qom/object.h"
#define TYPE_XLNX_ZYNQMP_IPI "xlnx.zynqmp_ipi"
+typedef struct XlnxZynqMPIPI XlnxZynqMPIPI;
#define XLNX_ZYNQMP_IPI(obj) \
OBJECT_CHECK(XlnxZynqMPIPI, (obj), TYPE_XLNX_ZYNQMP_IPI)
@@ -38,7 +40,7 @@
#define NUM_IPIS 11
-typedef struct XlnxZynqMPIPI {
+struct XlnxZynqMPIPI {
/* Private */
SysBusDevice parent_obj;
@@ -51,6 +53,6 @@ typedef struct XlnxZynqMPIPI {
uint32_t regs[R_XLNX_ZYNQMP_IPI_MAX];
RegisterInfo regs_info[R_XLNX_ZYNQMP_IPI_MAX];
-} XlnxZynqMPIPI;
+};
#endif /* XLNX_ZYNQMP_IPI_H */
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-23 23:47:21 +0000