diff options
Diffstat (limited to 'include/hw/arm')
27 files changed, 123 insertions, 66 deletions
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 77c82a9982..631454f1c7 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -14,6 +14,7 @@ #include "hw/rtc/allwinner-rtc.h" #include "target/arm/cpu.h" +#include "qom/object.h" #define AW_A10_SDRAM_BASE 0x40000000 @@ -21,9 +22,10 @@ #define AW_A10_NUM_USB 2 #define TYPE_AW_A10 "allwinner-a10" +typedef struct AwA10State AwA10State; #define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10) -typedef struct AwA10State { +struct AwA10State { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -38,6 +40,6 @@ typedef struct AwA10State { MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; OHCISysBusState ohci[AW_A10_NUM_USB]; -} AwA10State; +}; #endif diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 626139dcb3..5fda95066f 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -106,6 +106,7 @@ enum { #define TYPE_AW_H3 "allwinner-h3" /** Convert input object to Allwinner H3 state object */ +typedef struct AwH3State AwH3State; #define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) /** @} */ @@ -116,7 +117,7 @@ enum { * This struct contains the state of all the devices * which are currently emulated by the H3 SoC code. */ -typedef struct AwH3State { +struct AwH3State { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -136,7 +137,7 @@ typedef struct AwH3State { MemoryRegion sram_a1; MemoryRegion sram_a2; MemoryRegion sram_c; -} AwH3State; +}; /** * Emulate Boot ROM firmware setup functionality. diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 347b977ae5..e5788e9d3c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -105,8 +105,11 @@ #include "hw/or-irq.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" +#include "qom/object.h" #define TYPE_ARM_SSE "arm-sse" +typedef struct ARMSSE ARMSSE; +typedef struct ARMSSEClass ARMSSEClass; #define ARM_SSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARM_SSE) /* @@ -140,7 +143,7 @@ #define RAM3_PPU 6 #define NUM_PPUS 7 -typedef struct ARMSSE { +struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -215,14 +218,14 @@ typedef struct ARMSSE { uint32_t init_svtor; bool cpu_fpu[SSE_MAX_CPUS]; bool cpu_dsp[SSE_MAX_CPUS]; -} ARMSSE; +}; typedef struct ARMSSEInfo ARMSSEInfo; -typedef struct ARMSSEClass { +struct ARMSSEClass { SysBusDeviceClass parent_class; const ARMSSEInfo *info; -} ARMSSEClass; +}; #define ARM_SSE_CLASS(klass) \ OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARM_SSE) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index a30e3c6471..c820d32ad5 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -13,11 +13,13 @@ #include "hw/sysbus.h" #include "hw/intc/armv7m_nvic.h" #include "target/arm/idau.h" +#include "qom/object.h" #define TYPE_BITBAND "ARM,bitband-memory" +typedef struct BitBandState BitBandState; #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) -typedef struct { +struct BitBandState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ @@ -26,9 +28,10 @@ typedef struct { MemoryRegion iomem; uint32_t base; MemoryRegion *source_memory; -} BitBandState; +}; #define TYPE_ARMV7M "armv7m" +typedef struct ARMv7MState ARMv7MState; #define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M) #define ARMV7M_NUM_BITBANDS 2 @@ -49,7 +52,7 @@ typedef struct { * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO */ -typedef struct ARMv7MState { +struct ARMv7MState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ @@ -72,6 +75,6 @@ typedef struct ARMv7MState { bool start_powered_off; bool vfp; bool dsp; -} ARMv7MState; +}; #endif diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 09da9d9acc..4e5ec37acb 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -10,10 +10,12 @@ #define ARM_ASPEED_H #include "hw/boards.h" +#include "qom/object.h" typedef struct AspeedMachineState AspeedMachineState; #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") +typedef struct AspeedMachineClass AspeedMachineClass; #define ASPEED_MACHINE(obj) \ OBJECT_CHECK(AspeedMachineState, (obj), TYPE_ASPEED_MACHINE) @@ -27,7 +29,7 @@ typedef struct AspeedMachineState AspeedMachineState; #define ASPEED_MACHINE_GET_CLASS(obj) \ OBJECT_GET_CLASS(AspeedMachineClass, (obj), TYPE_ASPEED_MACHINE) -typedef struct AspeedMachineClass { +struct AspeedMachineClass { MachineClass parent_obj; const char *name; @@ -40,7 +42,7 @@ typedef struct AspeedMachineClass { uint32_t num_cs; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); -} AspeedMachineClass; +}; #endif diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index d46f197cbe..31679ee42e 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -27,6 +27,7 @@ #include "hw/gpio/aspeed_gpio.h" #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" +#include "qom/object.h" #define ASPEED_SPIS_NUM 2 #define ASPEED_EHCIS_NUM 2 @@ -34,7 +35,7 @@ #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 4 -typedef struct AspeedSoCState { +struct AspeedSoCState { /*< private >*/ DeviceState parent; @@ -60,12 +61,14 @@ typedef struct AspeedSoCState { AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; AspeedSDHCIState emmc; -} AspeedSoCState; +}; +typedef struct AspeedSoCState AspeedSoCState; #define TYPE_ASPEED_SOC "aspeed-soc" +typedef struct AspeedSoCClass AspeedSoCClass; #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) -typedef struct AspeedSoCClass { +struct AspeedSoCClass { DeviceClass parent_class; const char *name; @@ -79,7 +82,7 @@ typedef struct AspeedSoCClass { const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; -} AspeedSoCClass; +}; #define ASPEED_SOC_CLASS(klass) \ OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h index 48a0ad1633..67f5a5f8f5 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -29,12 +29,14 @@ #include "hw/timer/bcm2835_systmr.h" #include "hw/usb/hcd-dwc2.h" #include "hw/misc/unimp.h" +#include "qom/object.h" #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" +typedef struct BCM2835PeripheralState BCM2835PeripheralState; #define BCM2835_PERIPHERALS(obj) \ OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS) -typedef struct BCM2835PeripheralState { +struct BCM2835PeripheralState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ @@ -70,6 +72,6 @@ typedef struct BCM2835PeripheralState { UnimplementedDeviceState smi; DWC2State dwc2; UnimplementedDeviceState sdramc; -} BCM2835PeripheralState; +}; #endif /* BCM2835_PERIPHERALS_H */ diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 79dfff9d73..cf22dc96a0 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -15,8 +15,11 @@ #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" #include "target/arm/cpu.h" +#include "qom/object.h" #define TYPE_BCM283X "bcm283x" +typedef struct BCM283XClass BCM283XClass; +typedef struct BCM283XState BCM283XState; #define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) #define BCM283X_NCPUS 4 @@ -28,7 +31,7 @@ #define TYPE_BCM2836 "bcm2836" #define TYPE_BCM2837 "bcm2837" -typedef struct BCM283XState { +struct BCM283XState { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -40,14 +43,14 @@ typedef struct BCM283XState { } cpu[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; -} BCM283XState; +}; typedef struct BCM283XInfo BCM283XInfo; -typedef struct BCM283XClass { +struct BCM283XClass { DeviceClass parent_class; const BCM283XInfo *info; -} BCM283XClass; +}; #define BCM283X_CLASS(klass) \ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h index 63785baaa8..f77833f6e3 100644 --- a/include/hw/arm/digic.h +++ b/include/hw/arm/digic.h @@ -21,14 +21,16 @@ #include "cpu.h" #include "hw/timer/digic-timer.h" #include "hw/char/digic-uart.h" +#include "qom/object.h" #define TYPE_DIGIC "digic" +typedef struct DigicState DigicState; #define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC) #define DIGIC4_NB_TIMERS 3 -typedef struct DigicState { +struct DigicState { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -37,6 +39,6 @@ typedef struct DigicState { DigicTimerState timer[DIGIC4_NB_TIMERS]; DigicUartState uart; -} DigicState; +}; #endif /* HW_ARM_DIGIC_H */ diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 55260394af..114c594cd2 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -27,6 +27,7 @@ #include "hw/or-irq.h" #include "hw/sysbus.h" #include "target/arm/cpu-qom.h" +#include "qom/object.h" #define EXYNOS4210_NCPUS 2 @@ -85,7 +86,7 @@ typedef struct Exynos4210Irq { qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; } Exynos4210Irq; -typedef struct Exynos4210State { +struct Exynos4210State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ @@ -101,7 +102,8 @@ typedef struct Exynos4210State { MemoryRegion bootreg_mem; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; -} Exynos4210State; +}; +typedef struct Exynos4210State Exynos4210State; #define TYPE_EXYNOS4210_SOC "exynos4210" #define EXYNOS4210_SOC(obj) \ diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 54ee1bfd78..8b4c974f09 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -32,8 +32,10 @@ #include "hw/watchdog/wdt_imx2.h" #include "exec/memory.h" #include "target/arm/cpu.h" +#include "qom/object.h" #define TYPE_FSL_IMX25 "fsl,imx25" +typedef struct FslIMX25State FslIMX25State; #define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25) #define FSL_IMX25_NUM_UARTS 5 @@ -44,7 +46,7 @@ #define FSL_IMX25_NUM_ESDHCS 2 #define FSL_IMX25_NUM_USBS 2 -typedef struct FslIMX25State { +struct FslIMX25State { /*< private >*/ DeviceState parent_obj; @@ -66,7 +68,7 @@ typedef struct FslIMX25State { MemoryRegion iram; MemoryRegion iram_alias; uint32_t phy_num; -} FslIMX25State; +}; /** * i.MX25 memory map diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index dd8561b309..12368f2c8f 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -28,8 +28,10 @@ #include "hw/watchdog/wdt_imx2.h" #include "exec/memory.h" #include "target/arm/cpu.h" +#include "qom/object.h" #define TYPE_FSL_IMX31 "fsl,imx31" +typedef struct FslIMX31State FslIMX31State; #define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31) #define FSL_IMX31_NUM_UARTS 2 @@ -37,7 +39,7 @@ #define FSL_IMX31_NUM_I2CS 3 #define FSL_IMX31_NUM_GPIOS 3 -typedef struct FslIMX31State { +struct FslIMX31State { /*< private >*/ DeviceState parent_obj; @@ -55,7 +57,7 @@ typedef struct FslIMX31State { MemoryRegion rom; MemoryRegion iram; MemoryRegion iram_alias; -} FslIMX31State; +}; #define FSL_IMX31_SECURE_ROM_ADDR 0x00000000 #define FSL_IMX31_SECURE_ROM_SIZE 0x4000 diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 162fe99375..e66ea1e917 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -34,8 +34,10 @@ #include "hw/usb/imx-usb-phy.h" #include "exec/memory.h" #include "cpu.h" +#include "qom/object.h" #define TYPE_FSL_IMX6 "fsl,imx6" +typedef struct FslIMX6State FslIMX6State; #define FSL_IMX6(obj) OBJECT_CHECK(FslIMX6State, (obj), TYPE_FSL_IMX6) #define FSL_IMX6_NUM_CPUS 4 @@ -49,7 +51,7 @@ #define FSL_IMX6_NUM_USB_PHYS 2 #define FSL_IMX6_NUM_USBS 4 -typedef struct FslIMX6State { +struct FslIMX6State { /*< private >*/ DeviceState parent_obj; @@ -74,7 +76,7 @@ typedef struct FslIMX6State { MemoryRegion ocram; MemoryRegion ocram_alias; uint32_t phy_num; -} FslIMX6State; +}; #define FSL_IMX6_MMDC_ADDR 0x10000000 diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index fcbaf3dc86..e95c4820c6 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -38,8 +38,10 @@ #include "hw/usb/imx-usb-phy.h" #include "exec/memory.h" #include "cpu.h" +#include "qom/object.h" #define TYPE_FSL_IMX6UL "fsl,imx6ul" +typedef struct FslIMX6ULState FslIMX6ULState; #define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL) enum FslIMX6ULConfiguration { @@ -60,7 +62,7 @@ enum FslIMX6ULConfiguration { FSL_IMX6UL_NUM_USBS = 2, }; -typedef struct FslIMX6ULState { +struct FslIMX6ULState { /*< private >*/ DeviceState parent_obj; @@ -89,7 +91,7 @@ typedef struct FslIMX6ULState { MemoryRegion ocram_alias; uint32_t phy_num[FSL_IMX6UL_NUM_ETHS]; -} FslIMX6ULState; +}; enum FslIMX6ULMemoryMap { FSL_IMX6UL_MMDC_ADDR = 0x80000000, diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index ad88923707..8095e5544b 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -39,8 +39,10 @@ #include "hw/pci-host/designware.h" #include "hw/usb/chipidea.h" #include "cpu.h" +#include "qom/object.h" #define TYPE_FSL_IMX7 "fsl,imx7" +typedef struct FslIMX7State FslIMX7State; #define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7) enum FslIMX7Configuration { @@ -59,7 +61,7 @@ enum FslIMX7Configuration { FSL_IMX7_NUM_ADCS = 2, }; -typedef struct FslIMX7State { +struct FslIMX7State { /*< private >*/ DeviceState parent_obj; @@ -82,7 +84,7 @@ typedef struct FslIMX7State { ChipideaState usb[FSL_IMX7_NUM_USBS]; DesignwarePCIEHost pcie; uint32_t phy_num[FSL_IMX7_NUM_ETHS]; -} FslIMX7State; +}; enum FslIMX7MemoryMap { FSL_IMX7_MMDC_ADDR = 0x80000000, diff --git a/include/hw/arm/linux-boot-if.h b/include/hw/arm/linux-boot-if.h index 7bbdfd1cc6..6d9e13fd36 100644 --- a/include/hw/arm/linux-boot-if.h +++ b/include/hw/arm/linux-boot-if.h @@ -9,6 +9,7 @@ #include "qom/object.h" #define TYPE_ARM_LINUX_BOOT_IF "arm-linux-boot-if" +typedef struct ARMLinuxBootIfClass ARMLinuxBootIfClass; #define ARM_LINUX_BOOT_IF_CLASS(klass) \ OBJECT_CLASS_CHECK(ARMLinuxBootIfClass, (klass), TYPE_ARM_LINUX_BOOT_IF) #define ARM_LINUX_BOOT_IF_GET_CLASS(obj) \ @@ -18,7 +19,7 @@ typedef struct ARMLinuxBootIf ARMLinuxBootIf; -typedef struct ARMLinuxBootIfClass { +struct ARMLinuxBootIfClass { /*< private >*/ InterfaceClass parent_class; @@ -35,6 +36,6 @@ typedef struct ARMLinuxBootIfClass { * (or for a CPU which doesn't support TrustZone) */ void (*arm_linux_init)(ARMLinuxBootIf *obj, bool secure_boot); -} ARMLinuxBootIfClass; +}; #endif diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index c9cb214aa6..b4bc5ef96a 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -30,8 +30,10 @@ #include "hw/misc/msf2-sysreg.h" #include "hw/ssi/mss-spi.h" #include "hw/net/msf2-emac.h" +#include "qom/object.h" #define TYPE_MSF2_SOC "msf2-soc" +typedef struct MSF2State MSF2State; #define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) #define MSF2_NUM_SPIS 2 @@ -44,7 +46,7 @@ */ #define MSF2_NUM_TIMERS 2 -typedef struct MSF2State { +struct MSF2State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ @@ -64,6 +66,6 @@ typedef struct MSF2State { MSSTimerState timer; MSSSpiState spi[MSF2_NUM_SPIS]; MSF2EmacState emac; -} MSF2State; +}; #endif diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 0cb78aafea..727ac1ae04 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -17,14 +17,16 @@ #include "hw/gpio/nrf51_gpio.h" #include "hw/nvram/nrf51_nvm.h" #include "hw/timer/nrf51_timer.h" +#include "qom/object.h" #define TYPE_NRF51_SOC "nrf51-soc" +typedef struct NRF51State NRF51State; #define NRF51_SOC(obj) \ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) #define NRF51_NUM_TIMERS 3 -typedef struct NRF51State { +struct NRF51State { /*< private >*/ SysBusDevice parent_obj; @@ -50,6 +52,6 @@ typedef struct NRF51State { MemoryRegion container; -} NRF51State; +}; #endif diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 6be386d0e2..0d365edeec 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -24,6 +24,7 @@ #include "hw/input/tsc2xxx.h" #include "target/arm/cpu-qom.h" #include "qemu/log.h" +#include "qom/object.h" # define OMAP_EMIFS_BASE 0x00000000 # define OMAP2_Q0_BASE 0x00000000 @@ -69,10 +70,10 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent); /* omap_intc.c */ #define TYPE_OMAP_INTC "common-omap-intc" +typedef struct omap_intr_handler_s omap_intr_handler; #define OMAP_INTC(obj) \ OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC) -typedef struct omap_intr_handler_s omap_intr_handler; /* * TODO: Ideally we should have a clock framework that @@ -93,9 +94,9 @@ void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); /* omap_i2c.c */ #define TYPE_OMAP_I2C "omap_i2c" +typedef struct OMAPI2CState OMAPI2CState; #define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C) -typedef struct OMAPI2CState OMAPI2CState; /* TODO: clock framework (see above) */ void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index 09c1336071..b2f9a41468 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -13,6 +13,7 @@ #include "exec/memory.h" #include "target/arm/cpu-qom.h" #include "hw/pcmcia.h" +#include "qom/object.h" /* Interrupt numbers */ # define PXA2XX_PIC_SSP3 0 diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 880dccd7c0..b6b51a1cb1 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -21,6 +21,7 @@ #include "hw/sysbus.h" #include "hw/pci/pci.h" +#include "qom/object.h" #define SMMU_PCI_BUS_MAX 256 #define SMMU_PCI_DEVFN_MAX 256 @@ -102,7 +103,7 @@ typedef struct SMMUIOTLBKey { uint8_t level; } SMMUIOTLBKey; -typedef struct SMMUState { +struct SMMUState { /* <private> */ SysBusDevice dev; const char *mrtypename; @@ -116,9 +117,10 @@ typedef struct SMMUState { QLIST_HEAD(, SMMUDevice) devices_with_notifiers; uint8_t bus_num; PCIBus *primary_bus; -} SMMUState; +}; +typedef struct SMMUState SMMUState; -typedef struct { +struct SMMUBaseClass { /* <private> */ SysBusDeviceClass parent_class; @@ -126,7 +128,8 @@ typedef struct { DeviceRealize parent_realize; -} SMMUBaseClass; +}; +typedef struct SMMUBaseClass SMMUBaseClass; #define TYPE_ARM_SMMU "arm-smmu" #define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 68d7a963e0..698b89d234 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -21,6 +21,7 @@ #include "hw/arm/smmu-common.h" #include "hw/registerfields.h" +#include "qom/object.h" #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" @@ -32,7 +33,7 @@ typedef struct SMMUQueue { uint8_t log2size; } SMMUQueue; -typedef struct SMMUv3State { +struct SMMUv3State { SMMUState smmu_state; uint32_t features; @@ -61,7 +62,8 @@ typedef struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; -} SMMUv3State; +}; +typedef struct SMMUv3State SMMUv3State; typedef enum { SMMU_IRQ_EVTQ, @@ -70,14 +72,15 @@ typedef enum { SMMU_IRQ_GERROR, } SMMUIrq; -typedef struct { +struct SMMUv3Class { /*< private >*/ SMMUBaseClass smmu_base_class; /*< public >*/ DeviceRealize parent_realize; DeviceReset parent_reset; -} SMMUv3Class; +}; +typedef struct SMMUv3Class SMMUv3Class; #define TYPE_ARM_SMMUV3 "arm-smmuv3" #define ARM_SMMUV3(obj) OBJECT_CHECK(SMMUv3State, (obj), TYPE_ARM_SMMUV3) diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 922a733f88..6d86937e07 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -32,8 +32,10 @@ #include "hw/or-irq.h" #include "hw/ssi/stm32f2xx_spi.h" #include "hw/arm/armv7m.h" +#include "qom/object.h" #define TYPE_STM32F205_SOC "stm32f205-soc" +typedef struct STM32F205State STM32F205State; #define STM32F205_SOC(obj) \ OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC) @@ -47,7 +49,7 @@ #define SRAM_BASE_ADDRESS 0x20000000 #define SRAM_SIZE (128 * 1024) -typedef struct STM32F205State { +struct STM32F205State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ @@ -63,6 +65,6 @@ typedef struct STM32F205State { STM32F2XXSPIState spi[STM_NUM_SPIS]; qemu_or_irq *adc_irqs; -} STM32F205State; +}; #endif diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 1fe97f8c3a..8f44fb2046 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -33,8 +33,10 @@ #include "hw/or-irq.h" #include "hw/ssi/stm32f2xx_spi.h" #include "hw/arm/armv7m.h" +#include "qom/object.h" #define TYPE_STM32F405_SOC "stm32f405-soc" +typedef struct STM32F405State STM32F405State; #define STM32F405_SOC(obj) \ OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) @@ -48,7 +50,7 @@ #define SRAM_BASE_ADDRESS 0x20000000 #define SRAM_SIZE (192 * 1024) -typedef struct STM32F405State { +struct STM32F405State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ @@ -68,6 +70,6 @@ typedef struct STM32F405State { MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; -} STM32F405State; +}; #endif diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index dff67e1bef..49ad860943 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -37,6 +37,7 @@ #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" +#include "qom/object.h" #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 @@ -115,7 +116,7 @@ typedef struct MemMapEntry { hwaddr size; } MemMapEntry; -typedef struct { +struct VirtMachineClass { MachineClass parent; bool disallow_affinity_adjustment; bool no_its; @@ -126,9 +127,10 @@ typedef struct { bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ bool kvm_no_adjvtime; bool acpi_expose_flash; -} VirtMachineClass; +}; +typedef struct VirtMachineClass VirtMachineClass; -typedef struct { +struct VirtMachineState { MachineState parent; Notifier machine_done; DeviceState *platform_bus_dev; @@ -162,7 +164,8 @@ typedef struct { DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; -} VirtMachineState; +}; +typedef struct VirtMachineState VirtMachineState; #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 9c9f47ba9d..a960619ec9 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -20,8 +20,10 @@ #include "hw/dma/xlnx-zdma.h" #include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" +#include "qom/object.h" #define TYPE_XLNX_VERSAL "xlnx-versal" +typedef struct Versal Versal; #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) #define XLNX_VERSAL_NR_ACPUS 2 @@ -31,7 +33,7 @@ #define XLNX_VERSAL_NR_SDS 2 #define XLNX_VERSAL_NR_IRQS 192 -typedef struct Versal { +struct Versal { /*< private >*/ SysBusDevice parent_obj; @@ -74,7 +76,7 @@ typedef struct Versal { MemoryRegion *mr_ddr; uint32_t psci_conduit; } cfg; -} Versal; +}; /* Memory-map and IRQ definitions. Copied a subset from * auto-generated files. */ diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 53076fa29a..6a24216abf 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -32,8 +32,10 @@ #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "hw/cpu/cluster.h" #include "target/arm/cpu.h" +#include "qom/object.h" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" +typedef struct XlnxZynqMPState XlnxZynqMPState; #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ TYPE_XLNX_ZYNQMP) @@ -73,7 +75,7 @@ #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) -typedef struct XlnxZynqMPState { +struct XlnxZynqMPState { /*< private >*/ DeviceState parent_obj; @@ -112,6 +114,6 @@ typedef struct XlnxZynqMPState { bool virt; /* Has the RPU subsystem? */ bool has_rpu; -} XlnxZynqMPState; +}; #endif |