diff options
Diffstat (limited to 'hw')
308 files changed, 3617 insertions, 940 deletions
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index e2317be546..f82e9512fd 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -1,5 +1,4 @@ #include "qemu/osdep.h" -#include "hw/boards.h" #include "migration/vmstate.h" #include "hw/acpi/cpu.h" #include "qapi/error.h" diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 5454be67d5..39c825763a 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -11,7 +11,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "hw/acpi/acpi.h" #include "hw/acpi/generic_event_device.h" #include "hw/irq.h" diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 853447cf9d..4daa79ec8d 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -35,7 +35,6 @@ #include "sysemu/runstate.h" #include "hw/acpi/acpi.h" #include "hw/acpi/tco.h" -#include "exec/address-spaces.h" #include "hw/i386/ich9.h" #include "hw/mem/pc-dimm.h" diff --git a/hw/acpi/memory_hotplug.c b/hw/acpi/memory_hotplug.c index 0bdcf15528..af37889423 100644 --- a/hw/acpi/memory_hotplug.c +++ b/hw/acpi/memory_hotplug.c @@ -2,7 +2,6 @@ #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/pc-hotplug.h" #include "hw/mem/pc-dimm.h" -#include "hw/boards.h" #include "hw/qdev-core.h" #include "migration/vmstate.h" #include "trace.h" diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index f4cb3c979d..4999277d57 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -31,7 +31,6 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" #include "hw/acpi/acpi.h" -#include "exec/address-spaces.h" #include "hw/pci/pci_bus.h" #include "migration/vmstate.h" #include "qapi/error.h" diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 8f8b0e95e5..0bd23d74e2 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -33,7 +33,6 @@ #include "sysemu/xen.h" #include "qapi/error.h" #include "qemu/range.h" -#include "exec/address-spaces.h" #include "hw/acpi/pcihp.h" #include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index c8e300d93f..1017ecf330 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -13,7 +13,6 @@ #include "hw/loader.h" #include "alpha_sys.h" #include "qemu/error-report.h" -#include "sysemu/sysemu.h" #include "hw/rtc/mc146818rtc.h" #include "hw/ide/pci.h" #include "hw/timer/i8254.h" diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index a42b319812..87020cbe0d 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -11,10 +11,8 @@ #include "qemu/units.h" #include "qapi/error.h" #include "cpu.h" -#include "hw/boards.h" #include "hw/irq.h" #include "alpha_sys.h" -#include "exec/address-spaces.h" #include "qom/object.h" diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8c37cf00da..b887f6a5b1 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -142,6 +142,7 @@ config PXA2XX select SD select SSI select USB_OHCI + select PCMCIA config GUMSTIX bool diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index d404f31e02..05e84728cb 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -16,10 +16,8 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/allwinner-a10.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 88259a9c0d..27f1070145 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -18,13 +18,11 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/units.h" #include "hw/qdev-core.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/char/serial.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 6dd10d8470..af0d935bf7 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "hw/arm/armv7m.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/loader.h" @@ -19,7 +18,6 @@ #include "sysemu/reset.h" #include "qemu/error-report.h" #include "qemu/module.h" -#include "exec/address-spaces.h" #include "target/arm/idau.h" /* Bitbanded IO. Each word corresponds to a single bit. */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a17b75f494..3fe6c55744 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -11,20 +11,15 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "exec/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" -#include "hw/boards.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/misc/pca9552.h" #include "hw/misc/tmp105.h" #include "hw/misc/led.h" #include "hw/qdev-properties.h" -#include "qemu/log.h" #include "sysemu/block-backend.h" -#include "sysemu/sysemu.h" #include "hw/loader.h" #include "qemu/error-report.h" #include "qemu/units.h" @@ -138,6 +133,19 @@ struct AspeedMachineState { /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 +/* Quanta-Q71l hardware value */ +#define QUANTA_Q71L_BMC_HW_STRAP1 ( \ + SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ + SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ + SCU_AST2400_HW_STRAP_ACPI_DIS | \ + SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ + SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ + SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) + /* AST2600 evb hardware value */ #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 @@ -146,6 +154,10 @@ struct AspeedMachineState { #define TACOMA_BMC_HW_STRAP1 0x00000000 #define TACOMA_BMC_HW_STRAP2 0x00000040 +/* Rainier hardware value: (QEMU prototype) */ +#define RAINIER_BMC_HW_STRAP1 0x00000000 +#define RAINIER_BMC_HW_STRAP2 0x00000000 + /* * The max ram region is for firmwares that scan the address space * with load/store to guess how much RAM the SoC has. @@ -327,7 +339,7 @@ static void aspeed_machine_init(MachineState *machine) object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, &error_abort); object_property_set_link(OBJECT(&bmc->soc), "dram", - OBJECT(&bmc->ram_container), &error_abort); + OBJECT(machine->ram), &error_abort); if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot @@ -433,6 +445,34 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); } +static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = &bmc->soc; + + /* + * The quanta-q71l platform expects tmp75s which are compatible with + * tmp105s. + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); + + /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ + /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ + /* TODO: Add Memory Riser i2c mux and eeproms. */ + + /* TODO: i2c-2: pca9546@74 */ + /* TODO: i2c-2: pca9548@77 */ + /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ + /* TODO: i2c-7: Add pca9546@70 */ + /* - i2c@0: pmbus@59 */ + /* - i2c@1: pmbus@58 */ + /* - i2c@2: pmbus@58 */ + /* - i2c@3: pmbus@59 */ + /* TODO: i2c-7: Add PDB FRU eeprom@52 */ + /* TODO: i2c-8: Add BMC FRU eeprom@50 */ +} + static void ast2500_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = &bmc->soc; @@ -629,6 +669,58 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc) eeprom_buf); } +static void rainier_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = &bmc->soc; + + /* The rainier expects a TMP275 but a TMP105 is compatible */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, + 0x49); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, + 0x4a); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, + 0x49); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, + 0x4a); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, + 0x4b); + + /* Bus 7: TODO dps310@76 */ + /* Bus 7: TODO max31785@52 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61); + /* Bus 7: TODO si7021-a20@20 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, + 0x48); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, + 0x4a); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); + /* Bus 8: ucd90320@11 */ + /* Bus 8: ucd90320@b */ + /* Bus 8: ucd90320@c */ + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, + 0x49); +} + static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -728,6 +820,23 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; +static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; + amc->soc_name = "ast2400-a1"; + amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; + amc->fmc_model = "n25q256a"; + amc->spi_model = "mx25l25635e"; + amc->num_cs = 1; + amc->i2c_init = quanta_q71l_bmc_i2c_init; + mc->default_ram_size = 128 * MiB; + mc->default_cpus = mc->min_cpus = mc->max_cpus = + aspeed_soc_num_cpus(amc->soc_name); +} + static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, void *data) { @@ -811,6 +920,9 @@ static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 512 * MiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); + + mc->deprecation_reason = "redundant system. Please use a similar " + "OpenPOWER BMC, Witherspoon or Romulus."; }; static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) @@ -886,6 +998,25 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; +static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "IBM Rainier BMC (Cortex A7)"; + amc->soc_name = "ast2600-a1"; + amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; + amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; + amc->fmc_model = "mx66l1g45g"; + amc->spi_model = "mx66l1g45g"; + amc->num_cs = 2; + amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->i2c_init = rainier_bmc_i2c_init; + mc->default_ram_size = 1 * GiB; + mc->default_cpus = mc->min_cpus = mc->max_cpus = + aspeed_soc_num_cpus(amc->soc_name); +}; + static const TypeInfo aspeed_machine_types[] = { { .name = MACHINE_TYPE_NAME("palmetto-bmc"), @@ -928,6 +1059,14 @@ static const TypeInfo aspeed_machine_types[] = { .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_g220a_class_init, }, { + .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_quanta_q71l_class_init, + }, { + .name = MACHINE_TYPE_NAME("rainier-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_rainier_class_init, + }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, .instance_size = sizeof(AspeedMachineState), diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index bc87e754a3..e3013128c6 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -9,12 +9,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "exec/address-spaces.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" #include "hw/char/serial.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" @@ -42,6 +39,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_DEV_ETH2] = 0x1E680000, [ASPEED_DEV_ETH4] = 0x1E690000, [ASPEED_DEV_VIC] = 0x1E6C0000, + [ASPEED_DEV_HACE] = 0x1E6D0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, [ASPEED_DEV_XDMA] = 0x1E6E7000, @@ -102,6 +100,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ [ASPEED_DEV_ETH1] = 2, [ASPEED_DEV_ETH2] = 3, + [ASPEED_DEV_HACE] = 4, [ASPEED_DEV_ETH3] = 32, [ASPEED_DEV_ETH4] = 33, [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ @@ -185,7 +184,8 @@ static void aspeed_soc_ast2600_init(Object *obj) object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); } - object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); + object_initialize_child(obj, "xdma", &s->xdma, typename); snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); @@ -213,6 +213,9 @@ static void aspeed_soc_ast2600_init(Object *obj) TYPE_SYSBUS_SDHCI); object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); + + snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); + object_initialize_child(obj, "hace", &s->hace, typename); } /* @@ -344,10 +347,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); - if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", - sc->memmap[ASPEED_DEV_SDRAM], errp)) { - return; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } @@ -498,6 +497,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); + + /* HACE */ + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); } static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 057d053c84..3ad6c56fa9 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -12,12 +12,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "exec/address-spaces.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" #include "hw/char/serial.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" @@ -34,6 +31,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { [ASPEED_DEV_VIC] = 0x1E6C0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, + [ASPEED_DEV_HACE] = 0x1E6E3000, [ASPEED_DEV_XDMA] = 0x1E6E7000, [ASPEED_DEV_VIDEO] = 0x1E700000, [ASPEED_DEV_ADC] = 0x1E6E9000, @@ -65,6 +63,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { [ASPEED_DEV_VIC] = 0x1E6C0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, + [ASPEED_DEV_HACE] = 0x1E6E3000, [ASPEED_DEV_XDMA] = 0x1E6E7000, [ASPEED_DEV_ADC] = 0x1E6E9000, [ASPEED_DEV_VIDEO] = 0x1E700000, @@ -117,6 +116,7 @@ static const int aspeed_soc_ast2400_irqmap[] = { [ASPEED_DEV_ETH2] = 3, [ASPEED_DEV_XDMA] = 6, [ASPEED_DEV_SDHCI] = 26, + [ASPEED_DEV_HACE] = 4, }; #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap @@ -196,7 +196,8 @@ static void aspeed_soc_init(Object *obj) TYPE_FTGMAC100); } - object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); + object_initialize_child(obj, "xdma", &s->xdma, typename); snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); @@ -212,6 +213,9 @@ static void aspeed_soc_init(Object *obj) } object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); + + snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); + object_initialize_child(obj, "hace", &s->hace, typename); } static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -301,10 +305,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); - if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", - sc->memmap[ASPEED_DEV_SDRAM], errp)) { - return; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } @@ -425,6 +425,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); + + /* HACE */ + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); } static Property aspeed_soc_properties[] = { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index de7ade2878..24354338ca 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e56c42ac22..d7b059225e 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -25,7 +25,6 @@ #include "sysemu/device_tree.h" #include "qemu/config-file.h" #include "qemu/option.h" -#include "exec/address-spaces.h" #include "qemu/units.h" /* Kernel boot protocol is specified in the kernel docs diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 9d0d728180..294ba5de6e 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -16,11 +16,7 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "qapi/error.h" -#include "cpu.h" -#include "sysemu/sysemu.h" -#include "hw/sysbus.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 6cdc1d83fc..b771a3d8b7 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -27,14 +27,11 @@ #include "qapi/error.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "hw/arm/digic.h" #include "hw/block/flash.h" #include "hw/loader.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "qemu/units.h" #include "qemu/cutils.h" diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index ced2769b10..5c7a51bbad 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu/log.h" #include "cpu.h" #include "hw/cpu/a9mpcore.h" #include "hw/irq.h" diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 56b729141b..35dd9875da 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -25,8 +25,6 @@ #include "qemu/units.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "cpu.h" -#include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/boot.h" diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 08a98f828f..24c4374590 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -24,10 +24,8 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/fsl-imx25.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "chardev/char.h" diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 0983998bb4..def27bb913 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/fsl-imx31.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index bf886268c5..c3cb315dbc 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -29,7 +29,6 @@ #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "hw/char/pl011.h" #include "hw/ide/ahci.h" @@ -170,7 +169,7 @@ struct HighbankRegsState { uint32_t regs[NUM_REGS]; }; -static VMStateDescription vmstate_highbank_regs = { +static const VMStateDescription vmstate_highbank_regs = { .name = "highbank-regs", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 1c201d0d8e..bd16acd4d9 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -25,12 +25,10 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" #include "hw/boards.h" #include "qemu/error-report.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "hw/i2c/i2c.h" #include "qemu/cutils.h" @@ -67,7 +65,6 @@ static struct arm_boot_info imx25_pdk_binfo; static void imx25_pdk_init(MachineState *machine) { - MachineClass *mc = MACHINE_GET_CLASS(machine); IMX25PDK *s = g_new0(IMX25PDK, 1); unsigned int ram_size; unsigned int alias_offset; @@ -79,8 +76,8 @@ static void imx25_pdk_init(MachineState *machine) /* We need to initialize our memory */ if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) { - char *sz = size_to_str(mc->default_ram_size); - error_report("Invalid RAM size, should be %s", sz); + char *sz = size_to_str(FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE); + error_report("RAM size more than %s is not supported", sz); g_free(sz); exit(EXIT_FAILURE); } diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index e3f7d4ead2..39559c44c2 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -15,7 +15,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/fsl-imx31.h" #include "hw/boards.h" #include "qemu/error-report.h" diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index ed69a7b037..ce16b6b317 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -15,7 +15,6 @@ #include "hw/arm/fsl-imx6ul.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index e57d52b344..e896222c34 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -17,7 +17,6 @@ #include "hw/arm/fsl-imx7.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 25016e464d..70aa31a7f6 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -55,6 +55,7 @@ #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "sysemu/reset.h" #include "hw/misc/unimp.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/timer/cmsdk-apb-timer.h" @@ -72,6 +73,7 @@ #include "hw/core/split-irq.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/irq.h" #define MPS2TZ_NUMIRQ_MAX 96 #define MPS2TZ_RAM_MAX 5 @@ -153,6 +155,9 @@ struct MPS2TZMachineState { SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; Clock *s32kclk; + + bool remap; + qemu_irq remap_irq; }; #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -228,6 +233,10 @@ static const RAMInfo an505_raminfo[] = { { }, }; +/* + * Note that the addresses and MPC numbering here should match up + * with those used in remap_memory(), which can swap the BRAM and QSPI. + */ static const RAMInfo an524_raminfo[] = { { .name = "bram", .base = 0x00000000, @@ -457,6 +466,7 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); sccdev = DEVICE(scc); + qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); @@ -573,6 +583,52 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } +static hwaddr boot_mem_base(MPS2TZMachineState *mms) +{ + /* + * Return the canonical address of the block which will be mapped + * at address 0x0 (i.e. where the vector table is). + * This is usually 0, but if the AN524 alternate memory map is + * enabled it will be the base address of the QSPI block. + */ + return mms->remap ? 0x28000000 : 0; +} + +static void remap_memory(MPS2TZMachineState *mms, int map) +{ + /* + * Remap the memory for the AN524. 'map' is the value of + * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 + * for the "option 1" mapping where QSPI is at address 0. + * + * Effectively we need to swap around the "upstream" ends of + * MPC 0 and MPC 1. + */ + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + int i; + + if (mmc->fpga_type != FPGA_AN524) { + return; + } + + memory_region_transaction_begin(); + for (i = 0; i < 2; i++) { + TZMPC *mpc = &mms->mpc[i]; + MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); + hwaddr addr = (i ^ map) ? 0x28000000 : 0; + + memory_region_set_address(upstream, addr); + } + memory_region_transaction_commit(); +} + +static void remap_irq_fn(void *opaque, int n, int level) +{ + MPS2TZMachineState *mms = opaque; + + remap_memory(mms, level); +} + static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) @@ -711,7 +767,7 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); for (p = mmc->raminfo; p->name; p++) { - if (p->base == 0) { + if (p->base == boot_mem_base(mms)) { return p->size; } } @@ -1095,6 +1151,16 @@ static void mps2tz_common_init(MachineState *machine) create_non_mpc_ram(mms); + if (mmc->fpga_type == FPGA_AN524) { + /* + * Connect the line from the SCC so that we can remap when the + * guest updates that register. + */ + mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); + qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, + mms->remap_irq); + } + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, boot_ram_size(mms)); } @@ -1117,12 +1183,47 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, *iregion = region; } +static char *mps2_get_remap(Object *obj, Error **errp) +{ + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); + const char *val = mms->remap ? "QSPI" : "BRAM"; + return g_strdup(val); +} + +static void mps2_set_remap(Object *obj, const char *value, Error **errp) +{ + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); + + if (!strcmp(value, "BRAM")) { + mms->remap = false; + } else if (!strcmp(value, "QSPI")) { + mms->remap = true; + } else { + error_setg(errp, "Invalid remap value"); + error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); + } +} + +static void mps2_machine_reset(MachineState *machine) +{ + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); + + /* + * Set the initial memory mapping before triggering the reset of + * the rest of the system, so that the guest image loader and CPU + * reset see the correct mapping. + */ + remap_memory(mms, mms->remap); + qemu_devices_reset(); +} + static void mps2tz_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); mc->init = mps2tz_common_init; + mc->reset = mps2_machine_reset; iic->check = mps2_tz_idau_check; } @@ -1225,6 +1326,11 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) mmc->raminfo = an524_raminfo; mmc->armsse_type = TYPE_SSE200; mps2tz_set_default_ram_info(mmc); + + object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); + object_class_property_set_description(oc, "remap", + "Set memory mapping. Valid values " + "are BRAM (default) and QSPI."); } static void mps3tz_an547_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index d2c29e82d1..5cfe7caf83 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -27,7 +27,6 @@ #include "qapi/error.h" #include "exec/address-spaces.h" #include "hw/char/serial.h" -#include "hw/irq.h" #include "hw/arm/msf2-soc.h" #include "hw/misc/unimp.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index f9b61c36dd..343ec977c0 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -31,7 +31,6 @@ #include "hw/arm/boot.h" #include "exec/address-spaces.h" #include "hw/arm/msf2-soc.h" -#include "cpu.h" #define DDR_BASE_ADDRESS 0xA0000000 #define DDR_SIZE (64 * MiB) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 9cebece2de..2d612cc0c9 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -19,7 +19,6 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/char/serial.h" -#include "hw/hw.h" #include "qemu/timer.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" @@ -32,7 +31,6 @@ #include "sysemu/block-backend.h" #include "sysemu/runstate.h" #include "sysemu/dma.h" -#include "exec/address-spaces.h" #include "ui/pixel_ops.h" #include "qemu/cutils.h" #include "qom/object.h" diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 495b0f8e91..2ab0080e0b 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -16,7 +16,6 @@ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/npcm7xx.h" #include "hw/char/serial.h" diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index e22fe4bf8f..d4553e3786 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -16,7 +16,6 @@ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "hw/arm/npcm7xx.h" #include "hw/core/cpu.h" #include "hw/i2c/smbus_eeprom.h" @@ -27,7 +26,6 @@ #include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" -#include "sysemu/sysemu.h" #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index e15981e019..9407c2f268 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -13,9 +13,7 @@ #include "hw/arm/boot.h" #include "hw/sysbus.h" #include "hw/misc/unimp.h" -#include "exec/address-spaces.h" #include "qemu/log.h" -#include "cpu.h" #include "hw/arm/nrf51.h" #include "hw/arm/nrf51_soc.h" diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 387eea4d44..0aefa5d0f3 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -43,7 +43,6 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "qemu/log.h" -#include "exec/address-spaces.h" /* Nokia N8x0 support */ struct n800_s { diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 02c0f66431..180d3788f8 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -24,7 +24,6 @@ #include "qemu-common.h" #include "cpu.h" #include "exec/address-spaces.h" -#include "hw/boards.h" #include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 16d388fc79..02b1aa8c97 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -27,7 +27,6 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "hw/boards.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 40cdb5c6d2..0cf9895ce7 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -21,12 +21,9 @@ #include "qemu/units.h" #include "exec/address-spaces.h" #include "qapi/error.h" -#include "cpu.h" -#include "hw/sysbus.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" -#include "sysemu/sysemu.h" static struct arm_boot_info orangepi_binfo = { .nb_cpus = AW_H3_NUM_CPUS, diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 4e3dc5fbbf..68e11dd1ec 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -29,7 +29,6 @@ #include "hw/input/tsc2xxx.h" #include "hw/irq.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "cpu.h" #include "qemu/cutils.h" #include "qom/object.h" diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index cf6cb2a373..ed032fed54 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -301,7 +301,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) return dev; } -static VMStateDescription vmstate_pxa2xx_pic_regs = { +static const VMStateDescription vmstate_pxa2xx_pic_regs = { .name = "pxa2xx_pic", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 990509d385..b30a17871f 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -16,14 +16,12 @@ #include "qemu/units.h" #include "qemu/cutils.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/bcm2836.h" #include "hw/registerfields.h" #include "qemu/error-report.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/arm/boot.h" -#include "sysemu/sysemu.h" #include "qom/object.h" #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 0831159d15..1c54316ba3 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -20,7 +20,6 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/i2c/i2c.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "hw/char/pl011.h" #include "hw/cpu/a9mpcore.h" diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index a3dbf85e0e..42348e5cb1 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -15,7 +15,6 @@ #include "hw/arm/fsl-imx6.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 88dfb2284c..43c19b4923 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -27,7 +27,6 @@ #include "sysemu/numa.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 84d2c62c26..0459850a93 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -17,7 +17,6 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "trace.h" #include "exec/target_page.h" #include "hw/core/cpu.h" diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 228dc54b0b..7bed2ac520 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -23,7 +23,6 @@ #include "migration/vmstate.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" -#include "exec/address-spaces.h" #include "cpu.h" #include "trace.h" #include "qemu/log.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 6b3bf9828b..b45a929cbd 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -1134,7 +1134,7 @@ static bool is_version_0(void *opaque, int version_id) return version_id == 0; } -static VMStateDescription vmstate_sl_nand_info = { +static const VMStateDescription vmstate_sl_nand_info = { .name = "sl-nand", .version_id = 0, .minimum_version_id = 0, @@ -1170,7 +1170,7 @@ static const TypeInfo sl_nand_info = { .class_init = sl_nand_class_init, }; -static VMStateDescription vmstate_spitz_kbd = { +static const VMStateDescription vmstate_spitz_kbd = { .name = "spitz-keyboard", .version_id = 1, .minimum_version_id = 0, diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 27292ec411..8b4dab9b79 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -27,7 +27,6 @@ #include "migration/vmstate.h" #include "hw/misc/unimp.h" #include "hw/qdev-clock.h" -#include "cpu.h" #include "qom/object.h" #define GPIO_A 0 diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index c7ca54bcea..939a57dda5 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -30,7 +30,6 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "cpu.h" -#include "hw/boards.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" @@ -207,7 +206,7 @@ static int strongarm_pic_post_load(void *opaque, int version_id) return 0; } -static VMStateDescription vmstate_strongarm_pic_regs = { +static const VMStateDescription vmstate_strongarm_pic_regs = { .name = "strongarm_pic", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 1ea5534626..575399c4fc 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -21,7 +21,6 @@ #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/irq.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "hw/block/flash.h" #include "qemu/error-report.h" #include "hw/char/pl011.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 326a1a6db5..58481c0762 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -35,7 +35,6 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "hw/block/flash.h" #include "sysemu/device_tree.h" #include "qemu/error-report.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index fee696fb0e..0a78532018 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -36,7 +36,6 @@ #include "monitor/qdev.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "hw/boards.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/arm/virt.h" @@ -48,11 +47,9 @@ #include "sysemu/device_tree.h" #include "sysemu/numa.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "sysemu/tpm.h" #include "sysemu/kvm.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "qemu/bitops.h" #include "qemu/error-report.h" #include "qemu/module.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8db6cfd47f..81af32dc42 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -22,7 +22,6 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "net/net.h" -#include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/block/flash.h" @@ -119,7 +118,7 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) qemu_check_nic_model(nd, TYPE_CADENCE_GEM); qdev_set_nic_properties(dev, nd); } - object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); + object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, base); diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 8482cd6196..5bca360dce 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -10,11 +10,9 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "sysemu/device_tree.h" -#include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/arm/sysbus-fdt.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 79609692e4..fb776834f7 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "qemu/log.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "net/net.h" diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index a9db25eb99..6c6cb02e86 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -17,7 +17,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/xlnx-zynqmp.h" #include "hw/boards.h" #include "qemu/error-report.h" diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 7f01284a5c..3597e8db4d 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -18,11 +18,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/arm/xlnx-zynqmp.h" #include "hw/intc/arm_gic_common.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "kvm_arm.h" diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 5099bd8380..9c1e876207 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -162,7 +162,7 @@ static void zipit_lcd_realize(SSIPeripheral *dev, Error **errp) z->pos = 0; } -static VMStateDescription vmstate_zipit_lcd_state = { +static const VMStateDescription vmstate_zipit_lcd_state = { .name = "zipit-lcd", .version_id = 2, .minimum_version_id = 2, @@ -268,7 +268,7 @@ static uint8_t aer915_recv(I2CSlave *slave) return retval; } -static VMStateDescription vmstate_aer915_state = { +static const VMStateDescription vmstate_aer915_state = { .name = "aer915", .version_id = 1, .minimum_version_id = 1, diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 3ff31492fa..48ef478346 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "hw/boards.h" #include "atmega.h" #include "boot.h" #include "qom/object.h" diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 44c6afebbb..80b8a41cb5 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -18,7 +18,6 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qom/object.h" -#include "hw/boards.h" /* FIXME memory_region_allocate_system_memory for sram */ #include "hw/misc/unimp.h" #include "atmega.h" diff --git a/hw/block/ecc.c b/hw/block/ecc.c index 1a182367ee..6e0d63842c 100644 --- a/hw/block/ecc.c +++ b/hw/block/ecc.c @@ -78,7 +78,7 @@ void ecc_reset(ECCState *s) } /* Save/restore */ -VMStateDescription vmstate_ecc_state = { +const VMStateDescription vmstate_ecc_state = { .name = "ecc-state", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 183d3f44c2..b77503dc84 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -259,6 +259,8 @@ static const FlashPartInfo known_devices[] = { { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, + { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, + { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, /* Spansion -- single (large) sector size only, at least * for the chips listed here (without boot sectors). diff --git a/hw/block/nvme-subsys.c b/hw/block/nvme-subsys.c index 283a97b79d..9604c19117 100644 --- a/hw/block/nvme-subsys.c +++ b/hw/block/nvme-subsys.c @@ -17,7 +17,6 @@ #include "hw/block/block.h" #include "block/aio.h" #include "block/accounting.h" -#include "sysemu/sysemu.h" #include "hw/pci/pci.h" #include "nvme.h" #include "nvme-subsys.h" diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c index 8a002b0a19..2facf85c2d 100644 --- a/hw/char/mchp_pfsoc_mmuart.c +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "chardev/char.h" -#include "exec/address-spaces.h" #include "hw/char/mchp_pfsoc_mmuart.h" static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index ba1af1cfc4..ddae738d56 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" -#include "hw/sysbus.h" #include "hw/char/riscv_htif.h" #include "hw/char/serial.h" #include "chardev/char.h" diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 3a00ba7f00..fe12666789 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -19,10 +19,8 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" -#include "hw/sysbus.h" #include "chardev/char.h" #include "chardev/char-fe.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/char/sifive_uart.h" diff --git a/hw/char/spapr_vty.c b/hw/char/spapr_vty.c index 79eaa2fa52..91eae1a598 100644 --- a/hw/char/spapr_vty.c +++ b/hw/char/spapr_vty.c @@ -2,7 +2,6 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "cpu.h" #include "migration/vmstate.h" #include "chardev/char-fe.h" #include "hw/ppc/spapr.h" diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index b20038991a..dd6bc27b3b 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -28,7 +28,6 @@ #include "qemu/error-report.h" #include "qemu/queue.h" #include "hw/qdev-properties.h" -#include "hw/sysbus.h" #include "trace.h" #include "hw/virtio/virtio-serial.h" #include "hw/virtio/virtio-access.h" diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index 2b2a7b5e9a..d14f932eea 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -32,7 +32,6 @@ #include "qemu/osdep.h" #include "hw/core/cpu.h" -#include "hw/sysbus.h" #include "sysemu/dma.h" #include "sysemu/reset.h" #include "hw/boards.h" diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c index bde44e27b4..d3f9d1a06e 100644 --- a/hw/core/guest-loader.c +++ b/hw/core/guest-loader.c @@ -26,7 +26,6 @@ #include "qemu/osdep.h" #include "hw/core/cpu.h" -#include "hw/sysbus.h" #include "sysemu/dma.h" #include "hw/loader.h" #include "hw/qdev-properties.h" diff --git a/hw/core/loader.c b/hw/core/loader.c index d3e5f3b423..5b34869a54 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -57,7 +57,6 @@ #include "hw/loader.h" #include "hw/nvram/fw_cfg.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "hw/boards.h" #include "qemu/cutils.h" #include "sysemu/runstate.h" diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 68a942595a..a36c96608f 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/boards.h" #include "qapi/error.h" #include "qapi/qapi-builtin-visit.h" @@ -22,7 +21,6 @@ #include "sysemu/hw_accel.h" #include "sysemu/numa.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" static void cpustate_to_cpuinfo_s390(CpuInfoS390 *info, const CPUState *cpu) { diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 7e693523d7..f586a4bef5 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "hw/boards.h" -#include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "hw/core/cpu.h" diff --git a/hw/core/numa.c b/hw/core/numa.c index 68cee65f61..ac6bed5817 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -26,7 +26,6 @@ #include "qemu/units.h" #include "sysemu/hostmem.h" #include "sysemu/numa.h" -#include "sysemu/sysemu.h" #include "exec/cpu-common.h" #include "exec/ramlist.h" #include "qemu/bitmap.h" diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index af5a0e3517..d82050d927 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -34,7 +34,6 @@ #include "hw/loader.h" #include "elf.h" #include "boot.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "sysemu/sysemu.h" diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c index e2d895109d..dd6a1aa8ae 100644 --- a/hw/display/next-fb.c +++ b/hw/display/next-fb.c @@ -24,8 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "ui/console.h" -#include "hw/hw.h" -#include "hw/boards.h" #include "hw/loader.h" #include "framebuffer.h" #include "ui/pixel_ops.h" diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 93907e82a3..2ba75637ec 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -2384,7 +2384,7 @@ static bool qxl_monitors_config_needed(void *opaque) } -static VMStateDescription qxl_memslot = { +static const VMStateDescription qxl_memslot = { .name = "qxl-memslot", .version_id = QXL_SAVE_VERSION, .minimum_version_id = QXL_SAVE_VERSION, @@ -2396,7 +2396,7 @@ static VMStateDescription qxl_memslot = { } }; -static VMStateDescription qxl_surface = { +static const VMStateDescription qxl_surface = { .name = "qxl-surface", .version_id = QXL_SAVE_VERSION, .minimum_version_id = QXL_SAVE_VERSION, @@ -2414,7 +2414,7 @@ static VMStateDescription qxl_surface = { } }; -static VMStateDescription qxl_vmstate_monitors_config = { +static const VMStateDescription qxl_vmstate_monitors_config = { .name = "qxl/monitors-config", .version_id = 1, .minimum_version_id = 1, @@ -2425,7 +2425,7 @@ static VMStateDescription qxl_vmstate_monitors_config = { }, }; -static VMStateDescription qxl_vmstate = { +static const VMStateDescription qxl_vmstate = { .name = "qxl", .version_id = QXL_SAVE_VERSION, .minimum_version_id = QXL_SAVE_VERSION, diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index f1a586b1d7..2627307cc8 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "exec/address-spaces.h" #include "qemu/log.h" #include "qemu/module.h" #include "hw/dma/pl080.h" diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c index b3707ff3de..fa896f7edf 100644 --- a/hw/dma/pxa2xx_dma.c +++ b/hw/dma/pxa2xx_dma.c @@ -525,7 +525,7 @@ static bool is_version_0(void *opaque, int version_id) return version_id == 0; } -static VMStateDescription vmstate_pxa2xx_dma_chan = { +static const VMStateDescription vmstate_pxa2xx_dma_chan = { .name = "pxa2xx_dma_chan", .version_id = 1, .minimum_version_id = 1, @@ -540,7 +540,7 @@ static VMStateDescription vmstate_pxa2xx_dma_chan = { }, }; -static VMStateDescription vmstate_pxa2xx_dma = { +static const VMStateDescription vmstate_pxa2xx_dma = { .name = "pxa2xx_dma", .version_id = 1, .minimum_version_id = 0, diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index e1f6fedbda..9b2ac2017d 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 98324dadcd..797b4fed8f 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c index 5b82c9440d..eab96dd84e 100644 --- a/hw/hppa/dino.c +++ b/hw/hppa/dino.c @@ -14,13 +14,11 @@ #include "qemu/module.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "migration/vmstate.h" #include "hppa_sys.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c index 1a85657948..88c3791eb6 100644 --- a/hw/hppa/lasi.c +++ b/hw/hppa/lasi.c @@ -13,9 +13,7 @@ #include "qemu/units.h" #include "qemu/log.h" #include "qapi/error.h" -#include "cpu.h" #include "trace.h" -#include "hw/hw.h" #include "hw/irq.h" #include "sysemu/sysemu.h" #include "sysemu/runstate.h" @@ -24,7 +22,6 @@ #include "hw/char/parallel.h" #include "hw/char/serial.h" #include "hw/input/lasips2.h" -#include "exec/address-spaces.h" #include "migration/vmstate.h" #include "qom/object.h" diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index f2b71db9bd..2a46af5bc9 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -9,7 +9,6 @@ #include "cpu.h" #include "elf.h" #include "hw/loader.h" -#include "hw/boards.h" #include "qemu/error-report.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 518a3f5c6f..8d276d9ed3 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -601,7 +601,7 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, break; } - bus->dma_addr = value & 0xfffffffc; + bus->dma_addr = value & 0x3ffffffc; break; case I2CD_DMA_LEN: @@ -816,7 +816,8 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) return; } - address_space_init(&s->dram_as, s->dram_mr, "dma-dram"); + address_space_init(&s->dram_as, s->dram_mr, + TYPE_ASPEED_I2C "-dma-dram"); } } diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index 720d2331e9..845392505f 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" -#include "qemu/log.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "migration/vmstate.h" diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index de98750aef..bfecb0038c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -43,7 +43,6 @@ #include "sysemu/tpm.h" #include "hw/acpi/tpm.h" #include "hw/acpi/vmgenid.h" -#include "hw/boards.h" #include "sysemu/tpm_backend.h" #include "hw/rtc/mc146818rtc_regs.h" #include "migration/vmstate.h" diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c index ccd3303aac..1a0f77b911 100644 --- a/hw/i386/acpi-microvm.c +++ b/hw/i386/acpi-microvm.c @@ -30,7 +30,6 @@ #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/utils.h" -#include "hw/boards.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/microvm.h" #include "hw/pci/pci.h" diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6be8f32918..209b3f5553 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -24,14 +24,12 @@ #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "intel_iommu_internal.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" #include "hw/i386/pc.h" #include "hw/i386/apic-msidef.h" -#include "hw/boards.h" #include "hw/i386/x86-iommu.h" #include "hw/pci-host/q35.h" #include "sysemu/kvm.h" diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index 3dbff2be2e..52ff490910 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/i386/apic_internal.h" #include "hw/pci/msi.h" #include "sysemu/hw_accel.h" diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 51872dd84c..efbc1e0d12 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -14,7 +14,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/host-utils.h" #include "qemu/module.h" #include "sysemu/kvm.h" diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c index dfc3c98005..71a563181e 100644 --- a/hw/i386/kvm/ioapic.c +++ b/hw/i386/kvm/ioapic.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "monitor/monitor.h" #include "hw/i386/x86.h" -#include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/i386/ioapic_internal.h" #include "hw/i386/apic_internal.h" diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 46315445d2..43f8a8f679 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -11,7 +11,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" -#include "cpu.h" #include "sysemu/sysemu.h" #include "sysemu/cpus.h" #include "sysemu/hw_accel.h" diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index edf2b0f061..aba0c83219 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -49,7 +49,6 @@ #include "hw/pci-host/gpex.h" #include "hw/usb/xhci.h" -#include "cpu.h" #include "elf.h" #include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 364816efc9..8cfaf216e7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -65,7 +65,6 @@ #include "hw/xen/start_info.h" #include "ui/qemu-spice.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "sysemu/arch_init.h" #include "qemu/bitmap.h" #include "qemu/config-file.h" @@ -74,7 +73,6 @@ #include "qemu/cutils.h" #include "hw/acpi/acpi.h" #include "hw/acpi/cpu_hotplug.h" -#include "hw/boards.h" #include "acpi-build.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4e8edffeaf..5ac2edbf1f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -42,15 +42,12 @@ #include "hw/irq.h" #include "sysemu/kvm.h" #include "hw/kvm/clock.h" -#include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "sysemu/arch_init.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "hw/acpi/acpi.h" -#include "cpu.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 458ed41c65..46a0f196f4 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -38,7 +38,6 @@ #include "hw/kvm/clock.h" #include "hw/pci-host/q35.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" #include "hw/i386/ich9.h" diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 9fe72b370e..6ce37a2b05 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -35,7 +35,6 @@ #include "hw/i386/pc.h" #include "hw/loader.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "sysemu/sev.h" diff --git a/hw/i386/vmport.c b/hw/i386/vmport.c index 490a57f52c..7cc75dbc6d 100644 --- a/hw/i386/vmport.c +++ b/hw/i386/vmport.c @@ -37,7 +37,6 @@ #include "sysemu/hw_accel.h" #include "sysemu/qtest.h" #include "qemu/log.h" -#include "cpu.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index 5f4301639c..86ad03972e 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" -#include "hw/boards.h" #include "hw/i386/x86-iommu.h" #include "hw/qdev-properties.h" #include "hw/i386/pc.h" diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 7ce672e5a5..c53fa17c50 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -33,7 +33,6 @@ #include "sysemu/xen.h" #include "sysemu/xen-mapcache.h" #include "trace.h" -#include "exec/address-spaces.h" #include <xen/hvm/ioreq.h> #include <xen/hvm/e820.h> diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c index 01ae1fb161..72028449ba 100644 --- a/hw/i386/xen/xen_platform.c +++ b/hw/i386/xen/xen_platform.c @@ -27,12 +27,10 @@ #include "qapi/error.h" #include "hw/ide.h" #include "hw/pci/pci.h" -#include "hw/irq.h" #include "hw/xen/xen_common.h" #include "migration/vmstate.h" #include "hw/xen/xen-legacy-backend.h" #include "trace.h" -#include "exec/address-spaces.h" #include "sysemu/xen.h" #include "sysemu/block-backend.h" #include "qemu/error-report.h" diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig index 5d9106b1ac..8e2c893454 100644 --- a/hw/ide/Kconfig +++ b/hw/ide/Kconfig @@ -41,6 +41,7 @@ config IDE_VIA config MICRODRIVE bool select IDE_QDEV + depends on PCMCIA config AHCI bool diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 7f32e87731..109de9e2d1 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -26,7 +26,6 @@ #include "hw/ide/ahci.h" #include "hw/ide/internal.h" -#include "hw/sysbus.h" #include "hw/pci/pci.h" #define AHCI_MEM_BAR_SIZE 0x1000 diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c index 0786e57338..e7faf24058 100644 --- a/hw/input/lasips2.c +++ b/hw/input/lasips2.c @@ -24,12 +24,9 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "hw/qdev-properties.h" -#include "hw/hw.h" #include "hw/input/ps2.h" #include "hw/input/lasips2.h" -#include "hw/sysbus.h" #include "exec/hwaddr.h" -#include "sysemu/sysemu.h" #include "trace.h" #include "exec/address-spaces.h" #include "migration/vmstate.h" diff --git a/hw/intc/apic.c b/hw/intc/apic.c index f4f50f974e..3df11c34d6 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -17,7 +17,6 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/> */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/thread.h" #include "hw/i386/apic_internal.h" #include "hw/i386/apic.h" diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 97dd96dffa..2a20982066 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -22,7 +22,6 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "cpu.h" #include "qapi/visitor.h" #include "hw/i386/apic.h" #include "hw/i386/apic_internal.h" diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9494185cf4..7d2a13273a 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -22,8 +22,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" -#include "hw/sysbus.h" #include "migration/blocker.h" #include "sysemu/kvm.h" #include "kvm_arm.h" diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 66eaa97198..d63f8af604 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -18,7 +18,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "hw/sysbus.h" #include "hw/intc/arm_gicv3.h" #include "gicv3_internal.h" diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 65a4c880a3..5c09f00dec 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -22,7 +22,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/intc/arm_gicv3_common.h" -#include "hw/sysbus.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "sysemu/kvm.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 0d8426dafc..c4287d82d8 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/timer.h" diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 984334fa7b..3bfe2544b7 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "hw/irq.h" #include "hw/sysbus.h" -#include "cpu.h" #include "hw/qdev-properties.h" #include "hw/sparc/grlib.h" diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c index 17007a4078..237d5f97eb 100644 --- a/hw/intc/imx_gpcv2.c +++ b/hw/intc/imx_gpcv2.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "hw/intc/imx_gpcv2.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c index 1731a10683..1f10314807 100644 --- a/hw/intc/ompic.c +++ b/hw/intc/ompic.c @@ -7,7 +7,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" #include "hw/irq.h" diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 65970e1b37..9b4c17854d 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -47,7 +47,6 @@ #include "qapi/error.h" #include "qemu/bitops.h" #include "qapi/qmp/qerror.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/timer.h" #include "qemu/error-report.h" diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c index e1a39e33cb..21da680389 100644 --- a/hw/intc/openpic_kvm.c +++ b/hw/intc/openpic_kvm.c @@ -24,9 +24,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include <sys/ioctl.h> -#include "exec/address-spaces.h" #include "hw/ppc/openpic.h" #include "hw/ppc/openpic_kvm.h" #include "hw/pci/msi.h" diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c index aacdb1bbc2..74e02858d4 100644 --- a/hw/intc/s390_flic.c +++ b/hw/intc/s390_flic.c @@ -20,7 +20,6 @@ #include "hw/qdev-properties.h" #include "hw/s390x/css.h" #include "trace.h" -#include "cpu.h" #include "qapi/error.h" #include "hw/s390x/s390-virtio-ccw.h" diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c index b3fb9f8395..929cfa3a68 100644 --- a/hw/intc/s390_flic_kvm.c +++ b/hw/intc/s390_flic_kvm.c @@ -11,13 +11,11 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "kvm_s390x.h" #include <sys/ioctl.h> #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "hw/sysbus.h" #include "sysemu/kvm.h" #include "hw/s390x/s390_flic.h" #include "hw/s390x/adapter.h" diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 97a1a27a9a..78903beb06 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -25,11 +25,9 @@ #include "qemu/error-report.h" #include "hw/sysbus.h" #include "hw/pci/msi.h" -#include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/intc/sifive_plic.h" #include "target/riscv/cpu.h" -#include "sysemu/sysemu.h" #include "migration/vmstate.h" #define RISCV_DEBUG_PLIC 0 diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 801bc19341..89cfa018f5 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -1798,7 +1798,7 @@ static target_ulong h_int_reset(PowerPCCPU *cpu, return H_PARAMETER; } - device_legacy_reset(DEVICE(xive)); + device_cold_reset(DEVICE(xive)); if (spapr_xive_in_kernel(xive)) { Error *local_err = NULL; diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 68f9d44feb..48a835eab7 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "trace.h" #include "qemu/timer.h" #include "hw/ppc/xics.h" diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index 570d635bcc..f5bfc501bc 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -28,7 +28,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" #include "trace.h" #include "sysemu/kvm.h" #include "hw/ppc/spapr.h" diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 8ae4f41459..37b2d99977 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "trace.h" #include "qemu/timer.h" #include "hw/ppc/spapr.h" diff --git a/hw/ipmi/isa_ipmi_bt.c b/hw/ipmi/isa_ipmi_bt.c index b7c2ad557b..02625eb94e 100644 --- a/hw/ipmi/isa_ipmi_bt.c +++ b/hw/ipmi/isa_ipmi_bt.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" #include "hw/irq.h" diff --git a/hw/ipmi/isa_ipmi_kcs.c b/hw/ipmi/isa_ipmi_kcs.c index 7dd6bf0040..3b23ad08b3 100644 --- a/hw/ipmi/isa_ipmi_kcs.c +++ b/hw/ipmi/isa_ipmi_kcs.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" #include "hw/irq.h" diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c index 179c185695..c81bfe58ef 100644 --- a/hw/isa/isa-superio.c +++ b/hw/isa/isa-superio.c @@ -14,7 +14,6 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "sysemu/sysemu.h" #include "sysemu/blockdev.h" #include "chardev/char.h" #include "hw/block/fdc.h" diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 3963b73520..5f9de0239c 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -34,7 +34,6 @@ #include "qapi/visitor.h" #include "qemu/range.h" #include "hw/isa/isa.h" -#include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/isa/apm.h" @@ -45,7 +44,6 @@ #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "hw/core/cpu.h" diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index f46ccae25c..dab901c9ad 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -29,7 +29,6 @@ #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/xen.h" -#include "sysemu/sysemu.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index b3b6a4378a..0fe7b69bc4 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -29,7 +29,6 @@ #include "hw/southbridge/piix.h" #include "hw/pci/pci.h" #include "hw/isa/isa.h" -#include "hw/sysbus.h" #include "hw/intc/i8259.h" #include "hw/dma/i8257.h" #include "hw/timer/i8254.h" @@ -268,8 +267,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, - isa_get_irq(NULL, 9), NULL, 0, NULL); - } + qdev_get_gpio_in_named(dev, "isa", 9), + NULL, 0, NULL); + } return dev; } diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 98325bb32b..f57f3e7067 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -8,6 +8,9 @@ * * Contributions after 2012-01-13 are licensed under the terms of the * GNU GPL, version 2 or (at your option) any later version. + * + * VT8231 south bridge support and general clean up to allow it + * Copyright (c) 2018-2020 BALATON Zoltan */ #include "qemu/osdep.h" @@ -30,7 +33,6 @@ #include "qemu/module.h" #include "qemu/range.h" #include "qemu/timer.h" -#include "exec/address-spaces.h" #include "trace.h" #define TYPE_VIA_PM "via-pm" @@ -265,15 +267,80 @@ static const TypeInfo vt8231_pm_info = { }; -typedef struct SuperIOConfig { +#define TYPE_VIA_SUPERIO "via-superio" +OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO) + +struct ViaSuperIOState { + ISASuperIODevice superio; uint8_t regs[0x100]; + const MemoryRegionOps *io_ops; MemoryRegion io; -} SuperIOConfig; +}; + +static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable) +{ + memory_region_set_enabled(&s->io, enable); +} + +static void via_superio_realize(DeviceState *d, Error **errp) +{ + ViaSuperIOState *s = VIA_SUPERIO(d); + ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s); + Error *local_err = NULL; + + assert(s->io_ops); + ic->parent_realize(d, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2); + memory_region_set_enabled(&s->io, false); + /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */ + memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0, + &s->io); +} + +static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size) +{ + ViaSuperIOState *sc = opaque; + uint8_t idx = sc->regs[0]; + uint8_t val = sc->regs[idx]; + + if (addr == 0) { + return idx; + } + if (addr == 1 && idx == 0) { + val = 0; /* reading reg 0 where we store index value */ + } + trace_via_superio_read(idx, val); + return val; +} -static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, - unsigned size) +static void via_superio_class_init(ObjectClass *klass, void *data) { - SuperIOConfig *sc = opaque; + DeviceClass *dc = DEVICE_CLASS(klass); + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); + + sc->parent_realize = dc->realize; + dc->realize = via_superio_realize; +} + +static const TypeInfo via_superio_info = { + .name = TYPE_VIA_SUPERIO, + .parent = TYPE_ISA_SUPERIO, + .instance_size = sizeof(ViaSuperIOState), + .class_size = sizeof(ISASuperIOClass), + .class_init = via_superio_class_init, + .abstract = true, +}; + +#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" + +static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + ViaSuperIOState *sc = opaque; uint8_t idx = sc->regs[0]; if (addr == 0) { /* config index register */ @@ -304,25 +371,105 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, sc->regs[idx] = data; } -static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) +static const MemoryRegionOps vt82c686b_superio_cfg_ops = { + .read = via_superio_cfg_read, + .write = vt82c686b_superio_cfg_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static void vt82c686b_superio_reset(DeviceState *dev) +{ + ViaSuperIOState *s = VIA_SUPERIO(dev); + + memset(s->regs, 0, sizeof(s->regs)); + /* Device ID */ + vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); + vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); + /* Function select - all disabled */ + vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); + vt82c686b_superio_cfg_write(s, 1, 0x03, 1); + /* Floppy ctrl base addr 0x3f0-7 */ + vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); + vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); + /* Parallel port base addr 0x378-f */ + vt82c686b_superio_cfg_write(s, 0, 0xe6, 1); + vt82c686b_superio_cfg_write(s, 1, 0xde, 1); + /* Serial port 1 base addr 0x3f8-f */ + vt82c686b_superio_cfg_write(s, 0, 0xe7, 1); + vt82c686b_superio_cfg_write(s, 1, 0xfe, 1); + /* Serial port 2 base addr 0x2f8-f */ + vt82c686b_superio_cfg_write(s, 0, 0xe8, 1); + vt82c686b_superio_cfg_write(s, 1, 0xbe, 1); + + vt82c686b_superio_cfg_write(s, 0, 0, 1); +} + +static void vt82c686b_superio_init(Object *obj) +{ + VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops; +} + +static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) { - SuperIOConfig *sc = opaque; + DeviceClass *dc = DEVICE_CLASS(klass); + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); + + dc->reset = vt82c686b_superio_reset; + sc->serial.count = 2; + sc->parallel.count = 1; + sc->ide.count = 0; /* emulated by via-ide */ + sc->floppy.count = 1; +} + +static const TypeInfo vt82c686b_superio_info = { + .name = TYPE_VT82C686B_SUPERIO, + .parent = TYPE_VIA_SUPERIO, + .instance_size = sizeof(ViaSuperIOState), + .instance_init = vt82c686b_superio_init, + .class_size = sizeof(ISASuperIOClass), + .class_init = vt82c686b_superio_class_init, +}; + + +#define TYPE_VT8231_SUPERIO "vt8231-superio" + +static void vt8231_superio_cfg_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + ViaSuperIOState *sc = opaque; uint8_t idx = sc->regs[0]; - uint8_t val = sc->regs[idx]; - if (addr == 0) { - return idx; + if (addr == 0) { /* config index register */ + sc->regs[0] = data; + return; } - if (addr == 1 && idx == 0) { - val = 0; /* reading reg 0 where we store index value */ + + /* config data register */ + trace_via_superio_write(idx, data); + switch (idx) { + case 0x00 ... 0xdf: + case 0xe7 ... 0xef: + case 0xf0 ... 0xf1: + case 0xf5: + case 0xf8: + case 0xfd: + /* ignore write to read only registers */ + return; + default: + qemu_log_mask(LOG_UNIMP, + "via_superio_cfg: unimplemented register 0x%x\n", idx); + break; } - trace_via_superio_read(idx, val); - return val; + sc->regs[idx] = data; } -static const MemoryRegionOps superio_cfg_ops = { - .read = superio_cfg_read, - .write = superio_cfg_write, +static const MemoryRegionOps vt8231_superio_cfg_ops = { + .read = via_superio_cfg_read, + .write = vt8231_superio_cfg_write, .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 1, @@ -330,47 +477,119 @@ static const MemoryRegionOps superio_cfg_ops = { }, }; +static void vt8231_superio_reset(DeviceState *dev) +{ + ViaSuperIOState *s = VIA_SUPERIO(dev); + + memset(s->regs, 0, sizeof(s->regs)); + /* Device ID */ + s->regs[0xf0] = 0x3c; + /* Device revision */ + s->regs[0xf1] = 0x01; + /* Function select - all disabled */ + vt8231_superio_cfg_write(s, 0, 0xf2, 1); + vt8231_superio_cfg_write(s, 1, 0x03, 1); + /* Serial port base addr */ + vt8231_superio_cfg_write(s, 0, 0xf4, 1); + vt8231_superio_cfg_write(s, 1, 0xfe, 1); + /* Parallel port base addr */ + vt8231_superio_cfg_write(s, 0, 0xf6, 1); + vt8231_superio_cfg_write(s, 1, 0xde, 1); + /* Floppy ctrl base addr */ + vt8231_superio_cfg_write(s, 0, 0xf7, 1); + vt8231_superio_cfg_write(s, 1, 0xfc, 1); + + vt8231_superio_cfg_write(s, 0, 0, 1); +} + +static void vt8231_superio_init(Object *obj) +{ + VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops; +} -OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) +static uint16_t vt8231_superio_serial_iobase(ISASuperIODevice *sio, + uint8_t index) +{ + return 0x2f8; /* FIXME: This should be settable via registers f2-f4 */ +} -struct VT82C686BISAState { +static void vt8231_superio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); + + dc->reset = vt8231_superio_reset; + sc->serial.count = 1; + sc->serial.get_iobase = vt8231_superio_serial_iobase; + sc->parallel.count = 1; + sc->ide.count = 0; /* emulated by via-ide */ + sc->floppy.count = 1; +} + +static const TypeInfo vt8231_superio_info = { + .name = TYPE_VT8231_SUPERIO, + .parent = TYPE_VIA_SUPERIO, + .instance_size = sizeof(ViaSuperIOState), + .instance_init = vt8231_superio_init, + .class_size = sizeof(ISASuperIOClass), + .class_init = vt8231_superio_class_init, +}; + + +#define TYPE_VIA_ISA "via-isa" +OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA) + +struct ViaISAState { PCIDevice dev; qemu_irq cpu_intr; - SuperIOConfig superio_cfg; + ViaSuperIOState *via_sio; +}; + +static const VMStateDescription vmstate_via = { + .name = "via-isa", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, ViaISAState), + VMSTATE_END_OF_LIST() + } +}; + +static const TypeInfo via_isa_info = { + .name = TYPE_VIA_ISA, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(ViaISAState), + .abstract = true, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, }; static void via_isa_request_i8259_irq(void *opaque, int irq, int level) { - VT82C686BISAState *s = opaque; + ViaISAState *s = opaque; qemu_set_irq(s->cpu_intr, level); } +/* TYPE_VT82C686B_ISA */ + static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) { - VT82C686BISAState *s = VT82C686B_ISA(d); + ViaISAState *s = VIA_ISA(d); trace_via_isa_write(addr, val, len); pci_default_write_config(d, addr, val, len); if (addr == 0x85) { /* BIT(1): enable or disable superio config io ports */ - memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); + via_superio_io_enable(s->via_sio, val & BIT(1)); } } -static const VMStateDescription vmstate_via = { - .name = "vt82c686b", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), - VMSTATE_END_OF_LIST() - } -}; - static void vt82c686b_isa_reset(DeviceState *dev) { - VT82C686BISAState *s = VT82C686B_ISA(dev); + ViaISAState *s = VIA_ISA(dev); uint8_t *pci_conf = s->dev.config; pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); @@ -386,18 +605,11 @@ static void vt82c686b_isa_reset(DeviceState *dev) pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ pci_conf[0x5f] = 0x04; pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ - - s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */ - s->superio_cfg.regs[0xe2] = 0x03; /* Function select */ - s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */ - s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */ - s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */ - s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */ } static void vt82c686b_realize(PCIDevice *d, Error **errp) { - VT82C686BISAState *s = VT82C686B_ISA(d); + ViaISAState *s = VIA_ISA(d); DeviceState *dev = DEVICE(d); ISABus *isa_bus; qemu_irq *isa_irq; @@ -410,7 +622,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); + s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus, + TYPE_VT82C686B_SUPERIO)); mc146818_rtc_init(isa_bus, 2000, NULL); for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { @@ -418,19 +631,9 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp) d->wmask[i] = 0; } } - - memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, - &s->superio_cfg, "superio_cfg", 2); - memory_region_set_enabled(&s->superio_cfg.io, false); - /* - * The floppy also uses 0x3f0 and 0x3f1. - * But we do not emulate a floppy, so just set it here. - */ - memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, - &s->superio_cfg.io); } -static void via_class_init(ObjectClass *klass, void *data) +static void vt82c686b_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); @@ -438,47 +641,101 @@ static void via_class_init(ObjectClass *klass, void *data) k->realize = vt82c686b_realize; k->config_write = vt82c686b_write_config; k->vendor_id = PCI_VENDOR_ID_VIA; - k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; + k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA; k->class_id = PCI_CLASS_BRIDGE_ISA; k->revision = 0x40; dc->reset = vt82c686b_isa_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_via; - /* - * Reason: part of VIA VT82C686 southbridge, needs to be wired up, - * e.g. by mips_fuloong2e_init() - */ + /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */ dc->user_creatable = false; } -static const TypeInfo via_info = { +static const TypeInfo vt82c686b_isa_info = { .name = TYPE_VT82C686B_ISA, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(VT82C686BISAState), - .class_init = via_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, + .parent = TYPE_VIA_ISA, + .instance_size = sizeof(ViaISAState), + .class_init = vt82c686b_class_init, }; +/* TYPE_VT8231_ISA */ -static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) +static void vt8231_write_config(PCIDevice *d, uint32_t addr, + uint32_t val, int len) { - ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); + ViaISAState *s = VIA_ISA(d); - sc->serial.count = 2; - sc->parallel.count = 1; - sc->ide.count = 0; - sc->floppy.count = 1; + trace_via_isa_write(addr, val, len); + pci_default_write_config(d, addr, val, len); + if (addr == 0x50) { + /* BIT(2): enable or disable superio config io ports */ + via_superio_io_enable(s->via_sio, val & BIT(2)); + } } -static const TypeInfo via_superio_info = { - .name = TYPE_VT82C686B_SUPERIO, - .parent = TYPE_ISA_SUPERIO, - .instance_size = sizeof(ISASuperIODevice), - .class_size = sizeof(ISASuperIOClass), - .class_init = vt82c686b_superio_class_init, +static void vt8231_isa_reset(DeviceState *dev) +{ + ViaISAState *s = VIA_ISA(dev); + uint8_t *pci_conf = s->dev.config; + + pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); + pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); + + pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */ + pci_conf[0x67] = 0x08; /* Fast IR Config */ + pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */ +} + +static void vt8231_realize(PCIDevice *d, Error **errp) +{ + ViaISAState *s = VIA_ISA(d); + DeviceState *dev = DEVICE(d); + ISABus *isa_bus; + qemu_irq *isa_irq; + int i; + + qdev_init_gpio_out(dev, &s->cpu_intr, 1); + isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); + isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), + &error_fatal); + isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); + i8254_pit_init(isa_bus, 0x40, 0, NULL); + i8257_dma_init(isa_bus, 0); + s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus, TYPE_VT8231_SUPERIO)); + mc146818_rtc_init(isa_bus, 2000, NULL); + + for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { + if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { + d->wmask[i] = 0; + } + } +} + +static void vt8231_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = vt8231_realize; + k->config_write = vt8231_write_config; + k->vendor_id = PCI_VENDOR_ID_VIA; + k->device_id = PCI_DEVICE_ID_VIA_8231_ISA; + k->class_id = PCI_CLASS_BRIDGE_ISA; + k->revision = 0x10; + dc->reset = vt8231_isa_reset; + dc->desc = "ISA bridge"; + dc->vmsd = &vmstate_via; + /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ + dc->user_creatable = false; +} + +static const TypeInfo vt8231_isa_info = { + .name = TYPE_VT8231_ISA, + .parent = TYPE_VIA_ISA, + .instance_size = sizeof(ViaISAState), + .class_init = vt8231_class_init, }; @@ -487,8 +744,12 @@ static void vt82c686b_register_types(void) type_register_static(&via_pm_info); type_register_static(&vt82c686b_pm_info); type_register_static(&vt8231_pm_info); - type_register_static(&via_info); type_register_static(&via_superio_info); + type_register_static(&vt82c686b_superio_info); + type_register_static(&vt8231_superio_info); + type_register_static(&via_isa_info); + type_register_static(&vt82c686b_isa_info); + type_register_static(&vt8231_isa_info); } type_init(vt82c686b_register_types) diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c index b5d97dd53e..2961e4c2b4 100644 --- a/hw/lm32/lm32_boards.c +++ b/hw/lm32/lm32_boards.c @@ -30,7 +30,6 @@ #include "elf.h" #include "lm32_hwsetup.h" #include "lm32.h" -#include "exec/address-spaces.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c index 72d1326531..bef7855328 100644 --- a/hw/lm32/milkymist.c +++ b/hw/lm32/milkymist.c @@ -37,7 +37,6 @@ #include "hw/display/milkymist_tmu2.h" #include "hw/sd/sd.h" #include "lm32.h" -#include "exec/address-spaces.h" #include "qemu/cutils.h" #define BIOS_FILENAME "mmone-bios.bin" diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c index 673898b0ea..11ae4c9795 100644 --- a/hw/m68k/an5206.c +++ b/hw/m68k/an5206.c @@ -13,7 +13,6 @@ #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 7a03c71059..93812ee206 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -26,7 +26,6 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "elf.h" -#include "exec/address-spaces.h" #define SYS_FREQ 166666666 diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c index cf02f57a71..4cd30188c0 100644 --- a/hw/m68k/mcf_intc.c +++ b/hw/m68k/mcf_intc.c @@ -11,7 +11,6 @@ #include "qemu/module.h" #include "qemu/log.h" #include "cpu.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/sysbus.h" #include "hw/m68k/mcf.h" diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 92b45d760f..de951ffe5d 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -10,9 +10,7 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "exec/hwaddr.h" -#include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "hw/irq.h" diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c index c11b5281f1..0544160e91 100644 --- a/hw/m68k/next-kbd.c +++ b/hw/m68k/next-kbd.c @@ -29,12 +29,9 @@ #include "qemu/osdep.h" #include "qemu/log.h" -#include "exec/address-spaces.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/m68k/next-cube.h" #include "ui/console.h" -#include "sysemu/sysemu.h" #include "migration/vmstate.h" #include "qom/object.h" diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 4d2e866eec..11376daa85 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -26,14 +26,11 @@ #include "qemu/datadir.h" #include "sysemu/sysemu.h" #include "cpu.h" -#include "hw/hw.h" #include "hw/boards.h" -#include "hw/irq.h" #include "hw/or-irq.h" #include "elf.h" #include "hw/loader.h" #include "ui/console.h" -#include "exec/address-spaces.h" #include "hw/char/escc.h" #include "hw/sysbus.h" #include "hw/scsi/esp.h" diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c index e9a5d4c69b..4e8bce5aa6 100644 --- a/hw/m68k/virt.c +++ b/hw/m68k/virt.c @@ -12,14 +12,11 @@ #include "qemu-common.h" #include "sysemu/sysemu.h" #include "cpu.h" -#include "hw/hw.h" #include "hw/boards.h" -#include "hw/irq.h" #include "hw/qdev-properties.h" #include "elf.h" #include "hw/loader.h" #include "ui/console.h" -#include "exec/address-spaces.h" #include "hw/sysbus.h" #include "standard-headers/asm-m68k/bootinfo.h" #include "standard-headers/asm-m68k/bootinfo-virt.h" diff --git a/hw/mem/sparse-mem.c b/hw/mem/sparse-mem.c index a13ac74dd9..e6640eb8e7 100644 --- a/hw/mem/sparse-mem.c +++ b/hw/mem/sparse-mem.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qapi/error.h" diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index caaba1aa4c..8821d009f1 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -33,7 +33,6 @@ #include "qemu/error-report.h" #include "sysemu/device_tree.h" #include "sysemu/reset.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" diff --git a/hw/mips/boston.c b/hw/mips/boston.c index ac2e93a05a..20b06865b2 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/char/serial.h" #include "hw/ide/pci.h" diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 4f61f2c873..c1b8066a13 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -33,13 +33,11 @@ #include "hw/mips/bootloader.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" -#include "qemu/log.h" #include "hw/loader.h" #include "hw/ide/pci.h" #include "hw/qdev-properties.h" #include "elf.h" #include "hw/isa/vt82c686.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 43349d6837..c7480bd019 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -33,7 +33,6 @@ #include "migration/vmstate.h" #include "hw/intc/i8259.h" #include "hw/irq.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 1a0888a0fd..dba2088ed1 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -47,7 +47,6 @@ #include "hw/audio/pcspk.h" #include "hw/input/i8042.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "qapi/error.h" diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index b15071defc..ae192db0c8 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -29,10 +29,8 @@ #include "qemu/cutils.h" #include "qemu/datadir.h" #include "qapi/error.h" -#include "cpu.h" #include "elf.h" #include "kvm_mips.h" -#include "hw/boards.h" #include "hw/char/serial.h" #include "hw/intc/loongson_liointc.h" #include "hw/mips/mips.h" @@ -49,12 +47,10 @@ #include "hw/pci-host/gpex.h" #include "hw/usb.h" #include "net/net.h" -#include "exec/address-spaces.h" #include "sysemu/kvm.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "qemu/log.h" #include "qemu/error-report.h" #define PM_CNTL_MODE 0x10 diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 26e7b1bd9f..7dcf175d72 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -27,7 +27,6 @@ #include "qemu/bitops.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/clock.h" #include "hw/southbridge/piix.h" #include "hw/isa/superio.h" @@ -39,7 +38,6 @@ #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" -#include "sysemu/sysemu.h" #include "sysemu/arch_init.h" #include "qemu/log.h" #include "hw/mips/bios.h" @@ -47,7 +45,6 @@ #include "hw/irq.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "qom/object.h" #include "hw/sysbus.h" /* SysBusDevice */ #include "qemu/host-utils.h" diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 1195716dc7..dd0101ad4d 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,12 +1,15 @@ mips_ss = ss.source_set() mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) -mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) -mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) +mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) + +if 'CONFIG_TCG' in config_all +mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) +mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) -mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) +endif hw_arch += {'mips': mips_ss} diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 0f9c6f07c1..2db5e10fe0 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -24,7 +24,6 @@ #include "qemu/main-loop.h" #include "hw/irq.h" #include "hw/mips/cpudevs.h" -#include "cpu.h" #include "sysemu/kvm.h" #include "kvm_mips.h" diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index f5d0da05aa..2325e7e05a 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -29,7 +29,6 @@ #include "qapi/error.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/clock.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" @@ -43,7 +42,6 @@ #include "elf.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c new file mode 100644 index 0000000000..10f00e65f4 --- /dev/null +++ b/hw/misc/aspeed_hace.c @@ -0,0 +1,389 @@ +/* + * ASPEED Hash and Crypto Engine + * + * Copyright (C) 2021 IBM Corp. + * + * Joel Stanley <joel@jms.id.au> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/misc/aspeed_hace.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "crypto/hash.h" +#include "hw/qdev-properties.h" +#include "hw/irq.h" + +#define R_CRYPT_CMD (0x10 / 4) + +#define R_STATUS (0x1c / 4) +#define HASH_IRQ BIT(9) +#define CRYPT_IRQ BIT(12) +#define TAG_IRQ BIT(15) + +#define R_HASH_SRC (0x20 / 4) +#define R_HASH_DEST (0x24 / 4) +#define R_HASH_SRC_LEN (0x2c / 4) + +#define R_HASH_CMD (0x30 / 4) +/* Hash algorithm selection */ +#define HASH_ALGO_MASK (BIT(4) | BIT(5) | BIT(6)) +#define HASH_ALGO_MD5 0 +#define HASH_ALGO_SHA1 BIT(5) +#define HASH_ALGO_SHA224 BIT(6) +#define HASH_ALGO_SHA256 (BIT(4) | BIT(6)) +#define HASH_ALGO_SHA512_SERIES (BIT(5) | BIT(6)) +/* SHA512 algorithm selection */ +#define SHA512_HASH_ALGO_MASK (BIT(10) | BIT(11) | BIT(12)) +#define HASH_ALGO_SHA512_SHA512 0 +#define HASH_ALGO_SHA512_SHA384 BIT(10) +#define HASH_ALGO_SHA512_SHA256 BIT(11) +#define HASH_ALGO_SHA512_SHA224 (BIT(10) | BIT(11)) +/* HMAC modes */ +#define HASH_HMAC_MASK (BIT(7) | BIT(8)) +#define HASH_DIGEST 0 +#define HASH_DIGEST_HMAC BIT(7) +#define HASH_DIGEST_ACCUM BIT(8) +#define HASH_HMAC_KEY (BIT(7) | BIT(8)) +/* Cascaded operation modes */ +#define HASH_ONLY 0 +#define HASH_ONLY2 BIT(0) +#define HASH_CRYPT_THEN_HASH BIT(1) +#define HASH_HASH_THEN_CRYPT (BIT(0) | BIT(1)) +/* Other cmd bits */ +#define HASH_IRQ_EN BIT(9) +#define HASH_SG_EN BIT(18) +/* Scatter-gather data list */ +#define SG_LIST_LEN_SIZE 4 +#define SG_LIST_LEN_MASK 0x0FFFFFFF +#define SG_LIST_LEN_LAST BIT(31) +#define SG_LIST_ADDR_SIZE 4 +#define SG_LIST_ADDR_MASK 0x7FFFFFFF +#define SG_LIST_ENTRY_SIZE (SG_LIST_LEN_SIZE + SG_LIST_ADDR_SIZE) +#define ASPEED_HACE_MAX_SG 256 /* max number of entries */ + +static const struct { + uint32_t mask; + QCryptoHashAlgorithm algo; +} hash_algo_map[] = { + { HASH_ALGO_MD5, QCRYPTO_HASH_ALG_MD5 }, + { HASH_ALGO_SHA1, QCRYPTO_HASH_ALG_SHA1 }, + { HASH_ALGO_SHA224, QCRYPTO_HASH_ALG_SHA224 }, + { HASH_ALGO_SHA256, QCRYPTO_HASH_ALG_SHA256 }, + { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512, QCRYPTO_HASH_ALG_SHA512 }, + { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384, QCRYPTO_HASH_ALG_SHA384 }, + { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256, QCRYPTO_HASH_ALG_SHA256 }, +}; + +static int hash_algo_lookup(uint32_t reg) +{ + int i; + + reg &= HASH_ALGO_MASK | SHA512_HASH_ALGO_MASK; + + for (i = 0; i < ARRAY_SIZE(hash_algo_map); i++) { + if (reg == hash_algo_map[i].mask) { + return hash_algo_map[i].algo; + } + } + + return -1; +} + +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) +{ + struct iovec iov[ASPEED_HACE_MAX_SG]; + g_autofree uint8_t *digest_buf; + size_t digest_len = 0; + int i; + + if (sg_mode) { + uint32_t len = 0; + + for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { + uint32_t addr, src; + hwaddr plen; + + if (i == ASPEED_HACE_MAX_SG) { + qemu_log_mask(LOG_GUEST_ERROR, + "aspeed_hace: guest failed to set end of sg list marker\n"); + break; + } + + src = s->regs[R_HASH_SRC] + (i * SG_LIST_ENTRY_SIZE); + + len = address_space_ldl_le(&s->dram_as, src, + MEMTXATTRS_UNSPECIFIED, NULL); + + addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE, + MEMTXATTRS_UNSPECIFIED, NULL); + addr &= SG_LIST_ADDR_MASK; + + iov[i].iov_len = len & SG_LIST_LEN_MASK; + plen = iov[i].iov_len; + iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, + MEMTXATTRS_UNSPECIFIED); + } + } else { + hwaddr len = s->regs[R_HASH_SRC_LEN]; + + iov[0].iov_len = len; + iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], + &len, false, + MEMTXATTRS_UNSPECIFIED); + i = 1; + } + + if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, &digest_len, NULL) < 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + + if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST], + MEMTXATTRS_UNSPECIFIED, + digest_buf, digest_len)) { + qemu_log_mask(LOG_GUEST_ERROR, + "aspeed_hace: address space write failed\n"); + } + + for (; i > 0; i--) { + address_space_unmap(&s->dram_as, iov[i - 1].iov_base, + iov[i - 1].iov_len, false, + iov[i - 1].iov_len); + } + + /* + * Set status bits to indicate completion. Testing shows hardware sets + * these irrespective of HASH_IRQ_EN. + */ + s->regs[R_STATUS] |= HASH_IRQ; +} + +static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int size) +{ + AspeedHACEState *s = ASPEED_HACE(opaque); + + addr >>= 2; + + if (addr >= ASPEED_HACE_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", + __func__, addr << 2); + return 0; + } + + return s->regs[addr]; +} + +static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + AspeedHACEState *s = ASPEED_HACE(opaque); + AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s); + + addr >>= 2; + + if (addr >= ASPEED_HACE_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", + __func__, addr << 2); + return; + } + + switch (addr) { + case R_STATUS: + if (data & HASH_IRQ) { + data &= ~HASH_IRQ; + + if (s->regs[addr] & HASH_IRQ) { + qemu_irq_lower(s->irq); + } + } + break; + case R_HASH_SRC: + data &= ahc->src_mask; + break; + case R_HASH_DEST: + data &= ahc->dest_mask; + break; + case R_HASH_SRC_LEN: + data &= 0x0FFFFFFF; + break; + case R_HASH_CMD: { + int algo; + data &= ahc->hash_mask; + + if ((data & HASH_HMAC_MASK)) { + qemu_log_mask(LOG_UNIMP, + "%s: HMAC engine command mode %"PRIx64" not implemented", + __func__, (data & HASH_HMAC_MASK) >> 8); + } + if (data & BIT(1)) { + qemu_log_mask(LOG_UNIMP, + "%s: Cascaded mode not implemented", + __func__); + } + algo = hash_algo_lookup(data); + if (algo < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", + __func__, data & ahc->hash_mask); + break; + } + do_hash_operation(s, algo, data & HASH_SG_EN); + + if (data & HASH_IRQ_EN) { + qemu_irq_raise(s->irq); + } + break; + } + case R_CRYPT_CMD: + qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n", + __func__); + break; + default: + break; + } + + s->regs[addr] = data; +} + +static const MemoryRegionOps aspeed_hace_ops = { + .read = aspeed_hace_read, + .write = aspeed_hace_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static void aspeed_hace_reset(DeviceState *dev) +{ + struct AspeedHACEState *s = ASPEED_HACE(dev); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static void aspeed_hace_realize(DeviceState *dev, Error **errp) +{ + AspeedHACEState *s = ASPEED_HACE(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_hace_ops, s, + TYPE_ASPEED_HACE, 0x1000); + + if (!s->dram_mr) { + error_setg(errp, TYPE_ASPEED_HACE ": 'dram' link not set"); + return; + } + + address_space_init(&s->dram_as, s->dram_mr, "dram"); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static Property aspeed_hace_properties[] = { + DEFINE_PROP_LINK("dram", AspeedHACEState, dram_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + + +static const VMStateDescription vmstate_aspeed_hace = { + .name = TYPE_ASPEED_HACE, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = aspeed_hace_realize; + dc->reset = aspeed_hace_reset; + device_class_set_props(dc, aspeed_hace_properties); + dc->vmsd = &vmstate_aspeed_hace; +} + +static const TypeInfo aspeed_hace_info = { + .name = TYPE_ASPEED_HACE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedHACEState), + .class_init = aspeed_hace_class_init, + .class_size = sizeof(AspeedHACEClass) +}; + +static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass); + + dc->desc = "AST2400 Hash and Crypto Engine"; + + ahc->src_mask = 0x0FFFFFFF; + ahc->dest_mask = 0x0FFFFFF8; + ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ +} + +static const TypeInfo aspeed_ast2400_hace_info = { + .name = TYPE_ASPEED_AST2400_HACE, + .parent = TYPE_ASPEED_HACE, + .class_init = aspeed_ast2400_hace_class_init, +}; + +static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass); + + dc->desc = "AST2500 Hash and Crypto Engine"; + + ahc->src_mask = 0x3fffffff; + ahc->dest_mask = 0x3ffffff8; + ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ +} + +static const TypeInfo aspeed_ast2500_hace_info = { + .name = TYPE_ASPEED_AST2500_HACE, + .parent = TYPE_ASPEED_HACE, + .class_init = aspeed_ast2500_hace_class_init, +}; + +static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass); + + dc->desc = "AST2600 Hash and Crypto Engine"; + + ahc->src_mask = 0x7FFFFFFF; + ahc->dest_mask = 0x7FFFFFF8; + ahc->hash_mask = 0x00147FFF; +} + +static const TypeInfo aspeed_ast2600_hace_info = { + .name = TYPE_ASPEED_AST2600_HACE, + .parent = TYPE_ASPEED_HACE, + .class_init = aspeed_ast2600_hace_class_init, +}; + +static void aspeed_hace_register_types(void) +{ + type_register_static(&aspeed_ast2400_hace_info); + type_register_static(&aspeed_ast2500_hace_info); + type_register_static(&aspeed_ast2600_hace_info); + type_register_static(&aspeed_hace_info); +} + +type_init(aspeed_hace_register_types); diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c index 533d237e3c..1c21577c98 100644 --- a/hw/misc/aspeed_xdma.c +++ b/hw/misc/aspeed_xdma.c @@ -30,6 +30,19 @@ #define XDMA_IRQ_ENG_STAT_US_COMP BIT(4) #define XDMA_IRQ_ENG_STAT_DS_COMP BIT(5) #define XDMA_IRQ_ENG_STAT_RESET 0xF8000000 + +#define XDMA_AST2600_BMC_CMDQ_ADDR 0x14 +#define XDMA_AST2600_BMC_CMDQ_ENDP 0x18 +#define XDMA_AST2600_BMC_CMDQ_WRP 0x1c +#define XDMA_AST2600_BMC_CMDQ_RDP 0x20 +#define XDMA_AST2600_IRQ_CTRL 0x38 +#define XDMA_AST2600_IRQ_CTRL_US_COMP BIT(16) +#define XDMA_AST2600_IRQ_CTRL_DS_COMP BIT(17) +#define XDMA_AST2600_IRQ_CTRL_W_MASK 0x017003FF +#define XDMA_AST2600_IRQ_STATUS 0x3c +#define XDMA_AST2600_IRQ_STATUS_US_COMP BIT(16) +#define XDMA_AST2600_IRQ_STATUS_DS_COMP BIT(17) + #define XDMA_MEM_SIZE 0x1000 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) @@ -52,56 +65,48 @@ static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val, unsigned int idx; uint32_t val32 = (uint32_t)val; AspeedXDMAState *xdma = opaque; + AspeedXDMAClass *axc = ASPEED_XDMA_GET_CLASS(xdma); if (addr >= ASPEED_XDMA_REG_SIZE) { return; } - switch (addr) { - case XDMA_BMC_CMDQ_ENDP: + if (addr == axc->cmdq_endp) { xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK; - break; - case XDMA_BMC_CMDQ_WRP: + } else if (addr == axc->cmdq_wrp) { idx = TO_REG(addr); xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK; - xdma->regs[TO_REG(XDMA_BMC_CMDQ_RDP)] = xdma->regs[idx]; + xdma->regs[TO_REG(axc->cmdq_rdp)] = xdma->regs[idx]; trace_aspeed_xdma_write(addr, val); if (xdma->bmc_cmdq_readp_set) { xdma->bmc_cmdq_readp_set = 0; } else { - xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] |= - XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP; + xdma->regs[TO_REG(axc->intr_status)] |= axc->intr_complete; - if (xdma->regs[TO_REG(XDMA_IRQ_ENG_CTRL)] & - (XDMA_IRQ_ENG_CTRL_US_COMP | XDMA_IRQ_ENG_CTRL_DS_COMP)) + if (xdma->regs[TO_REG(axc->intr_ctrl)] & axc->intr_complete) { qemu_irq_raise(xdma->irq); + } } - break; - case XDMA_BMC_CMDQ_RDP: + } else if (addr == axc->cmdq_rdp) { trace_aspeed_xdma_write(addr, val); if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) { xdma->bmc_cmdq_readp_set = 1; } - break; - case XDMA_IRQ_ENG_CTRL: - xdma->regs[TO_REG(addr)] = val32 & XDMA_IRQ_ENG_CTRL_W_MASK; - break; - case XDMA_IRQ_ENG_STAT: + } else if (addr == axc->intr_ctrl) { + xdma->regs[TO_REG(addr)] = val32 & axc->intr_ctrl_mask; + } else if (addr == axc->intr_status) { trace_aspeed_xdma_write(addr, val); idx = TO_REG(addr); - if (val32 & (XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP)) { - xdma->regs[idx] &= - ~(XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP); + if (val32 & axc->intr_complete) { + xdma->regs[idx] &= ~axc->intr_complete; qemu_irq_lower(xdma->irq); } - break; - default: + } else { xdma->regs[TO_REG(addr)] = val32; - break; } } @@ -127,10 +132,11 @@ static void aspeed_xdma_realize(DeviceState *dev, Error **errp) static void aspeed_xdma_reset(DeviceState *dev) { AspeedXDMAState *xdma = ASPEED_XDMA(dev); + AspeedXDMAClass *axc = ASPEED_XDMA_GET_CLASS(xdma); xdma->bmc_cmdq_readp_set = 0; memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE); - xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] = XDMA_IRQ_ENG_STAT_RESET; + xdma->regs[TO_REG(axc->intr_status)] = XDMA_IRQ_ENG_STAT_RESET; qemu_irq_lower(xdma->irq); } @@ -144,6 +150,73 @@ static const VMStateDescription aspeed_xdma_vmstate = { }, }; +static void aspeed_2600_xdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass); + + dc->desc = "ASPEED 2600 XDMA Controller"; + + axc->cmdq_endp = XDMA_AST2600_BMC_CMDQ_ENDP; + axc->cmdq_wrp = XDMA_AST2600_BMC_CMDQ_WRP; + axc->cmdq_rdp = XDMA_AST2600_BMC_CMDQ_RDP; + axc->intr_ctrl = XDMA_AST2600_IRQ_CTRL; + axc->intr_ctrl_mask = XDMA_AST2600_IRQ_CTRL_W_MASK; + axc->intr_status = XDMA_AST2600_IRQ_STATUS; + axc->intr_complete = XDMA_AST2600_IRQ_STATUS_US_COMP | + XDMA_AST2600_IRQ_STATUS_DS_COMP; +} + +static const TypeInfo aspeed_2600_xdma_info = { + .name = TYPE_ASPEED_2600_XDMA, + .parent = TYPE_ASPEED_XDMA, + .class_init = aspeed_2600_xdma_class_init, +}; + +static void aspeed_2500_xdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass); + + dc->desc = "ASPEED 2500 XDMA Controller"; + + axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP; + axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP; + axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP; + axc->intr_ctrl = XDMA_IRQ_ENG_CTRL; + axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK; + axc->intr_status = XDMA_IRQ_ENG_STAT; + axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP; +}; + +static const TypeInfo aspeed_2500_xdma_info = { + .name = TYPE_ASPEED_2500_XDMA, + .parent = TYPE_ASPEED_XDMA, + .class_init = aspeed_2500_xdma_class_init, +}; + +static void aspeed_2400_xdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass); + + dc->desc = "ASPEED 2400 XDMA Controller"; + + axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP; + axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP; + axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP; + axc->intr_ctrl = XDMA_IRQ_ENG_CTRL; + axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK; + axc->intr_status = XDMA_IRQ_ENG_STAT; + axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP; +}; + +static const TypeInfo aspeed_2400_xdma_info = { + .name = TYPE_ASPEED_2400_XDMA, + .parent = TYPE_ASPEED_XDMA, + .class_init = aspeed_2400_xdma_class_init, +}; + static void aspeed_xdma_class_init(ObjectClass *classp, void *data) { DeviceClass *dc = DEVICE_CLASS(classp); @@ -158,10 +231,15 @@ static const TypeInfo aspeed_xdma_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(AspeedXDMAState), .class_init = aspeed_xdma_class_init, + .class_size = sizeof(AspeedXDMAClass), + .abstract = true, }; static void aspeed_xdma_register_type(void) { type_register_static(&aspeed_xdma_info); + type_register_static(&aspeed_2400_xdma_info); + type_register_static(&aspeed_2500_xdma_info); + type_register_static(&aspeed_2600_xdma_info); } type_init(aspeed_xdma_register_type); diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index 45972a5920..ee7698bd9c 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "hw/misc/imx7_snvs.h" -#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c index 08a50ee4c8..9403c5daa3 100644 --- a/hw/misc/imx_ccm.c +++ b/hw/misc/imx_ccm.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "hw/misc/imx_ccm.h" -#include "qemu/log.h" #include "qemu/module.h" #ifndef DEBUG_IMX_CCM diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c index 4c270df2db..632c03779c 100644 --- a/hw/misc/imx_rngc.c +++ b/hw/misc/imx_rngc.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "qemu/module.h" -#include "qemu/log.h" #include "qemu/guest-random.h" #include "hw/irq.h" #include "hw/misc/imx_rngc.h" diff --git a/hw/misc/led.c b/hw/misc/led.c index f552b8b648..f6d6d68bce 100644 --- a/hw/misc/led.c +++ b/hw/misc/led.c @@ -10,7 +10,6 @@ #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "hw/misc/led.h" -#include "hw/irq.h" #include "trace.h" #define LED_INTENSITY_PERCENT_MAX 100 diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index e6eeb575d5..4515296e66 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -35,7 +35,6 @@ #include "hw/char/escc.h" #include "hw/misc/macio/macio.h" #include "hw/intc/heathrow_pic.h" -#include "sysemu/sysemu.h" #include "trace.h" /* Note: this code is strongly inspirated from the corresponding code diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c index 15cf3d7725..43d8e970ab 100644 --- a/hw/misc/mchp_pfsoc_dmc.c +++ b/hw/misc/mchp_pfsoc_dmc.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_dmc.h" diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c index 8b0d1cacd7..f4fd55a0e5 100644 --- a/hw/misc/mchp_pfsoc_ioscb.c +++ b/hw/misc/mchp_pfsoc_ioscb.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_ioscb.h" diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 248a313345..89571eded5 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_sysreg.h" diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 21034dc60a..1e7b8b064b 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -109,6 +109,7 @@ softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c')) softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c')) softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( + 'aspeed_hace.c', 'aspeed_lpc.c', 'aspeed_scu.c', 'aspeed_sdmc.c', diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 133399598f..80683fed31 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -22,7 +22,6 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" -#include "cpu.h" #include "exec/exec-all.h" #include "hw/misc/mips_itu.h" #include "hw/qdev-properties.h" diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index c56aca86ad..b3b42a792c 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -23,6 +23,7 @@ #include "qemu/bitops.h" #include "trace.h" #include "hw/sysbus.h" +#include "hw/irq.h" #include "migration/vmstate.h" #include "hw/registerfields.h" #include "hw/misc/mps2-scc.h" @@ -186,10 +187,13 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case A_CFG0: /* - * TODO on some boards bit 0 controls RAM remapping; - * on others bit 1 is CPU_WAIT. + * On some boards bit 0 controls board-specific remapping; + * we always reflect bit 0 in the 'remap' GPIO output line, + * and let the board wire it up or not as it chooses. + * TODO on some boards bit 1 is CPU_WAIT. */ s->cfg0 = value; + qemu_set_irq(s->remap, s->cfg0 & 1); break; case A_CFG1: s->cfg1 = value; @@ -283,7 +287,7 @@ static void mps2_scc_reset(DeviceState *dev) int i; trace_mps2_scc_reset(); - s->cfg0 = 0; + s->cfg0 = s->cfg0_reset; s->cfg1 = 0; s->cfg2 = 0; s->cfg5 = 0; @@ -308,6 +312,7 @@ static void mps2_scc_init(Object *obj) memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); sysbus_init_mmio(sbd, &s->iomem); + qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1); } static void mps2_scc_realize(DeviceState *dev, Error **errp) @@ -353,6 +358,8 @@ static Property mps2_scc_properties[] = { DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), + /* Reset value for CFG0 register */ + DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0), /* * These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c index edfc35d5f0..2aaadfa966 100644 --- a/hw/misc/mst_fpga.c +++ b/hw/misc/mst_fpga.c @@ -222,7 +222,7 @@ static void mst_fpga_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } -static VMStateDescription vmstate_mst_fpga_regs = { +static const VMStateDescription vmstate_mst_fpga_regs = { .name = "mainstone_fpga", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c index 27113abd6c..7b66d58acc 100644 --- a/hw/misc/pvpanic-isa.c +++ b/hw/misc/pvpanic-isa.c @@ -13,7 +13,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c index d629639d8f..af8cbe2830 100644 --- a/hw/misc/pvpanic-pci.c +++ b/hw/misc/pvpanic-pci.c @@ -12,7 +12,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" diff --git a/hw/misc/sifive_e_prci.c b/hw/misc/sifive_e_prci.c index 8ec4ee4b41..a8702c6a5d 100644 --- a/hw/misc/sifive_e_prci.c +++ b/hw/misc/sifive_e_prci.c @@ -23,7 +23,6 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" -#include "hw/hw.h" #include "hw/misc/sifive_e_prci.h" static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size) diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c index 2deb2072cc..56df45bfe5 100644 --- a/hw/misc/sifive_test.c +++ b/hw/misc/sifive_test.c @@ -24,7 +24,6 @@ #include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" -#include "hw/hw.h" #include "hw/misc/sifive_test.h" static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) diff --git a/hw/misc/virt_ctrl.c b/hw/misc/virt_ctrl.c index 2ea01bd7a1..3552d7a09a 100644 --- a/hw/misc/virt_ctrl.c +++ b/hw/misc/virt_ctrl.c @@ -5,7 +5,6 @@ */ #include "qemu/osdep.h" -#include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "migration/vmstate.h" diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index f7b57fcae1..3d255d4879 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -29,14 +29,12 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "cpu.h" -#include "hw/sysbus.h" #include "net/net.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/char/serial.h" -#include "exec/address-spaces.h" #include "elf.h" #define PHYS_MEM_BASE 0x80000000 diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index affa21a5ed..22bb8910fa 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -37,7 +37,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qemu/cutils.h" -#include "sysemu/sysemu.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "net/can_emu.h" diff --git a/hw/net/i82596.c b/hw/net/i82596.c index 055c3a1470..ec21e2699a 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -12,7 +12,6 @@ #include "qemu/timer.h" #include "net/net.h" #include "net/eth.h" -#include "sysemu/sysemu.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" diff --git a/hw/net/lasi_i82596.c b/hw/net/lasi_i82596.c index 820b63f350..e37f7fabe9 100644 --- a/hw/net/lasi_i82596.c +++ b/hw/net/lasi_i82596.c @@ -18,7 +18,6 @@ #include "hw/net/lasi_82596.h" #include "hw/net/i82596.h" #include "trace.h" -#include "sysemu/sysemu.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c index 3e6206044f..9278fdce0b 100644 --- a/hw/net/msf2-emac.c +++ b/hw/net/msf2-emac.c @@ -32,7 +32,6 @@ #include "qemu-common.h" #include "qemu/log.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "hw/registerfields.h" #include "hw/net/msf2-emac.h" #include "hw/net/mii.h" diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c index 10e85a4556..a6876a936d 100644 --- a/hw/net/spapr_llan.c +++ b/hw/net/spapr_llan.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/log.h" #include "qemu/module.h" #include "net/net.h" diff --git a/hw/net/xgmac.c b/hw/net/xgmac.c index 00859a7d50..0ab6ae91aa 100644 --- a/hw/net/xgmac.c +++ b/hw/net/xgmac.c @@ -29,7 +29,6 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" #include "net/net.h" #include "qom/object.h" diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index a14fc31e86..3d1205b8bd 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/char/serial.h" diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index d9969ac148..5b3e4efed5 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -32,13 +32,11 @@ #include "qemu/units.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "qemu/option.h" #include "qemu/config-file.h" #include "qemu/error-report.h" #include "sysemu/device_tree.h" #include "sysemu/reset.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" diff --git a/hw/nios2/generic_nommu.c b/hw/nios2/generic_nommu.c index 19899e2c1e..fbc18dbd04 100644 --- a/hw/nios2/generic_nommu.c +++ b/hw/nios2/generic_nommu.c @@ -29,9 +29,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" -#include "hw/sysbus.h" #include "hw/char/serial.h" #include "hw/boards.h" #include "exec/memory.h" diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c index 942a6d5342..5c13452308 100644 --- a/hw/nubus/nubus-bus.c +++ b/hw/nubus/nubus-bus.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "hw/nubus/nubus.h" -#include "hw/sysbus.h" #include "qapi/error.h" diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index 7b3460d52d..7f1db8c423 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -21,7 +21,6 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" -#include "exec/address-spaces.h" #include "hw/arm/nrf51.h" #include "hw/nvram/nrf51_nvm.h" #include "hw/qdev-properties.h" diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c index 01f7752014..fbfdf47e26 100644 --- a/hw/nvram/spapr_nvram.c +++ b/hw/nvram/spapr_nvram.c @@ -26,14 +26,12 @@ #include "qemu/module.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include <libfdt.h> #include "sysemu/block-backend.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" #include "sysemu/runstate.h" -#include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/nvram/chrp_nvram.h" #include "hw/ppc/spapr.h" diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 39f1d344ae..73fe383c2d 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -29,7 +29,6 @@ #include "net/net.h" #include "hw/loader.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "sysemu/qtest.h" diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index 2ccc96f02c..79c20bf28b 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -72,3 +72,7 @@ config REMOTE_PCIHOST config SH_PCI bool select PCI + +config MV64361 + bool + select PCI diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 2a2db7cea6..afb3d1f81d 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -49,7 +49,6 @@ #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "exec/address-spaces.h" #include "hw/misc/unimp.h" #include "hw/registerfields.h" #include "qom/object.h" diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index 87a896973e..34b3538beb 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -19,6 +19,8 @@ pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c')) pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c')) # PowerPC E500 boards pci_ss.add(when: 'CONFIG_PPCE500_PCI', if_true: files('ppce500.c')) +# Pegasos2 +pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c')) # ARM devices pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c')) diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c new file mode 100644 index 0000000000..20510d8680 --- /dev/null +++ b/hw/pci-host/mv64361.c @@ -0,0 +1,951 @@ +/* + * Marvell Discovery II MV64361 System Controller for + * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator + * + * Copyright (c) 2018-2020 BALATON Zoltan + * + * This work is licensed under the GNU GPL license version 2 or later. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_host.h" +#include "hw/irq.h" +#include "hw/intc/i8259.h" +#include "hw/qdev-properties.h" +#include "exec/address-spaces.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "trace.h" +#include "hw/pci-host/mv64361.h" +#include "mv643xx.h" + +#define TYPE_MV64361_PCI_BRIDGE "mv64361-pcibridge" + +static void mv64361_pcibridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->vendor_id = PCI_VENDOR_ID_MARVELL; + k->device_id = PCI_DEVICE_ID_MARVELL_MV6436X; + k->class_id = PCI_CLASS_BRIDGE_HOST; + /* + * PCI-facing part of the host bridge, + * not usable without the host-facing part + */ + dc->user_creatable = false; +} + +static const TypeInfo mv64361_pcibridge_info = { + .name = TYPE_MV64361_PCI_BRIDGE, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PCIDevice), + .class_init = mv64361_pcibridge_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + + +#define TYPE_MV64361_PCI "mv64361-pcihost" +OBJECT_DECLARE_SIMPLE_TYPE(MV64361PCIState, MV64361_PCI) + +struct MV64361PCIState { + PCIHostState parent_obj; + + uint8_t index; + MemoryRegion io; + MemoryRegion mem; + qemu_irq irq[PCI_NUM_PINS]; + + uint32_t io_base; + uint32_t io_size; + uint32_t mem_base[4]; + uint32_t mem_size[4]; + uint64_t remap[5]; +}; + +static int mv64361_pcihost_map_irq(PCIDevice *pci_dev, int n) +{ + return (n + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; +} + +static void mv64361_pcihost_set_irq(void *opaque, int n, int level) +{ + MV64361PCIState *s = opaque; + qemu_set_irq(s->irq[n], level); +} + +static void mv64361_pcihost_realize(DeviceState *dev, Error **errp) +{ + MV64361PCIState *s = MV64361_PCI(dev); + PCIHostState *h = PCI_HOST_BRIDGE(dev); + char *name; + + name = g_strdup_printf("pci%d-io", s->index); + memory_region_init(&s->io, OBJECT(dev), name, 0x10000); + g_free(name); + name = g_strdup_printf("pci%d-mem", s->index); + memory_region_init(&s->mem, OBJECT(dev), name, 1ULL << 32); + g_free(name); + name = g_strdup_printf("pci.%d", s->index); + h->bus = pci_register_root_bus(dev, name, mv64361_pcihost_set_irq, + mv64361_pcihost_map_irq, dev, + &s->mem, &s->io, 0, 4, TYPE_PCI_BUS); + g_free(name); + pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE); +} + +static Property mv64361_pcihost_props[] = { + DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void mv64361_pcihost_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = mv64361_pcihost_realize; + device_class_set_props(dc, mv64361_pcihost_props); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); +} + +static const TypeInfo mv64361_pcihost_info = { + .name = TYPE_MV64361_PCI, + .parent = TYPE_PCI_HOST_BRIDGE, + .instance_size = sizeof(MV64361PCIState), + .class_init = mv64361_pcihost_class_init, +}; + +static void mv64361_pci_register_types(void) +{ + type_register_static(&mv64361_pcihost_info); + type_register_static(&mv64361_pcibridge_info); +} + +type_init(mv64361_pci_register_types) + + +OBJECT_DECLARE_SIMPLE_TYPE(MV64361State, MV64361) + +struct MV64361State { + SysBusDevice parent_obj; + + MemoryRegion regs; + MV64361PCIState pci[2]; + MemoryRegion cpu_win[19]; + qemu_irq cpu_irq; + + /* registers state */ + uint32_t cpu_conf; + uint32_t regs_base; + uint32_t base_addr_enable; + uint64_t main_int_cr; + uint64_t cpu0_int_mask; + uint32_t gpp_io; + uint32_t gpp_level; + uint32_t gpp_value; + uint32_t gpp_int_cr; + uint32_t gpp_int_mask; + bool gpp_int_level; +}; + +enum mv64361_irq_cause { + MV64361_IRQ_DEVERR = 1, + MV64361_IRQ_DMAERR = 2, + MV64361_IRQ_CPUERR = 3, + MV64361_IRQ_IDMA0 = 4, + MV64361_IRQ_IDMA1 = 5, + MV64361_IRQ_IDMA2 = 6, + MV64361_IRQ_IDMA3 = 7, + MV64361_IRQ_TIMER0 = 8, + MV64361_IRQ_TIMER1 = 9, + MV64361_IRQ_TIMER2 = 10, + MV64361_IRQ_TIMER3 = 11, + MV64361_IRQ_PCI0 = 12, + MV64361_IRQ_SRAMERR = 13, + MV64361_IRQ_GBEERR = 14, + MV64361_IRQ_CERR = 15, + MV64361_IRQ_PCI1 = 16, + MV64361_IRQ_DRAMERR = 17, + MV64361_IRQ_WDNMI = 18, + MV64361_IRQ_WDE = 19, + MV64361_IRQ_PCI0IN = 20, + MV64361_IRQ_PCI0OUT = 21, + MV64361_IRQ_PCI1IN = 22, + MV64361_IRQ_PCI1OUT = 23, + MV64361_IRQ_P1_GPP0_7 = 24, + MV64361_IRQ_P1_GPP8_15 = 25, + MV64361_IRQ_P1_GPP16_23 = 26, + MV64361_IRQ_P1_GPP24_31 = 27, + MV64361_IRQ_P1_CPU_DB = 28, + /* 29-31: reserved */ + MV64361_IRQ_GBE0 = 32, + MV64361_IRQ_GBE1 = 33, + MV64361_IRQ_GBE2 = 34, + /* 35: reserved */ + MV64361_IRQ_SDMA0 = 36, + MV64361_IRQ_TWSI = 37, + MV64361_IRQ_SDMA1 = 38, + MV64361_IRQ_BRG = 39, + MV64361_IRQ_MPSC0 = 40, + MV64361_IRQ_MPSC1 = 41, + MV64361_IRQ_G0RX = 42, + MV64361_IRQ_G0TX = 43, + MV64361_IRQ_G0MISC = 44, + MV64361_IRQ_G1RX = 45, + MV64361_IRQ_G1TX = 46, + MV64361_IRQ_G1MISC = 47, + MV64361_IRQ_G2RX = 48, + MV64361_IRQ_G2TX = 49, + MV64361_IRQ_G2MISC = 50, + /* 51-55: reserved */ + MV64361_IRQ_P0_GPP0_7 = 56, + MV64361_IRQ_P0_GPP8_15 = 57, + MV64361_IRQ_P0_GPP16_23 = 58, + MV64361_IRQ_P0_GPP24_31 = 59, + MV64361_IRQ_P0_CPU_DB = 60, + /* 61-63: reserved */ +}; + +PCIBus *mv64361_get_pci_bus(DeviceState *dev, int n) +{ + MV64361State *mv = MV64361(dev); + return PCI_HOST_BRIDGE(&mv->pci[n])->bus; +} + +static void unmap_region(MemoryRegion *mr) +{ + if (memory_region_is_mapped(mr)) { + memory_region_del_subregion(get_system_memory(), mr); + object_unparent(OBJECT(mr)); + } +} + +static void map_pci_region(MemoryRegion *mr, MemoryRegion *parent, + struct Object *owner, const char *name, + hwaddr poffs, uint64_t size, hwaddr moffs) +{ + memory_region_init_alias(mr, owner, name, parent, poffs, size); + memory_region_add_subregion(get_system_memory(), moffs, mr); + trace_mv64361_region_map(name, poffs, size, moffs); +} + +static void set_mem_windows(MV64361State *s, uint32_t val) +{ + MV64361PCIState *p; + MemoryRegion *mr; + uint32_t mask; + int i; + + val &= 0x1fffff; + for (mask = 1, i = 0; i < 21; i++, mask <<= 1) { + if ((val & mask) != (s->base_addr_enable & mask)) { + trace_mv64361_region_enable(!(val & mask) ? "enable" : "disable", i); + /* + * 0-3 are SDRAM chip selects but we map all RAM directly + * 4-7 are device chip selects (not sure what those are) + * 8 is Boot device (ROM) chip select but we map that directly too + */ + if (i == 9) { + p = &s->pci[0]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->io, OBJECT(s), "pci0-io-win", + p->remap[4], (p->io_size + 1) << 16, + (p->io_base & 0xfffff) << 16); + } + } else if (i == 10) { + p = &s->pci[0]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem0-win", + p->remap[0], (p->mem_size[0] + 1) << 16, + (p->mem_base[0] & 0xfffff) << 16); + } + } else if (i == 11) { + p = &s->pci[0]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem1-win", + p->remap[1], (p->mem_size[1] + 1) << 16, + (p->mem_base[1] & 0xfffff) << 16); + } + } else if (i == 12) { + p = &s->pci[0]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem2-win", + p->remap[2], (p->mem_size[2] + 1) << 16, + (p->mem_base[2] & 0xfffff) << 16); + } + } else if (i == 13) { + p = &s->pci[0]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem3-win", + p->remap[3], (p->mem_size[3] + 1) << 16, + (p->mem_base[3] & 0xfffff) << 16); + } + } else if (i == 14) { + p = &s->pci[1]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->io, OBJECT(s), "pci1-io-win", + p->remap[4], (p->io_size + 1) << 16, + (p->io_base & 0xfffff) << 16); + } + } else if (i == 15) { + p = &s->pci[1]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem0-win", + p->remap[0], (p->mem_size[0] + 1) << 16, + (p->mem_base[0] & 0xfffff) << 16); + } + } else if (i == 16) { + p = &s->pci[1]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem1-win", + p->remap[1], (p->mem_size[1] + 1) << 16, + (p->mem_base[1] & 0xfffff) << 16); + } + } else if (i == 17) { + p = &s->pci[1]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem2-win", + p->remap[2], (p->mem_size[2] + 1) << 16, + (p->mem_base[2] & 0xfffff) << 16); + } + } else if (i == 18) { + p = &s->pci[1]; + mr = &s->cpu_win[i]; + unmap_region(mr); + if (!(val & mask)) { + map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem3-win", + p->remap[3], (p->mem_size[3] + 1) << 16, + (p->mem_base[3] & 0xfffff) << 16); + } + /* 19 is integrated SRAM */ + } else if (i == 20) { + mr = &s->regs; + unmap_region(mr); + if (!(val & mask)) { + memory_region_add_subregion(get_system_memory(), + (s->regs_base & 0xfffff) << 16, mr); + } + } + } + } + s->base_addr_enable = val; +} + +static void mv64361_update_irq(void *opaque, int n, int level) +{ + MV64361State *s = opaque; + uint64_t val = s->main_int_cr; + + if (level) { + val |= BIT_ULL(n); + } else { + val &= ~BIT_ULL(n); + } + if ((s->main_int_cr & s->cpu0_int_mask) != (val & s->cpu0_int_mask)) { + qemu_set_irq(s->cpu_irq, level); + } + s->main_int_cr = val; +} + +static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size) +{ + MV64361State *s = MV64361(opaque); + uint32_t ret = 0; + + switch (addr) { + case MV64340_CPU_CONFIG: + ret = s->cpu_conf; + break; + case MV64340_PCI_0_IO_BASE_ADDR: + ret = s->pci[0].io_base; + break; + case MV64340_PCI_0_IO_SIZE: + ret = s->pci[0].io_size; + break; + case MV64340_PCI_0_IO_ADDR_REMAP: + ret = s->pci[0].remap[4] >> 16; + break; + case MV64340_PCI_0_MEMORY0_BASE_ADDR: + ret = s->pci[0].mem_base[0]; + break; + case MV64340_PCI_0_MEMORY0_SIZE: + ret = s->pci[0].mem_size[0]; + break; + case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP: + ret = (s->pci[0].remap[0] & 0xffff0000) >> 16; + break; + case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP: + ret = s->pci[0].remap[0] >> 32; + break; + case MV64340_PCI_0_MEMORY1_BASE_ADDR: + ret = s->pci[0].mem_base[1]; + break; + case MV64340_PCI_0_MEMORY1_SIZE: + ret = s->pci[0].mem_size[1]; + break; + case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP: + ret = (s->pci[0].remap[1] & 0xffff0000) >> 16; + break; + case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP: + ret = s->pci[0].remap[1] >> 32; + break; + case MV64340_PCI_0_MEMORY2_BASE_ADDR: + ret = s->pci[0].mem_base[2]; + break; + case MV64340_PCI_0_MEMORY2_SIZE: + ret = s->pci[0].mem_size[2]; + break; + case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP: + ret = (s->pci[0].remap[2] & 0xffff0000) >> 16; + break; + case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP: + ret = s->pci[0].remap[2] >> 32; + break; + case MV64340_PCI_0_MEMORY3_BASE_ADDR: + ret = s->pci[0].mem_base[3]; + break; + case MV64340_PCI_0_MEMORY3_SIZE: + ret = s->pci[0].mem_size[3]; + break; + case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP: + ret = (s->pci[0].remap[3] & 0xffff0000) >> 16; + break; + case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP: + ret = s->pci[0].remap[3] >> 32; + break; + case MV64340_PCI_1_IO_BASE_ADDR: + ret = s->pci[1].io_base; + break; + case MV64340_PCI_1_IO_SIZE: + ret = s->pci[1].io_size; + break; + case MV64340_PCI_1_IO_ADDR_REMAP: + ret = s->pci[1].remap[4] >> 16; + break; + case MV64340_PCI_1_MEMORY0_BASE_ADDR: + ret = s->pci[1].mem_base[0]; + break; + case MV64340_PCI_1_MEMORY0_SIZE: + ret = s->pci[1].mem_size[0]; + break; + case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP: + ret = (s->pci[1].remap[0] & 0xffff0000) >> 16; + break; + case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP: + ret = s->pci[1].remap[0] >> 32; + break; + case MV64340_PCI_1_MEMORY1_BASE_ADDR: + ret = s->pci[1].mem_base[1]; + break; + case MV64340_PCI_1_MEMORY1_SIZE: + ret = s->pci[1].mem_size[1]; + break; + case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP: + ret = (s->pci[1].remap[1] & 0xffff0000) >> 16; + break; + case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP: + ret = s->pci[1].remap[1] >> 32; + break; + case MV64340_PCI_1_MEMORY2_BASE_ADDR: + ret = s->pci[1].mem_base[2]; + break; + case MV64340_PCI_1_MEMORY2_SIZE: + ret = s->pci[1].mem_size[2]; + break; + case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP: + ret = (s->pci[1].remap[2] & 0xffff0000) >> 16; + break; + case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP: + ret = s->pci[1].remap[2] >> 32; + break; + case MV64340_PCI_1_MEMORY3_BASE_ADDR: + ret = s->pci[1].mem_base[3]; + break; + case MV64340_PCI_1_MEMORY3_SIZE: + ret = s->pci[1].mem_size[3]; + break; + case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP: + ret = (s->pci[1].remap[3] & 0xffff0000) >> 16; + break; + case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP: + ret = s->pci[1].remap[3] >> 32; + break; + case MV64340_INTERNAL_SPACE_BASE_ADDR: + ret = s->regs_base; + break; + case MV64340_BASE_ADDR_ENABLE: + ret = s->base_addr_enable; + break; + case MV64340_PCI_0_CONFIG_ADDR: + ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), 0, size); + break; + case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ... + MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3: + ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), + addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, size); + break; + case MV64340_PCI_1_CONFIG_ADDR: + ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), 0, size); + break; + case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ... + MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3: + ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), + addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, size); + break; + case MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG: + /* FIXME: Should this be sent via the PCI bus somehow? */ + if (s->gpp_int_level && (s->gpp_value & BIT(31))) { + ret = pic_read_irq(isa_pic); + } + break; + case MV64340_MAIN_INTERRUPT_CAUSE_LOW: + ret = s->main_int_cr; + break; + case MV64340_MAIN_INTERRUPT_CAUSE_HIGH: + ret = s->main_int_cr >> 32; + break; + case MV64340_CPU_INTERRUPT0_MASK_LOW: + ret = s->cpu0_int_mask; + break; + case MV64340_CPU_INTERRUPT0_MASK_HIGH: + ret = s->cpu0_int_mask >> 32; + break; + case MV64340_CPU_INTERRUPT0_SELECT_CAUSE: + ret = s->main_int_cr; + if (s->main_int_cr & s->cpu0_int_mask) { + if (!(s->main_int_cr & s->cpu0_int_mask & 0xffffffff)) { + ret = s->main_int_cr >> 32 | BIT(30); + } else if ((s->main_int_cr & s->cpu0_int_mask) >> 32) { + ret |= BIT(31); + } + } + break; + case MV64340_CUNIT_ARBITER_CONTROL_REG: + ret = 0x11ff0000 | (s->gpp_int_level << 10); + break; + case MV64340_GPP_IO_CONTROL: + ret = s->gpp_io; + break; + case MV64340_GPP_LEVEL_CONTROL: + ret = s->gpp_level; + break; + case MV64340_GPP_VALUE: + ret = s->gpp_value; + break; + case MV64340_GPP_VALUE_SET: + case MV64340_GPP_VALUE_CLEAR: + ret = 0; + break; + case MV64340_GPP_INTERRUPT_CAUSE: + ret = s->gpp_int_cr; + break; + case MV64340_GPP_INTERRUPT_MASK0: + case MV64340_GPP_INTERRUPT_MASK1: + ret = s->gpp_int_mask; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + } + if (addr != MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG) { + trace_mv64361_reg_read(addr, ret); + } + return ret; +} + +static void warn_swap_bit(uint64_t val) +{ + if ((val & 0x3000000ULL) >> 24 != 1) { + qemu_log_mask(LOG_UNIMP, "%s: Data swap not implemented", __func__); + } +} + +static void mv64361_set_pci_mem_remap(MV64361State *s, int bus, int idx, + uint64_t val, bool high) +{ + if (high) { + s->pci[bus].remap[idx] = val; + } else { + s->pci[bus].remap[idx] &= 0xffffffff00000000ULL; + s->pci[bus].remap[idx] |= (val & 0xffffULL) << 16; + } +} + +static void mv64361_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + MV64361State *s = MV64361(opaque); + + trace_mv64361_reg_write(addr, val); + switch (addr) { + case MV64340_CPU_CONFIG: + s->cpu_conf = val & 0xe4e3bffULL; + s->cpu_conf |= BIT(23); + break; + case MV64340_PCI_0_IO_BASE_ADDR: + s->pci[0].io_base = val & 0x30fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + s->pci[0].remap[4] = (val & 0xffffULL) << 16; + } + break; + case MV64340_PCI_0_IO_SIZE: + s->pci[0].io_size = val & 0xffffULL; + break; + case MV64340_PCI_0_IO_ADDR_REMAP: + s->pci[0].remap[4] = (val & 0xffffULL) << 16; + break; + case MV64340_PCI_0_MEMORY0_BASE_ADDR: + s->pci[0].mem_base[0] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 0, 0, val, false); + } + break; + case MV64340_PCI_0_MEMORY0_SIZE: + s->pci[0].mem_size[0] = val & 0xffffULL; + break; + case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP: + case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 0, 0, val, + (addr == MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP)); + break; + case MV64340_PCI_0_MEMORY1_BASE_ADDR: + s->pci[0].mem_base[1] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 0, 1, val, false); + } + break; + case MV64340_PCI_0_MEMORY1_SIZE: + s->pci[0].mem_size[1] = val & 0xffffULL; + break; + case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP: + case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 0, 1, val, + (addr == MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP)); + break; + case MV64340_PCI_0_MEMORY2_BASE_ADDR: + s->pci[0].mem_base[2] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 0, 2, val, false); + } + break; + case MV64340_PCI_0_MEMORY2_SIZE: + s->pci[0].mem_size[2] = val & 0xffffULL; + break; + case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP: + case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 0, 2, val, + (addr == MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP)); + break; + case MV64340_PCI_0_MEMORY3_BASE_ADDR: + s->pci[0].mem_base[3] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 0, 3, val, false); + } + break; + case MV64340_PCI_0_MEMORY3_SIZE: + s->pci[0].mem_size[3] = val & 0xffffULL; + break; + case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP: + case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 0, 3, val, + (addr == MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP)); + break; + case MV64340_PCI_1_IO_BASE_ADDR: + s->pci[1].io_base = val & 0x30fffffULL; + warn_swap_bit(val); + break; + if (!(s->cpu_conf & BIT(27))) { + s->pci[1].remap[4] = (val & 0xffffULL) << 16; + } + break; + case MV64340_PCI_1_IO_SIZE: + s->pci[1].io_size = val & 0xffffULL; + break; + case MV64340_PCI_1_MEMORY0_BASE_ADDR: + s->pci[1].mem_base[0] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 1, 0, val, false); + } + break; + case MV64340_PCI_1_MEMORY0_SIZE: + s->pci[1].mem_size[0] = val & 0xffffULL; + break; + case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP: + case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 1, 0, val, + (addr == MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP)); + break; + case MV64340_PCI_1_MEMORY1_BASE_ADDR: + s->pci[1].mem_base[1] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 1, 1, val, false); + } + break; + case MV64340_PCI_1_MEMORY1_SIZE: + s->pci[1].mem_size[1] = val & 0xffffULL; + break; + case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP: + case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 1, 1, val, + (addr == MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP)); + break; + case MV64340_PCI_1_MEMORY2_BASE_ADDR: + s->pci[1].mem_base[2] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 1, 2, val, false); + } + break; + case MV64340_PCI_1_MEMORY2_SIZE: + s->pci[1].mem_size[2] = val & 0xffffULL; + break; + case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP: + case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 1, 2, val, + (addr == MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP)); + break; + case MV64340_PCI_1_MEMORY3_BASE_ADDR: + s->pci[1].mem_base[3] = val & 0x70fffffULL; + warn_swap_bit(val); + if (!(s->cpu_conf & BIT(27))) { + mv64361_set_pci_mem_remap(s, 1, 3, val, false); + } + break; + case MV64340_PCI_1_MEMORY3_SIZE: + s->pci[1].mem_size[3] = val & 0xffffULL; + break; + case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP: + case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP: + mv64361_set_pci_mem_remap(s, 1, 3, val, + (addr == MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP)); + break; + case MV64340_INTERNAL_SPACE_BASE_ADDR: + s->regs_base = val & 0xfffffULL; + break; + case MV64340_BASE_ADDR_ENABLE: + set_mem_windows(s, val); + break; + case MV64340_PCI_0_CONFIG_ADDR: + pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), 0, val, size); + break; + case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ... + MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3: + pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), + addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, val, size); + break; + case MV64340_PCI_1_CONFIG_ADDR: + pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), 0, val, size); + break; + case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ... + MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3: + pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), + addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, val, size); + break; + case MV64340_CPU_INTERRUPT0_MASK_LOW: + s->cpu0_int_mask &= 0xffffffff00000000ULL; + s->cpu0_int_mask |= val & 0xffffffffULL; + break; + case MV64340_CPU_INTERRUPT0_MASK_HIGH: + s->cpu0_int_mask &= 0xffffffffULL; + s->cpu0_int_mask |= val << 32; + break; + case MV64340_CUNIT_ARBITER_CONTROL_REG: + s->gpp_int_level = !!(val & BIT(10)); + break; + case MV64340_GPP_IO_CONTROL: + s->gpp_io = val; + break; + case MV64340_GPP_LEVEL_CONTROL: + s->gpp_level = val; + break; + case MV64340_GPP_VALUE: + s->gpp_value &= ~s->gpp_io; + s->gpp_value |= val & s->gpp_io; + break; + case MV64340_GPP_VALUE_SET: + s->gpp_value |= val & s->gpp_io; + break; + case MV64340_GPP_VALUE_CLEAR: + s->gpp_value &= ~(val & s->gpp_io); + break; + case MV64340_GPP_INTERRUPT_CAUSE: + if (!s->gpp_int_level && val != s->gpp_int_cr) { + int i; + uint32_t ch = s->gpp_int_cr ^ val; + s->gpp_int_cr = val; + for (i = 0; i < 4; i++) { + if ((ch & 0xff << i) && !(val & 0xff << i)) { + mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + i, 0); + } + } + } else { + s->gpp_int_cr = val; + } + break; + case MV64340_GPP_INTERRUPT_MASK0: + case MV64340_GPP_INTERRUPT_MASK1: + s->gpp_int_mask = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%" + HWADDR_PRIx " = %"PRIx64"\n", __func__, addr, val); + break; + } +} + +static const MemoryRegionOps mv64361_ops = { + .read = mv64361_read, + .write = mv64361_write, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void mv64361_gpp_irq(void *opaque, int n, int level) +{ + MV64361State *s = opaque; + uint32_t mask = BIT(n); + uint32_t val = s->gpp_value & ~mask; + + if (s->gpp_level & mask) { + level = !level; + } + val |= level << n; + if (val > s->gpp_value) { + s->gpp_value = val; + s->gpp_int_cr |= mask; + if (s->gpp_int_mask & mask) { + mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + n / 8, 1); + } + } else if (val < s->gpp_value) { + int b = n / 8; + s->gpp_value = val; + if (s->gpp_int_level && !(val & 0xff << b)) { + mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + b, 0); + } + } +} + +static void mv64361_realize(DeviceState *dev, Error **errp) +{ + MV64361State *s = MV64361(dev); + int i; + + s->base_addr_enable = 0x1fffff; + memory_region_init_io(&s->regs, OBJECT(s), &mv64361_ops, s, + TYPE_MV64361, 0x10000); + for (i = 0; i < 2; i++) { + g_autofree char *name = g_strdup_printf("pcihost%d", i); + object_initialize_child(OBJECT(dev), name, &s->pci[i], + TYPE_MV64361_PCI); + DeviceState *pci = DEVICE(&s->pci[i]); + qdev_prop_set_uint8(pci, "index", i); + sysbus_realize_and_unref(SYS_BUS_DEVICE(pci), &error_fatal); + } + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq); + qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32); + /* FIXME: PCI IRQ connections may be board specific */ + for (i = 0; i < PCI_NUM_PINS; i++) { + s->pci[1].irq[i] = qdev_get_gpio_in_named(dev, "gpp", 12 + i); + } +} + +static void mv64361_reset(DeviceState *dev) +{ + MV64361State *s = MV64361(dev); + int i, j; + + /* + * These values may be board specific + * Real chip supports init from an eprom but that's not modelled + */ + set_mem_windows(s, 0x1fffff); + s->cpu_conf = 0x28000ff; + s->regs_base = 0x100f100; + s->pci[0].io_base = 0x100f800; + s->pci[0].io_size = 0xff; + s->pci[0].mem_base[0] = 0x100c000; + s->pci[0].mem_size[0] = 0x1fff; + s->pci[0].mem_base[1] = 0x100f900; + s->pci[0].mem_size[1] = 0xff; + s->pci[0].mem_base[2] = 0x100f400; + s->pci[0].mem_size[2] = 0x1ff; + s->pci[0].mem_base[3] = 0x100f600; + s->pci[0].mem_size[3] = 0x1ff; + s->pci[1].io_base = 0x100fe00; + s->pci[1].io_size = 0xff; + s->pci[1].mem_base[0] = 0x1008000; + s->pci[1].mem_size[0] = 0x3fff; + s->pci[1].mem_base[1] = 0x100fd00; + s->pci[1].mem_size[1] = 0xff; + s->pci[1].mem_base[2] = 0x1002600; + s->pci[1].mem_size[2] = 0x1ff; + s->pci[1].mem_base[3] = 0x100ff80; + s->pci[1].mem_size[3] = 0x7f; + for (i = 0; i < 2; i++) { + for (j = 0; j < 4; j++) { + s->pci[i].remap[j] = s->pci[i].mem_base[j] << 16; + } + } + s->pci[0].remap[1] = 0; + s->pci[1].remap[1] = 0; + set_mem_windows(s, 0xfbfff); +} + +static void mv64361_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = mv64361_realize; + dc->reset = mv64361_reset; +} + +static const TypeInfo mv64361_type_info = { + .name = TYPE_MV64361, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MV64361State), + .class_init = mv64361_class_init, +}; + +static void mv64361_register_types(void) +{ + type_register_static(&mv64361_type_info); +} + +type_init(mv64361_register_types) diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h new file mode 100644 index 0000000000..cd26a43f18 --- /dev/null +++ b/hw/pci-host/mv643xx.h @@ -0,0 +1,918 @@ +/* + * mv643xx.h - MV-643XX Internal registers definition file. + * + * Copyright 2002 Momentum Computer, Inc. + * Author: Matthew Dharm <mdharm@momenco.com> + * Copyright 2002 GALILEO TECHNOLOGY, LTD. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef ASM_MV643XX_H +#define ASM_MV643XX_H + +/****************************************/ +/* Processor Address Space */ +/****************************************/ + +/* DDR SDRAM BAR and size registers */ + +#define MV64340_CS_0_BASE_ADDR 0x008 +#define MV64340_CS_0_SIZE 0x010 +#define MV64340_CS_1_BASE_ADDR 0x208 +#define MV64340_CS_1_SIZE 0x210 +#define MV64340_CS_2_BASE_ADDR 0x018 +#define MV64340_CS_2_SIZE 0x020 +#define MV64340_CS_3_BASE_ADDR 0x218 +#define MV64340_CS_3_SIZE 0x220 + +/* Devices BAR and size registers */ + +#define MV64340_DEV_CS0_BASE_ADDR 0x028 +#define MV64340_DEV_CS0_SIZE 0x030 +#define MV64340_DEV_CS1_BASE_ADDR 0x228 +#define MV64340_DEV_CS1_SIZE 0x230 +#define MV64340_DEV_CS2_BASE_ADDR 0x248 +#define MV64340_DEV_CS2_SIZE 0x250 +#define MV64340_DEV_CS3_BASE_ADDR 0x038 +#define MV64340_DEV_CS3_SIZE 0x040 +#define MV64340_BOOTCS_BASE_ADDR 0x238 +#define MV64340_BOOTCS_SIZE 0x240 + +/* PCI 0 BAR and size registers */ + +#define MV64340_PCI_0_IO_BASE_ADDR 0x048 +#define MV64340_PCI_0_IO_SIZE 0x050 +#define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058 +#define MV64340_PCI_0_MEMORY0_SIZE 0x060 +#define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080 +#define MV64340_PCI_0_MEMORY1_SIZE 0x088 +#define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258 +#define MV64340_PCI_0_MEMORY2_SIZE 0x260 +#define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280 +#define MV64340_PCI_0_MEMORY3_SIZE 0x288 + +/* PCI 1 BAR and size registers */ +#define MV64340_PCI_1_IO_BASE_ADDR 0x090 +#define MV64340_PCI_1_IO_SIZE 0x098 +#define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0 +#define MV64340_PCI_1_MEMORY0_SIZE 0x0a8 +#define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0 +#define MV64340_PCI_1_MEMORY1_SIZE 0x0b8 +#define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0 +#define MV64340_PCI_1_MEMORY2_SIZE 0x2a8 +#define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0 +#define MV64340_PCI_1_MEMORY3_SIZE 0x2b8 + +/* SRAM base address */ +#define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268 + +/* internal registers space base address */ +#define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068 + +/* Enables the CS , DEV_CS , PCI 0 and PCI 1 windows above */ +#define MV64340_BASE_ADDR_ENABLE 0x278 + +/****************************************/ +/* PCI remap registers */ +/****************************************/ + + /* PCI 0 */ +#define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0 +#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 +#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 +#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 +#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 +#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 +#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 +#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 +#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 + /* PCI 1 */ +#define MV64340_PCI_1_IO_ADDR_REMAP 0x108 +#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 +#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 +#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 +#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 +#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 +#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 +#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 +#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 + +#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 +#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 +#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 +#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 +#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 +#define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 +#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 +#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 + +/****************************************/ +/* CPU Control Registers */ +/****************************************/ + +#define MV64340_CPU_CONFIG 0x000 +#define MV64340_CPU_MODE 0x120 +#define MV64340_CPU_MASTER_CONTROL 0x160 +#define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150 +#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158 +#define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168 + +/****************************************/ +/* SMP RegisterS */ +/****************************************/ + +#define MV64340_SMP_WHO_AM_I 0x200 +#define MV64340_SMP_CPU0_DOORBELL 0x214 +#define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C +#define MV64340_SMP_CPU1_DOORBELL 0x224 +#define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C +#define MV64340_SMP_CPU0_DOORBELL_MASK 0x234 +#define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C +#define MV64340_SMP_SEMAPHOR0 0x244 +#define MV64340_SMP_SEMAPHOR1 0x24c +#define MV64340_SMP_SEMAPHOR2 0x254 +#define MV64340_SMP_SEMAPHOR3 0x25c +#define MV64340_SMP_SEMAPHOR4 0x264 +#define MV64340_SMP_SEMAPHOR5 0x26c +#define MV64340_SMP_SEMAPHOR6 0x274 +#define MV64340_SMP_SEMAPHOR7 0x27c + +/****************************************/ +/* CPU Sync Barrier Register */ +/****************************************/ + +#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 +#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 +#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 +#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 + +/****************************************/ +/* CPU Access Protect */ +/****************************************/ + +#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 +#define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188 +#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 +#define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198 +#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 +#define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 +#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 +#define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 + + +/****************************************/ +/* CPU Error Report */ +/****************************************/ + +#define MV64340_CPU_ERROR_ADDR_LOW 0x070 +#define MV64340_CPU_ERROR_ADDR_HIGH 0x078 +#define MV64340_CPU_ERROR_DATA_LOW 0x128 +#define MV64340_CPU_ERROR_DATA_HIGH 0x130 +#define MV64340_CPU_ERROR_PARITY 0x138 +#define MV64340_CPU_ERROR_CAUSE 0x140 +#define MV64340_CPU_ERROR_MASK 0x148 + +/****************************************/ +/* CPU Interface Debug Registers */ +/****************************************/ + +#define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360 +#define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368 +#define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370 +#define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378 +#define MV64340_PUNIT_MMASK 0x3e4 + +/****************************************/ +/* Integrated SRAM Registers */ +/****************************************/ + +#define MV64340_SRAM_CONFIG 0x380 +#define MV64340_SRAM_TEST_MODE 0X3F4 +#define MV64340_SRAM_ERROR_CAUSE 0x388 +#define MV64340_SRAM_ERROR_ADDR 0x390 +#define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8 +#define MV64340_SRAM_ERROR_DATA_LOW 0x398 +#define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0 +#define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8 + +/****************************************/ +/* SDRAM Configuration */ +/****************************************/ + +#define MV64340_SDRAM_CONFIG 0x1400 +#define MV64340_D_UNIT_CONTROL_LOW 0x1404 +#define MV64340_D_UNIT_CONTROL_HIGH 0x1424 +#define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408 +#define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c +#define MV64340_SDRAM_ADDR_CONTROL 0x1410 +#define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414 +#define MV64340_SDRAM_OPERATION 0x1418 +#define MV64340_SDRAM_MODE 0x141c +#define MV64340_EXTENDED_DRAM_MODE 0x1420 +#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 +#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 +#define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438 +#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 +#define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4 + +/****************************************/ +/* SDRAM Error Report */ +/****************************************/ + +#define MV64340_SDRAM_ERROR_DATA_LOW 0x1444 +#define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440 +#define MV64340_SDRAM_ERROR_ADDR 0x1450 +#define MV64340_SDRAM_RECEIVED_ECC 0x1448 +#define MV64340_SDRAM_CALCULATED_ECC 0x144c +#define MV64340_SDRAM_ECC_CONTROL 0x1454 +#define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458 + +/******************************************/ +/* Controlled Delay Line (CDL) Registers */ +/******************************************/ + +#define MV64340_DFCDL_CONFIG0 0x1480 +#define MV64340_DFCDL_CONFIG1 0x1484 +#define MV64340_DLL_WRITE 0x1488 +#define MV64340_DLL_READ 0x148c +#define MV64340_SRAM_ADDR 0x1490 +#define MV64340_SRAM_DATA0 0x1494 +#define MV64340_SRAM_DATA1 0x1498 +#define MV64340_SRAM_DATA2 0x149c +#define MV64340_DFCL_PROBE 0x14a0 + +/******************************************/ +/* Debug Registers */ +/******************************************/ + +#define MV64340_DUNIT_DEBUG_LOW 0x1460 +#define MV64340_DUNIT_DEBUG_HIGH 0x1464 +#define MV64340_DUNIT_MMASK 0X1b40 + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define MV64340_DEVICE_BANK0_PARAMETERS 0x45c +#define MV64340_DEVICE_BANK1_PARAMETERS 0x460 +#define MV64340_DEVICE_BANK2_PARAMETERS 0x464 +#define MV64340_DEVICE_BANK3_PARAMETERS 0x468 +#define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c +#define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0 +#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 +#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc +#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 + +/****************************************/ +/* Device interrupt registers */ +/****************************************/ + +#define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0 +#define MV64340_DEVICE_INTERRUPT_MASK 0x4d4 +#define MV64340_DEVICE_ERROR_ADDR 0x4d8 +#define MV64340_DEVICE_ERROR_DATA 0x4dc +#define MV64340_DEVICE_ERROR_PARITY 0x4e0 + +/****************************************/ +/* Device debug registers */ +/****************************************/ + +#define MV64340_DEVICE_DEBUG_LOW 0x4e4 +#define MV64340_DEVICE_DEBUG_HIGH 0x4e8 +#define MV64340_RUNIT_MMASK 0x4f0 + +/****************************************/ +/* PCI Slave Address Decoding registers */ +/****************************************/ + +#define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08 +#define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88 +#define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08 +#define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88 +#define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c +#define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c +#define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c +#define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c +#define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10 +#define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90 +#define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10 +#define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90 +#define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18 +#define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98 +#define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14 +#define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94 +#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 +#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 +#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c +#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c +#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 +#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 +#define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24 +#define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4 +#define MV64340_PCI_0_CPU_BAR_SIZE 0xd28 +#define MV64340_PCI_1_CPU_BAR_SIZE 0xda8 +#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 +#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 +#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c +#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c +#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c +#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc +#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 +#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 +#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 +#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 +#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c +#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc +#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c +#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc +#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 +#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 +#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 +#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 +#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C +#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C +#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 +#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 +#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 +#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 +#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 +#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 +#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 +#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 +#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 +#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 +#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 +#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 +#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c +#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc +#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 +#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 +#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 +#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 +#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 +#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 +#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c +#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec +#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 +#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 +#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 +#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 +#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 +#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 +#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 +#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 +#define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c +#define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc +#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 +#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 +#define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44 +#define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4 +#define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48 +#define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 + +/***********************************/ +/* PCI Control Register Map */ +/***********************************/ + +#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 +#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 +#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C +#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C +#define MV64340_PCI_0_COMMAND 0xc00 +#define MV64340_PCI_1_COMMAND 0xc80 +#define MV64340_PCI_0_MODE 0xd00 +#define MV64340_PCI_1_MODE 0xd80 +#define MV64340_PCI_0_RETRY 0xc04 +#define MV64340_PCI_1_RETRY 0xc84 +#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 +#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 +#define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38 +#define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8 +#define MV64340_PCI_0_ARBITER_CONTROL 0x1d00 +#define MV64340_PCI_1_ARBITER_CONTROL 0x1d80 +#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 +#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 +#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c +#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c +#define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 +#define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 +#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 +#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 +#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 +#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 +#define MV64340_PCI_0_P2P_CONFIG 0x1d14 +#define MV64340_PCI_1_P2P_CONFIG 0x1d94 + +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 +#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 + +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 +#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 + +/****************************************/ +/* PCI Configuration Access Registers */ +/****************************************/ + +#define MV64340_PCI_0_CONFIG_ADDR 0xcf8 +#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc +#define MV64340_PCI_1_CONFIG_ADDR 0xc78 +#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c +#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 +#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 + +/****************************************/ +/* PCI Error Report Registers */ +/****************************************/ + +#define MV64340_PCI_0_SERR_MASK 0xc28 +#define MV64340_PCI_1_SERR_MASK 0xca8 +#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40 +#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0 +#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44 +#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4 +#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48 +#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8 +#define MV64340_PCI_0_ERROR_COMMAND 0x1d50 +#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0 +#define MV64340_PCI_0_ERROR_CAUSE 0x1d58 +#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8 +#define MV64340_PCI_0_ERROR_MASK 0x1d5c +#define MV64340_PCI_1_ERROR_MASK 0x1ddc + +/****************************************/ +/* PCI Debug Registers */ +/****************************************/ + +#define MV64340_PCI_0_MMASK 0X1D24 +#define MV64340_PCI_1_MMASK 0X1DA4 + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + +#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000 +#define MV64340_PCI_STATUS_AND_COMMAND 0x004 +#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C + +#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010 +#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014 +#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018 +#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C +#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 +#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 +#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c +#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034 +#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C + /* capability list */ +#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define MV64340_PCI_VPD_ADDR 0x048 +#define MV64340_PCI_VPD_DATA 0x04c +#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050 +#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054 +#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 +#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c +#define MV64340_PCI_X_COMMAND 0x060 +#define MV64340_PCI_X_STATUS 0x064 +#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068 + +/***********************************************/ +/* PCI Configuration, Function 1, Registers */ +/***********************************************/ + +#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110 +#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114 +#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118 +#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c +#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 +#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 + +/***********************************************/ +/* PCI Configuration, Function 2, Registers */ +/***********************************************/ + +#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 +#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 +#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 +#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c +#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 +#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 3, Registers */ +/***********************************************/ + +#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 +#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 +#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 +#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c +#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220 +#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 4, Registers */ +/***********************************************/ + +#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 +#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 +#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 +#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c +#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420 +#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 + +/****************************************/ +/* Messaging Unit Registers (I20) */ +/****************************************/ + +#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 +#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C +#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 +#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 +#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 +#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C +#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 +#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 +#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 +#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 +#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 +#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 +#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 +#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 +#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 +#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C +#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 +#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 +#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 +#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC + +#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 +#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C +#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 +#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 +#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 +#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC +#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 +#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 +#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 +#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 +#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 +#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 +#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 +#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 +#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 +#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC +#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 +#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 +#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 +#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C + +#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 +#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C +#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 +#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 +#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 +#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C +#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 +#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 +#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 +#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 +#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 +#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 +#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 +#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 +#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 +#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C +#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 +#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 +#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 +#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC +#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 +#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 +#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C +#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 +#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 +#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 +#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC +#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 +#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 +#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 +#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 +#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 +#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 +#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 +#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 +#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 +#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC +#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 +#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 +#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 +#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ + +/*******************************************/ +/* CUNIT Registers */ +/*******************************************/ + + /* Address Decoding Register Map */ + +#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200 +#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208 +#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210 +#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218 +#define MV64340_CUNIT_SIZE0 0xf204 +#define MV64340_CUNIT_SIZE1 0xf20c +#define MV64340_CUNIT_SIZE2 0xf214 +#define MV64340_CUNIT_SIZE3 0xf21c +#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 +#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 +#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 +#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254 +#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258 +#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C + + /* Error Report Registers */ + +#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310 +#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314 +#define MV64340_CUNIT_ERROR_ADDR 0xf318 + + /* Cunit Control Registers */ + +#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300 +#define MV64340_CUNIT_CONFIG_REG 0xb40c +#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 + + /* Cunit Debug Registers */ + +#define MV64340_CUNIT_DEBUG_LOW 0xf340 +#define MV64340_CUNIT_DEBUG_HIGH 0xf344 +#define MV64340_CUNIT_MMASK 0xf380 + + /* MPSCs Clocks Routing Registers */ + +#define MV64340_MPSC_ROUTING_REG 0xb400 +#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404 +#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408 + + /* MPSCs Interrupts Registers */ + +#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port << 3)) +#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port << 3)) + +#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port << 12)) +#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port << 12)) +#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port << 12)) +#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port << 12)) + + /* MPSC0 Registers */ + + +/***************************************/ +/* SDMA Registers */ +/***************************************/ + +#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel << 13)) +#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel << 13)) +#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel << 13)) +#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel << 13)) +#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel << 13)) + +#define MV64340_SDMA_CAUSE_REG 0xb800 +#define MV64340_SDMA_MASK_REG 0xb880 + +/* BRG Interrupts */ + +#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg << 3)) +#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg << 3)) +#define MV64340_BRG_CAUSE_REG 0xb834 +#define MV64340_BRG_MASK_REG 0xb8b4 + +/****************************************/ +/* DMA Channel Control */ +/****************************************/ + +#define MV64340_DMA_CHANNEL0_CONTROL 0x840 +#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880 +#define MV64340_DMA_CHANNEL1_CONTROL 0x844 +#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884 +#define MV64340_DMA_CHANNEL2_CONTROL 0x848 +#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888 +#define MV64340_DMA_CHANNEL3_CONTROL 0x84C +#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C + + +/****************************************/ +/* IDMA Registers */ +/****************************************/ + +#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800 +#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804 +#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808 +#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C +#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810 +#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814 +#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818 +#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c +#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820 +#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824 +#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828 +#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C +#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 +#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 +#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 +#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C +#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 +#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 +#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 +#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C + + /* IDMA Address Decoding Base Address Registers */ + +#define MV64340_DMA_BASE_ADDR_REG0 0xa00 +#define MV64340_DMA_BASE_ADDR_REG1 0xa08 +#define MV64340_DMA_BASE_ADDR_REG2 0xa10 +#define MV64340_DMA_BASE_ADDR_REG3 0xa18 +#define MV64340_DMA_BASE_ADDR_REG4 0xa20 +#define MV64340_DMA_BASE_ADDR_REG5 0xa28 +#define MV64340_DMA_BASE_ADDR_REG6 0xa30 +#define MV64340_DMA_BASE_ADDR_REG7 0xa38 + + /* IDMA Address Decoding Size Address Register */ + +#define MV64340_DMA_SIZE_REG0 0xa04 +#define MV64340_DMA_SIZE_REG1 0xa0c +#define MV64340_DMA_SIZE_REG2 0xa14 +#define MV64340_DMA_SIZE_REG3 0xa1c +#define MV64340_DMA_SIZE_REG4 0xa24 +#define MV64340_DMA_SIZE_REG5 0xa2c +#define MV64340_DMA_SIZE_REG6 0xa34 +#define MV64340_DMA_SIZE_REG7 0xa3C + + /* IDMA Address Decoding High Address Remap and Access Protection Registers */ + +#define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60 +#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64 +#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68 +#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C +#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80 +#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 +#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 +#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 +#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c +#define MV64340_DMA_ARBITER_CONTROL 0x860 +#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0 + + /* IDMA Headers Retarget Registers */ + +#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84 +#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88 + + /* IDMA Interrupt Register */ + +#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0 +#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4 +#define MV64340_DMA_ERROR_ADDR 0x8c8 +#define MV64340_DMA_ERROR_SELECT 0x8cc + + /* IDMA Debug Register ( for internal use ) */ + +#define MV64340_DMA_DEBUG_LOW 0x8e0 +#define MV64340_DMA_DEBUG_HIGH 0x8e4 +#define MV64340_DMA_SPARE 0xA8C + +/****************************************/ +/* Timer_Counter */ +/****************************************/ + +#define MV64340_TIMER_COUNTER0 0x850 +#define MV64340_TIMER_COUNTER1 0x854 +#define MV64340_TIMER_COUNTER2 0x858 +#define MV64340_TIMER_COUNTER3 0x85C +#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864 +#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 +#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c + +/****************************************/ +/* Watchdog registers */ +/****************************************/ + +#define MV64340_WATCHDOG_CONFIG_REG 0xb410 +#define MV64340_WATCHDOG_VALUE_REG 0xb414 + +/****************************************/ +/* I2C Registers */ +/****************************************/ + +#define MV64XXX_I2C_OFFSET 0xc000 +#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020 + +/****************************************/ +/* GPP Interface Registers */ +/****************************************/ + +#define MV64340_GPP_IO_CONTROL 0xf100 +#define MV64340_GPP_LEVEL_CONTROL 0xf110 +#define MV64340_GPP_VALUE 0xf104 +#define MV64340_GPP_INTERRUPT_CAUSE 0xf108 +#define MV64340_GPP_INTERRUPT_MASK0 0xf10c +#define MV64340_GPP_INTERRUPT_MASK1 0xf114 +#define MV64340_GPP_VALUE_SET 0xf118 +#define MV64340_GPP_VALUE_CLEAR 0xf11c + +/****************************************/ +/* Interrupt Controller Registers */ +/****************************************/ + +/****************************************/ +/* Interrupts */ +/****************************************/ + +#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004 +#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c +#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014 +#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c +#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024 +#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034 +#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c +#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044 +#define MV64340_INTERRUPT0_MASK_0_LOW 0x054 +#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c +#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064 +#define MV64340_INTERRUPT1_MASK_0_LOW 0x074 +#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c +#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084 + +/****************************************/ +/* MPP Interface Registers */ +/****************************************/ + +#define MV64340_MPP_CONTROL0 0xf000 +#define MV64340_MPP_CONTROL1 0xf004 +#define MV64340_MPP_CONTROL2 0xf008 +#define MV64340_MPP_CONTROL3 0xf00c + +/****************************************/ +/* Serial Initialization registers */ +/****************************************/ + +#define MV64340_SERIAL_INIT_LAST_DATA 0xf324 +#define MV64340_SERIAL_INIT_CONTROL 0xf328 +#define MV64340_SERIAL_INIT_STATUS 0xf32c + +#endif /* ASM_MV643XX_H */ diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 5ad1424b31..89c1b53dd7 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -415,7 +415,6 @@ static const VMStateDescription vmstate_ppce500_pci = { } }; -#include "exec/address-spaces.h" static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) { diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 0a9162fba9..9fef74fc56 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -38,7 +38,6 @@ #include "hw/irq.h" #include "hw/loader.h" #include "hw/or-irq.h" -#include "exec/address-spaces.h" #include "elf.h" #include "qom/object.h" diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index f41a0cc301..949ecc21f2 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -34,7 +34,6 @@ #include "hw/irq.h" #include "hw/pci-bridge/simba.h" #include "hw/pci-host/sabre.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c index 734892f47c..08c1562e22 100644 --- a/hw/pci-host/sh_pci.c +++ b/hw/pci-host/sh_pci.c @@ -30,7 +30,6 @@ #include "hw/pci/pci_host.h" #include "qemu/bswap.h" #include "qemu/module.h" -#include "exec/address-spaces.h" #include "qom/object.h" #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci" diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index 7d8063ac42..dac86ad3f0 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -3,6 +3,12 @@ # grackle.c grackle_set_irq(int irq_num, int level) "set_irq num %d level %d" +# mv64361.c +mv64361_region_map(const char *name, uint64_t poffs, uint64_t size, uint64_t moffs) "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64 +mv64361_region_enable(const char *op, int num) "Should %s region %d" +mv64361_reg_read(uint64_t addr, uint32_t val) "0x%"PRIx64" -> 0x%x" +mv64361_reg_write(uint64_t addr, uint64_t val) "0x%"PRIx64" <- 0x%"PRIx64 + # sabre.c sabre_set_request(int irq_num) "request irq %d" sabre_clear_request(int irq_num) "clear request irq %d" diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 8f35e13a0c..377084f1a8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -45,7 +45,6 @@ #include "trace.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" -#include "exec/address-spaces.h" #include "hw/hotplug.h" #include "hw/boards.h" #include "qapi/error.h" diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index 3534006f99..5abbe83220 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -23,7 +23,6 @@ #include "hw/pci/pci.h" #include "hw/pci/pcie_host.h" #include "qemu/module.h" -#include "exec/address-spaces.h" /* a helper function to get a PCIDevice for a given mmconfig address */ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, diff --git a/hw/pcmcia/meson.build b/hw/pcmcia/meson.build index ab50bd325d..51f2512b8e 100644 --- a/hw/pcmcia/meson.build +++ b/hw/pcmcia/meson.build @@ -1,2 +1,2 @@ -softmmu_ss.add(files('pcmcia.c')) +softmmu_ss.add(when: 'CONFIG_PCMCIA', if_true: files('pcmcia.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c')) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index d11dc30509..e51e0e5e5a 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -68,6 +68,15 @@ config SAM460EX select USB_OHCI select FDT_PPC +config PEGASOS2 + bool + select MV64361 + select VT82C686 + select IDE_VIA + select SMBUS_EEPROM +# This should come with VT82C686 + select ACPI_X86 + config PREP bool imply PCI_DEVICES diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 79467ac512..95451414dd 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -25,7 +25,6 @@ #include "qemu/config-file.h" #include "hw/char/serial.h" #include "hw/pci/pci.h" -#include "hw/boards.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -39,7 +38,6 @@ #include "hw/loader.h" #include "elf.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "qemu/host-utils.h" #include "qemu/option.h" #include "hw/pci-host/ppce500.h" diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 2175962846..7bb7ac3997 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -58,7 +58,6 @@ #include "hw/pci/pci.h" #include "net/net.h" #include "sysemu/sysemu.h" -#include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #include "hw/char/escc.h" #include "hw/misc/macio/macio.h" @@ -71,7 +70,6 @@ #include "sysemu/reset.h" #include "kvm_ppc.h" #include "hw/usb.h" -#include "exec/address-spaces.h" #include "hw/sysbus.h" #include "trace.h" @@ -157,6 +155,10 @@ static void ppc_core99_init(MachineState *machine) } /* allocate RAM */ + if (machine->ram_size > 2 * GiB) { + error_report("RAM size more than 2 GiB is not supported"); + exit(1); + } memory_region_add_subregion(get_system_memory(), 0, machine->ram); /* allocate and load firmware ROM */ diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 963d247f5f..de2be960e6 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -38,7 +38,6 @@ #include "hw/isa/isa.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" -#include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #include "hw/char/escc.h" #include "hw/misc/macio/macio.h" @@ -49,7 +48,6 @@ #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "kvm_ppc.h" -#include "exec/address-spaces.h" #define MAX_IDE_BUS 2 #define CFG_ADDR 0xf0000510 diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 218631c883..86d6f379d1 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -78,5 +78,7 @@ ppc_ss.add(when: 'CONFIG_E500', if_true: files( )) # PowerPC 440 Xilinx ML507 reference board. ppc_ss.add(when: 'CONFIG_VIRTEX', if_true: files('virtex_ml507.c')) +# Pegasos2 +ppc_ss.add(when: 'CONFIG_PEGASOS2', if_true: files('pegasos2.c')) hw_arch += {'ppc': ppc_ss} diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c new file mode 100644 index 0000000000..0bfd0928aa --- /dev/null +++ b/hw/ppc/pegasos2.c @@ -0,0 +1,144 @@ +/* + * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator + * + * Copyright (c) 2018-2020 BALATON Zoltan + * + * This work is licensed under the GNU GPL license version 2 or later. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/ppc/ppc.h" +#include "hw/sysbus.h" +#include "hw/pci/pci_host.h" +#include "hw/irq.h" +#include "hw/pci-host/mv64361.h" +#include "hw/isa/vt82c686.h" +#include "hw/ide/pci.h" +#include "hw/i2c/smbus_eeprom.h" +#include "hw/qdev-properties.h" +#include "sysemu/reset.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/fw-path-provider.h" +#include "elf.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "sysemu/kvm.h" +#include "kvm_ppc.h" +#include "exec/address-spaces.h" +#include "trace.h" +#include "qemu/datadir.h" +#include "sysemu/device_tree.h" + +#define PROM_FILENAME "pegasos2.rom" +#define PROM_ADDR 0xfff00000 +#define PROM_SIZE 0x80000 + +#define BUS_FREQ_HZ 133333333 + +static void pegasos2_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu = opaque; + + cpu_reset(CPU(cpu)); + cpu->env.spr[SPR_HID1] = 7ULL << 28; +} + +static void pegasos2_init(MachineState *machine) +{ + PowerPCCPU *cpu = NULL; + MemoryRegion *rom = g_new(MemoryRegion, 1); + DeviceState *mv; + PCIBus *pci_bus; + PCIDevice *dev; + I2CBus *i2c_bus; + const char *fwname = machine->firmware ?: PROM_FILENAME; + char *filename; + int sz; + uint8_t *spd_data; + + /* init CPU */ + cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); + if (PPC_INPUT(&cpu->env) != PPC_FLAGS_INPUT_6xx) { + error_report("Incompatible CPU, only 6xx bus supported"); + exit(1); + } + + /* Set time-base frequency */ + cpu_ppc_tb_init(&cpu->env, BUS_FREQ_HZ / 4); + qemu_register_reset(pegasos2_cpu_reset, cpu); + + /* RAM */ + memory_region_add_subregion(get_system_memory(), 0, machine->ram); + + /* allocate and load firmware */ + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); + if (!filename) { + error_report("Could not find firmware '%s'", fwname); + exit(1); + } + memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); + memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); + sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, + PPC_ELF_MACHINE, 0, 0); + if (sz <= 0) { + sz = load_image_targphys(filename, PROM_ADDR, PROM_SIZE); + } + if (sz <= 0 || sz > PROM_SIZE) { + error_report("Could not load firmware '%s'", filename); + exit(1); + } + g_free(filename); + + /* Marvell Discovery II system controller */ + mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, + ((qemu_irq *)cpu->env.irq_inputs)[PPC6xx_INPUT_INT])); + pci_bus = mv64361_get_pci_bus(mv, 1); + + /* VIA VT8231 South Bridge (multifunction PCI device) */ + /* VT8231 function 0: PCI-to-ISA Bridge */ + dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true, + TYPE_VT8231_ISA); + qdev_connect_gpio_out(DEVICE(dev), 0, + qdev_get_gpio_in_named(mv, "gpp", 31)); + + /* VT8231 function 1: IDE Controller */ + dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide"); + pci_ide_create_devs(dev); + + /* VT8231 function 2-3: USB Ports */ + pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci"); + pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci"); + + /* VT8231 function 4: Power Management Controller */ + dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM); + i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); + spd_data = spd_data_generate(DDR, machine->ram_size); + smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); + + /* VT8231 function 5-6: AC97 Audio & Modem */ + pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97); + pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97); + + /* other PC hardware */ + pci_vga_init(pci_bus); +} + +static void pegasos2_machine(MachineClass *mc) +{ + mc->desc = "Genesi/bPlan Pegasos II"; + mc->init = pegasos2_init; + mc->block_default_type = IF_IDE; + mc->default_boot_order = "cd"; + mc->default_display = "std"; + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); + mc->default_ram_id = "pegasos2.ram"; + mc->default_ram_size = 512 * MiB; +} + +DEFINE_MACHINE("pegasos2", pegasos2_machine) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 77af846cdf..ffe01977cd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -32,14 +32,12 @@ #include "sysemu/device_tree.h" #include "sysemu/hw_accel.h" #include "target/ppc/cpu.h" -#include "qemu/log.h" #include "hw/ppc/fdt.h" #include "hw/ppc/ppc.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_core.h" #include "hw/loader.h" #include "hw/nmi.h" -#include "exec/address-spaces.h" #include "qapi/visitor.h" #include "monitor/monitor.h" #include "hw/intc/intc.h" @@ -53,7 +51,6 @@ #include "hw/ppc/pnv_pnor.h" #include "hw/isa/isa.h" -#include "hw/boards.h" #include "hw/char/serial.h" #include "hw/rtc/mc146818rtc.h" diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index bd2bf2e044..8c2a15a0fb 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -29,6 +29,7 @@ #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" +#include "helper_regs.h" static const char *pnv_core_cpu_typename(PnvCore *pc) { @@ -55,8 +56,8 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) env->gpr[3] = PNV_FDT_ADDR; env->nip = 0x10; env->msr |= MSR_HVB; /* Hypervisor mode */ - env->spr[SPR_HRMOR] = pc->hrmor; + hreg_compute_hflags(env); pcc->intc_reset(pc->chip, cpu); } diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c index 4b455de1ea..5ef1cf2afb 100644 --- a/hw/ppc/pnv_pnor.c +++ b/hw/ppc/pnv_pnor.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/units.h" #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 3e868c8c8d..cd9a2c5952 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -26,7 +26,6 @@ #include "qapi/error.h" #include "monitor/monitor.h" -#include "exec/address-spaces.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" @@ -466,7 +465,7 @@ static void pnv_psi_reset(DeviceState *dev) static void pnv_psi_reset_handler(void *dev) { - device_legacy_reset(DEVICE(dev)); + device_cold_reset(DEVICE(dev)); } static void pnv_psi_realize(DeviceState *dev, Error **errp) @@ -710,7 +709,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, break; case PSIHB9_INTERRUPT_CONTROL: if (val & PSIHB9_IRQ_RESET) { - device_legacy_reset(DEVICE(&psi9->source)); + device_cold_reset(DEVICE(&psi9->source)); } psi->regs[reg] = val; break; diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index bf28d6bfc8..7375bf4fa9 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/ppc/ppc.h" #include "hw/ppc/ppc_e500.h" diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 8f77887fb1..972a7a4a3e 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -34,15 +34,12 @@ #include "ppc405.h" #include "hw/rtc/m48t59.h" #include "hw/block/flash.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/block-backend.h" #include "hw/boards.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "qemu/cutils.h" #define BIOS_FILENAME "ppc405_rom.bin" diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index fe047074a1..e632c408bd 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -34,7 +34,6 @@ #include "qemu/timer.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" -#include "qemu/log.h" #include "exec/address-spaces.h" #include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index b7539aa721..7fb620b9a0 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -25,7 +25,6 @@ #include "sysemu/device_tree.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "hw/char/serial.h" #include "hw/ppc/ppc.h" #include "ppc405.h" diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index 91cbcd0504..788d25514a 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -28,7 +28,6 @@ #include "hw/ppc/ppc4xx.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index f6f89058ab..993e3ba955 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -14,9 +14,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/irq.h" -#include "exec/address-spaces.h" #include "exec/memory.h" #include "hw/ppc/ppc.h" #include "hw/qdev-properties.h" diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index fe9d4f7155..980c48944f 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -29,7 +29,6 @@ #include "hw/irq.h" #include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" -#include "hw/boards.h" #include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" #include "qemu/log.h" diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c index e8789f64e8..8147ba6f94 100644 --- a/hw/ppc/ppc4xx_pci.c +++ b/hw/ppc/ppc4xx_pci.c @@ -28,7 +28,6 @@ #include "sysemu/reset.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 974c0c8a75..10b643861f 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -28,7 +28,6 @@ #include "qemu/timer.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "qemu/log.h" #include "hw/loader.h" #include "kvm_ppc.h" diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index f1b1efdcef..acfc2a91d8 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -24,12 +24,10 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/rtc/m48t59.h" #include "hw/char/serial.h" #include "hw/block/fdc.h" #include "net/net.h" -#include "sysemu/sysemu.h" #include "hw/isa/isa.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" @@ -38,7 +36,6 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/log.h" -#include "hw/irq.h" #include "hw/loader.h" #include "hw/rtc/mc146818rtc.h" #include "hw/isa/pc87312.h" @@ -46,7 +43,6 @@ #include "sysemu/arch_init.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" -#include "exec/address-spaces.h" #include "trace.h" #include "elf.h" #include "qemu/units.h" diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c index 4db5b51a2d..c0bc212e92 100644 --- a/hw/ppc/rs6000_mc.c +++ b/hw/ppc/rs6000_mc.c @@ -23,7 +23,6 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "exec/address-spaces.h" -#include "hw/boards.h" #include "qapi/error.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 0c6baf77e8..0737234d66 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -24,7 +24,6 @@ #include "sysemu/block-backend.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "exec/memory.h" #include "ppc440.h" #include "ppc405.h" diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 529ff056dd..8f40319aee 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -54,7 +54,6 @@ #include "cpu-models.h" #include "hw/core/cpu.h" -#include "hw/boards.h" #include "hw/ppc/ppc.h" #include "hw/loader.h" @@ -70,7 +69,6 @@ #include "hw/virtio/virtio-scsi.h" #include "hw/virtio/vhost-scsi-common.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" #include "hw/usb.h" #include "qemu/config-file.h" @@ -100,7 +98,7 @@ * * We load our kernel at 4M, leaving space for SLOF initial image */ -#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ +#define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ #define FW_MAX_SIZE 0x400000 #define FW_FILE_NAME "slof.bin" #define FW_OVERHEAD 0x2800000 @@ -1617,11 +1615,11 @@ static void spapr_machine_reset(MachineState *machine) spapr_clear_pending_events(spapr); /* - * We place the device tree and RTAS just below either the top of the RMA, + * We place the device tree just below either the top of the RMA, * or just below 2GB, whichever is lower, so that it can be * processed with 32-bit real mode code if necessary */ - fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; + fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); @@ -2694,7 +2692,7 @@ static void spapr_machine_init(MachineState *machine) spapr->rma_size = spapr_rma_size(spapr, &error_fatal); /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ - load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; + load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; /* * VSMT must be set in order to be able to compute VCPU ids, ie to @@ -4487,7 +4485,16 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) mc->init = spapr_machine_init; mc->reset = spapr_machine_reset; mc->block_default_type = IF_SCSI; - mc->max_cpus = 1024; + + /* + * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values + * should be limited by the host capability instead of hardcoded. + * max_cpus for KVM guests will be checked in kvm_init(), and TCG + * guests are welcome to have as many CPUs as the host are capable + * of emulate. + */ + mc->max_cpus = INT32_MAX; + mc->no_parallel = 1; mc->default_boot_order = ""; mc->default_ram_size = 512 * MiB; diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index 9e16505fa1..a2f2634601 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qapi/qmp/qnull.h" -#include "cpu.h" #include "qemu/cutils.h" #include "hw/ppc/spapr_drc.h" #include "qom/object.h" @@ -151,9 +150,32 @@ static uint32_t drc_isolate_logical(SpaprDrc *drc) static uint32_t drc_unisolate_logical(SpaprDrc *drc) { + SpaprMachineState *spapr = NULL; + switch (drc->state) { case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: + /* + * Unisolating a logical DRC that was marked for unplug + * means that the kernel is refusing the removal. + */ + if (drc->unplug_requested && drc->dev) { + if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB) { + spapr = SPAPR_MACHINE(qdev_get_machine()); + + spapr_memory_unplug_rollback(spapr, drc->dev); + } + + drc->unplug_requested = false; + error_report("Device hotunplug rejected by the guest " + "for device %s", drc->dev->id); + + /* + * TODO: send a QAPI DEVICE_UNPLUG_ERROR event when + * it is implemented. + */ + } + return RTAS_OUT_SUCCESS; /* Nothing to do */ case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: break; /* see below */ diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index d51daedfa6..0cfc19be19 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "sysemu/device_tree.h" #include "sysemu/runstate.h" diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7b5cd3553c..16c719c3de 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -7,7 +7,6 @@ #include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/error-report.h" -#include "cpu.h" #include "exec/exec-all.h" #include "helper_regs.h" #include "hw/ppc/spapr.h" @@ -1395,7 +1394,13 @@ static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, return H_P4; } - if (mflags == AIL_RESERVED) { + if (mflags == 1) { + /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ + return H_UNSUPPORTED_FLAG; + } + + if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { + /* AIL=2 is reserved in POWER10 (ISA v3.1) */ return H_UNSUPPORTED_FLAG; } diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 24537ffcbd..db01071858 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -25,7 +25,6 @@ #include "kvm_ppc.h" #include "migration/vmstate.h" #include "sysemu/dma.h" -#include "exec/address-spaces.h" #include "trace.h" #include "hw/ppc/spapr.h" diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c index b46c36917c..252204e25f 100644 --- a/hw/ppc/spapr_nvdimm.c +++ b/hw/ppc/spapr_nvdimm.c @@ -31,6 +31,10 @@ #include "qemu/range.h" #include "hw/ppc/spapr_numa.h" +/* DIMM health bitmap bitmap indicators. Taken from kernel's papr_scm.c */ +/* SCM device is unable to persist memory contents */ +#define PAPR_PMEM_UNARMED PPC_BIT(0) + bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm, uint64_t size, Error **errp) { @@ -467,6 +471,37 @@ static target_ulong h_scm_unbind_all(PowerPCCPU *cpu, SpaprMachineState *spapr, return H_SUCCESS; } +static target_ulong h_scm_health(PowerPCCPU *cpu, SpaprMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + + NVDIMMDevice *nvdimm; + uint64_t hbitmap = 0; + uint32_t drc_index = args[0]; + SpaprDrc *drc = spapr_drc_by_index(drc_index); + const uint64_t hbitmap_mask = PAPR_PMEM_UNARMED; + + + /* Ensure that the drc is valid & is valid PMEM dimm and is plugged in */ + if (!drc || !drc->dev || + spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { + return H_PARAMETER; + } + + nvdimm = NVDIMM(drc->dev); + + /* Update if the nvdimm is unarmed and send its status via health bitmaps */ + if (object_property_get_bool(OBJECT(nvdimm), NVDIMM_UNARMED_PROP, NULL)) { + hbitmap |= PAPR_PMEM_UNARMED; + } + + /* Update the out args with health bitmap/mask */ + args[0] = hbitmap; + args[1] = hbitmap_mask; + + return H_SUCCESS; +} + static void spapr_scm_register_types(void) { /* qemu/scm specific hcalls */ @@ -475,6 +510,7 @@ static void spapr_scm_register_types(void) spapr_register_hypercall(H_SCM_BIND_MEM, h_scm_bind_mem); spapr_register_hypercall(H_SCM_UNBIND_MEM, h_scm_unbind_mem); spapr_register_hypercall(H_SCM_UNBIND_ALL, h_scm_unbind_all); + spapr_register_hypercall(H_SCM_HEALTH, h_scm_health); } type_init(spapr_scm_register_types) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index feba18cb12..7a725855f9 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/sysbus.h" #include "migration/vmstate.h" @@ -35,7 +34,6 @@ #include "hw/pci/pci_host.h" #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" #include <libfdt.h> #include "trace.h" diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index e0547b1740..7817cf72ee 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include <linux/vfio.h> -#include "cpu.h" #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" #include "hw/pci/msix.h" diff --git a/hw/ppc/spapr_rng.c b/hw/ppc/spapr_rng.c index d14800e9de..df5c4b9687 100644 --- a/hw/ppc/spapr_rng.c +++ b/hw/ppc/spapr_rng.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/module.h" diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 8a79f9c628..03355b4c0a 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/log.h" #include "qemu/error-report.h" #include "sysemu/sysemu.h" @@ -41,7 +40,6 @@ #include "hw/ppc/spapr_rtas.h" #include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/ppc.h" -#include "hw/boards.h" #include <libfdt.h> #include "hw/ppc/spapr_drc.h" @@ -51,6 +49,7 @@ #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" #include "migration/blocker.h" +#include "helper_regs.h" static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, @@ -163,6 +162,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, cpu_synchronize_state(CPU(newcpu)); env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); + hreg_compute_hflags(env); /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ lpcr = env->spr[SPR_LPCR]; diff --git a/hw/ppc/spapr_rtas_ddw.c b/hw/ppc/spapr_rtas_ddw.c index 3501b05819..3e826e1308 100644 --- a/hw/ppc/spapr_rtas_ddw.c +++ b/hw/ppc/spapr_rtas_ddw.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "hw/ppc/spapr.h" diff --git a/hw/ppc/spapr_rtc.c b/hw/ppc/spapr_rtc.c index 68cfc578a3..fba4dfca35 100644 --- a/hw/ppc/spapr_rtc.c +++ b/hw/ppc/spapr_rtc.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qemu-common.h" -#include "cpu.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" #include "hw/ppc/spapr.h" diff --git a/hw/ppc/spapr_tpm_proxy.c b/hw/ppc/spapr_tpm_proxy.c index a01f81f9e0..2454086744 100644 --- a/hw/ppc/spapr_tpm_proxy.c +++ b/hw/ppc/spapr_tpm_proxy.c @@ -15,7 +15,6 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/reset.h" -#include "cpu.h" #include "hw/ppc/spapr.h" #include "hw/qdev-properties.h" #include "trace.h" diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index ef06e0362c..b59452bcd6 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -310,7 +310,7 @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq) static void spapr_vio_quiesce_one(SpaprVioDevice *dev) { if (dev->tcet) { - device_legacy_reset(DEVICE(dev->tcet)); + device_cold_reset(DEVICE(dev->tcet)); } free_crq(dev); } diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index cb421570da..9c575403b8 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -38,9 +38,7 @@ #include "elf.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/option.h" -#include "exec/address-spaces.h" #include "hw/intc/ppc-uic.h" #include "hw/ppc/ppc.h" diff --git a/hw/remote/iohub.c b/hw/remote/iohub.c index e4ff131a6b..547d597f0f 100644 --- a/hw/remote/iohub.c +++ b/hw/remote/iohub.c @@ -15,7 +15,6 @@ #include "hw/pci/pci_ids.h" #include "hw/pci/pci_bus.h" #include "qemu/thread.h" -#include "hw/boards.h" #include "hw/remote/machine.h" #include "hw/remote/iohub.h" #include "qemu/main-loop.h" diff --git a/hw/remote/machine.c b/hw/remote/machine.c index c0ab4f528a..952105eab5 100644 --- a/hw/remote/machine.c +++ b/hw/remote/machine.c @@ -17,7 +17,6 @@ #include "qemu-common.h" #include "hw/remote/machine.h" -#include "exec/address-spaces.h" #include "exec/memory.h" #include "qapi/error.h" #include "hw/pci/pci_host.h" diff --git a/hw/remote/memory.c b/hw/remote/memory.c index 32085b1e05..2d4174614a 100644 --- a/hw/remote/memory.c +++ b/hw/remote/memory.c @@ -12,7 +12,6 @@ #include "qemu-common.h" #include "hw/remote/memory.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" #include "qapi/error.h" diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-listener.c index af1fa6f5aa..901dbf1357 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -14,9 +14,7 @@ #include "qemu/range.h" #include "exec/memory.h" #include "exec/cpu-common.h" -#include "cpu.h" #include "exec/ram_addr.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "hw/remote/mpqemu-link.h" #include "hw/remote/proxy-memory-listener.h" diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c4146b7a6b..6cbd17ebf2 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -36,12 +36,10 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/units.h" #include "qemu/cutils.h" #include "qapi/error.h" #include "hw/boards.h" -#include "hw/irq.h" #include "hw/loader.h" #include "hw/sysbus.h" #include "chardev/char.h" diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index 4f92307102..7fe92d402f 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -18,7 +18,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index e168bffe69..dc9dea117e 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -24,7 +24,6 @@ #include "hw/boards.h" #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" -#include "exec/address-spaces.h" #include "qemu/units.h" #include "sysemu/sysemu.h" diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index f939bcf9ea..3e8b44b2c0 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -29,7 +29,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" @@ -48,7 +47,6 @@ #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" static MemMapEntry sifive_e_memmap[] = { [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 }, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7b59942369..698637e8e1 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -35,7 +35,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/visitor.h" diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ec7cb2f707..fe0806a476 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -24,7 +24,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c0dc69ff33..95a11adaa2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c index d54929e861..690f4e071a 100644 --- a/hw/rtc/m48t59.c +++ b/hw/rtc/m48t59.c @@ -32,7 +32,6 @@ #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/bcd.h" #include "qemu/module.h" diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index 5d0fcacd0c..3d2d3854e7 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -42,7 +42,6 @@ #include "qapi/error.h" #include "qapi/qapi-events-misc-target.h" #include "qapi/visitor.h" -#include "exec/address-spaces.h" #include "hw/rtc/mc146818rtc_regs.h" #ifdef TARGET_I386 @@ -1040,6 +1039,7 @@ static void rtc_class_initfn(ObjectClass *klass, void *data) dc->vmsd = &vmstate_rtc; isa->build_aml = rtc_build_aml; device_class_set_props(dc, mc146818rtc_properties); + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo mc146818rtc_info = { diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index b1d7c2488f..75d1fec6ca 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -21,12 +21,8 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" -#include "hw/hw.h" -#include "hw/sysbus.h" #include "hw/loader.h" #include "hw/rx/rx62n.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "sysemu/device_tree.h" #include "hw/boards.h" @@ -93,6 +89,7 @@ static void rx_gdbsim_init(MachineState *machine) char *sz = size_to_str(mc->default_ram_size); error_report("Invalid RAM size, should be more than %s", sz); g_free(sz); + exit(1); } /* Allocate memory space */ diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 9c34ce14de..fa5add9f9d 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -23,13 +23,11 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/hw.h" #include "hw/rx/rx62n.h" #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" -#include "cpu.h" #include "qom/object.h" /* diff --git a/hw/s390x/3270-ccw.c b/hw/s390x/3270-ccw.c index f3e7342b1e..25e628f575 100644 --- a/hw/s390x/3270-ccw.c +++ b/hw/s390x/3270-ccw.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/s390x/css.h" #include "hw/s390x/css-bridge.h" #include "hw/qdev-properties.h" diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c index 9d793d671e..191b29f077 100644 --- a/hw/s390x/css-bridge.c +++ b/hw/s390x/css-bridge.c @@ -20,7 +20,6 @@ #include "hw/s390x/css.h" #include "ccw-device.h" #include "hw/s390x/css-bridge.h" -#include "cpu.h" /* * Invoke device-specific unplug handler, disable the subchannel diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 4149b8e5a7..bed46f5ec3 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -15,7 +15,6 @@ #include "qemu/bitops.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "hw/s390x/ioinst.h" #include "hw/qdev-properties.h" #include "hw/s390x/css.h" diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index ff6b55e816..8c863cf386 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -18,9 +18,7 @@ #include "qapi/error.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "sysemu/tcg.h" -#include "cpu.h" #include "elf.h" #include "hw/loader.h" #include "hw/qdev-properties.h" diff --git a/hw/s390x/pv.c b/hw/s390x/pv.c index 93eccfc05d..401b63d6cb 100644 --- a/hw/s390x/pv.c +++ b/hw/s390x/pv.c @@ -13,7 +13,6 @@ #include <linux/kvm.h> -#include "cpu.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" diff --git a/hw/s390x/s390-ccw.c b/hw/s390x/s390-ccw.c index b497571863..242491a1ae 100644 --- a/hw/s390x/s390-ccw.c +++ b/hw/s390x/s390-ccw.c @@ -15,7 +15,6 @@ #include <libgen.h> #include "qapi/error.h" #include "qemu/module.h" -#include "hw/sysbus.h" #include "hw/s390x/css.h" #include "hw/s390x/css-bridge.h" #include "hw/s390x/s390-ccw.h" diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index dd138dae94..7db1c5943f 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qapi/visitor.h" -#include "cpu.h" #include "hw/s390x/s390-pci-bus.h" #include "hw/s390x/s390-pci-inst.h" #include "hw/s390x/s390-pci-vfio.h" diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 4b8326afa4..9ec277d50e 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -12,7 +12,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "exec/memop.h" #include "exec/memory-internal.h" #include "qemu/error-report.h" diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c index f89d8d9d16..f0b11a74e4 100644 --- a/hw/s390x/s390-stattrib-kvm.c +++ b/hw/s390x/s390-stattrib-kvm.c @@ -16,7 +16,6 @@ #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "exec/ram_addr.h" -#include "cpu.h" #include "kvm_s390x.h" Object *kvm_s390_stattrib_create(void) diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index 4441e1d331..9eda1c3b2a 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -11,7 +11,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "cpu.h" #include "migration/qemu-file.h" #include "migration/register.h" #include "hw/s390x/storage-attributes.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 56b52d2d30..7af27ca305 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -13,11 +13,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "hw/boards.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" -#include "hw/boards.h" #include "hw/s390x/s390-virtio-hcall.h" #include "hw/s390x/sclp.h" #include "hw/s390x/s390_flic.h" diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c index 0cf2290826..edb6e3ea01 100644 --- a/hw/s390x/sclp.c +++ b/hw/s390x/sclp.c @@ -15,8 +15,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/s390x/sclp.h" #include "hw/s390x/event-facility.h" diff --git a/hw/s390x/sclpcpu.c b/hw/s390x/sclpcpu.c index 62806d3273..f2b1a4b037 100644 --- a/hw/s390x/sclpcpu.c +++ b/hw/s390x/sclpcpu.c @@ -17,7 +17,6 @@ #include "hw/s390x/sclp.h" #include "qemu/module.h" #include "hw/s390x/event-facility.h" -#include "cpu.h" #include "sysemu/cpus.h" typedef struct ConfigMgtData { diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 8195f3546e..92b950e09a 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -17,7 +17,6 @@ #include "hw/virtio/virtio.h" #include "migration/qemu-file-types.h" #include "hw/virtio/virtio-net.h" -#include "hw/sysbus.h" #include "qemu/bitops.h" #include "qemu/error-report.h" #include "qemu/module.h" diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c index ca5c13c4a8..c210262484 100644 --- a/hw/scsi/spapr_vscsi.c +++ b/hw/scsi/spapr_vscsi.c @@ -34,7 +34,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/scsi/scsi.h" #include "migration/vmstate.h" #include "scsi/constants.h" diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c index 0b371c843d..56b8bae1c3 100644 --- a/hw/sd/cadence_sdhci.c +++ b/hw/sd/cadence_sdhci.c @@ -23,10 +23,8 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qapi/error.h" #include "migration/vmstate.h" -#include "hw/irq.h" #include "hw/sd/cadence_sdhci.h" #include "sdhci-internal.h" diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index 1f946908fe..b67def6381 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -318,7 +318,7 @@ void omap_mmc_reset(struct omap_mmc_s *host) * into any bus, and we must reset it manually. When omap_mmc is * QOMified this must move into the QOM reset function. */ - device_legacy_reset(DEVICE(host->card)); + device_cold_reset(DEVICE(host->card)); } static uint64_t omap_mmc_read(void *opaque, hwaddr offset, diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 443820901d..006010f30a 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -42,7 +42,6 @@ #include "hw/loader.h" #include "hw/usb.h" #include "hw/block/flash.h" -#include "exec/address-spaces.h" #define FLASH_BASE 0x00000000 #define FLASH_SIZE (16 * MiB) diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index f8ac3ec6e3..d53a436d8c 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -31,7 +31,6 @@ #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" -#include "cpu.h" #include "exec/exec-all.h" #define NB_DEVICES 4 diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index d9a9fcbc59..b0579aa0f1 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -31,11 +31,9 @@ #include "qapi/error.h" #include "cpu.h" #include "hw/sh4/sh.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #define BIOS_FILENAME "shix_bios.bin" diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 7e16eea9e6..7b4dec1721 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -40,7 +40,6 @@ #include "hw/loader.h" #include "elf.h" #include "trace.h" -#include "exec/address-spaces.h" #include "hw/sparc/grlib.h" #include "hw/misc/grlib_ahb_apb_pnp.h" @@ -137,7 +136,36 @@ static void main_cpu_reset(void *opaque) env->regbase[6] = s->sp; } -void leon3_irq_ack(void *irq_manager, int intno) +static void leon3_cache_control_int(CPUSPARCState *env) +{ + uint32_t state = 0; + + if (env->cache_control & CACHE_CTRL_IF) { + /* Instruction cache state */ + state = env->cache_control & CACHE_STATE_MASK; + if (state == CACHE_ENABLED) { + state = CACHE_FROZEN; + trace_int_helper_icache_freeze(); + } + + env->cache_control &= ~CACHE_STATE_MASK; + env->cache_control |= state; + } + + if (env->cache_control & CACHE_CTRL_DF) { + /* Data cache state */ + state = (env->cache_control >> 2) & CACHE_STATE_MASK; + if (state == CACHE_ENABLED) { + state = CACHE_FROZEN; + trace_int_helper_dcache_freeze(); + } + + env->cache_control &= ~(CACHE_STATE_MASK << 2); + env->cache_control |= (state << 2); + } +} + +static void leon3_irq_ack(void *irq_manager, int intno) { grlib_irqmp_ack((DeviceState *)irq_manager, intno); } @@ -181,6 +209,12 @@ static void leon3_set_pil_in(void *opaque, int n, int level) } } +static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno) +{ + leon3_irq_ack(irq_manager, intno); + leon3_cache_control_int(env); +} + static void leon3_generic_hw_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 1a00816d9a..42e139849e 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -107,6 +107,17 @@ struct sun4m_hwdef { uint8_t nvram_machine_id; }; +struct Sun4mMachineClass { + /*< private >*/ + MachineClass parent_obj; + /*< public >*/ + const struct sun4m_hwdef *hwdef; +}; +typedef struct Sun4mMachineClass Sun4mMachineClass; + +#define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") +DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) + const char *fw_cfg_arch_key_name(uint16_t key) { static const struct { @@ -159,38 +170,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr, } } -void cpu_check_irqs(CPUSPARCState *env) -{ - CPUState *cs; - - /* We should be holding the BQL before we mess with IRQs */ - g_assert(qemu_mutex_iothread_locked()); - - if (env->pil_in && (env->interrupt_index == 0 || - (env->interrupt_index & ~15) == TT_EXTINT)) { - unsigned int i; - - for (i = 15; i > 0; i--) { - if (env->pil_in & (1 << i)) { - int old_interrupt = env->interrupt_index; - - env->interrupt_index = TT_EXTINT | i; - if (old_interrupt != env->interrupt_index) { - cs = env_cpu(env); - trace_sun4m_cpu_interrupt(i); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { - cs = env_cpu(env); - trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); - env->interrupt_index = 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void cpu_kick_irq(SPARCCPU *cpu) { CPUSPARCState *env = &cpu->env; @@ -837,9 +816,9 @@ static void dummy_fdc_tc(void *opaque, int irq, int level) { } -static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, - MachineState *machine) +static void sun4m_hw_init(MachineState *machine) { + const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; DeviceState *slavio_intctl; unsigned int i; Nvram *nvram; @@ -1127,9 +1106,22 @@ enum { ss600mp_id, }; -static const struct sun4m_hwdef sun4m_hwdefs[] = { - /* SS-5 */ - { +static void sun4m_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->init = sun4m_hw_init; + mc->block_default_type = IF_SCSI; + mc->default_boot_order = "c"; + mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; +} + +static void ss5_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss5_hwdef = { .iommu_base = 0x10000000, .iommu_pad_base = 0x10004000, .iommu_pad_len = 0x0fffb000, @@ -1154,9 +1146,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = ss5_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* SS-10 */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 5"; + mc->is_default = true; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); + smc->hwdef = &ss5_hwdef; +} + +static void ss10_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss10_hwdef = { .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1170,18 +1172,28 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .dma_base = 0xef0400000ULL, .esp_base = 0xef0800000ULL, .le_base = 0xef0c00000ULL, - .apc_base = 0xefa000000ULL, // XXX should not exist + .apc_base = 0xefa000000ULL, /* XXX should not exist */ .aux1_base = 0xff1800000ULL, .aux2_base = 0xff1a01000ULL, .ecc_base = 0xf00000000ULL, - .ecc_version = 0x10000000, // version 0, implementation 1 + .ecc_version = 0x10000000, /* version 0, implementation 1 */ .nvram_machine_id = 0x72, .machine_id = ss10_id, .iommu_version = 0x03000000, .max_mem = 0xf00000000ULL, - }, - /* SS-600MP */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 10"; + mc->max_cpus = 4; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); + smc->hwdef = &ss10_hwdef; +} + +static void ss600mp_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss600mp_hwdef = { .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1193,18 +1205,28 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .dma_base = 0xef0081000ULL, .esp_base = 0xef0080000ULL, .le_base = 0xef0060000ULL, - .apc_base = 0xefa000000ULL, // XXX should not exist + .apc_base = 0xefa000000ULL, /* XXX should not exist */ .aux1_base = 0xff1800000ULL, - .aux2_base = 0xff1a01000ULL, // XXX should not exist + .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ .ecc_base = 0xf00000000ULL, - .ecc_version = 0x00000000, // version 0, implementation 0 + .ecc_version = 0x00000000, /* version 0, implementation 0 */ .nvram_machine_id = 0x71, .machine_id = ss600mp_id, .iommu_version = 0x01000000, .max_mem = 0xf00000000ULL, - }, - /* SS-20 */ - { + }; + + mc->desc = "Sun4m platform, SPARCserver 600MP"; + mc->max_cpus = 4; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); + smc->hwdef = &ss600mp_hwdef; +} + +static void ss20_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss20_hwdef = { .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1219,7 +1241,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .esp_base = 0xef0800000ULL, .le_base = 0xef0c00000ULL, .bpp_base = 0xef4800000ULL, - .apc_base = 0xefa000000ULL, // XXX should not exist + .apc_base = 0xefa000000ULL, /* XXX should not exist */ .aux1_base = 0xff1800000ULL, .aux2_base = 0xff1a01000ULL, .dbri_base = 0xee0000000ULL, @@ -1238,14 +1260,24 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { } }, .ecc_base = 0xf00000000ULL, - .ecc_version = 0x20000000, // version 0, implementation 2 + .ecc_version = 0x20000000, /* version 0, implementation 2 */ .nvram_machine_id = 0x72, .machine_id = ss20_id, .iommu_version = 0x13000000, .max_mem = 0xf00000000ULL, - }, - /* Voyager */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 20"; + mc->max_cpus = 4; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); + smc->hwdef = &ss20_hwdef; +} + +static void voyager_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef voyager_hwdef = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, .slavio_base = 0x70000000, @@ -1259,16 +1291,25 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .dma_base = 0x78400000, .esp_base = 0x78800000, .le_base = 0x78c00000, - .apc_base = 0x71300000, // pmc + .apc_base = 0x71300000, /* pmc */ .aux1_base = 0x71900000, .aux2_base = 0x71910000, .nvram_machine_id = 0x80, .machine_id = vger_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* LX */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation Voyager"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); + smc->hwdef = &voyager_hwdef; +} + +static void ss_lx_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss_lx_hwdef = { .iommu_base = 0x10000000, .iommu_pad_base = 0x10004000, .iommu_pad_len = 0x0fffb000, @@ -1290,9 +1331,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = lx_id, .iommu_version = 0x04000000, .max_mem = 0x10000000, - }, - /* SS-4 */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation LX"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); + smc->hwdef = &ss_lx_hwdef; +} + +static void ss4_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef ss4_hwdef = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, .cs_base = 0x6c000000, @@ -1314,9 +1364,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = ss4_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* SPARCClassic */ - { + }; + + mc->desc = "Sun4m platform, SPARCstation 4"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); + smc->hwdef = &ss4_hwdef; +} + +static void scls_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef scls_hwdef = { .iommu_base = 0x10000000, .tcx_base = 0x50000000, .slavio_base = 0x70000000, @@ -1337,11 +1396,20 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = scls_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, - /* SPARCbook */ - { + }; + + mc->desc = "Sun4m platform, SPARCClassic"; + mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); + smc->hwdef = &scls_hwdef; +} + +static void sbook_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); + static const struct sun4m_hwdef sbook_hwdef = { .iommu_base = 0x10000000, - .tcx_base = 0x50000000, // XXX + .tcx_base = 0x50000000, /* XXX */ .slavio_base = 0x70000000, .ms_kb_base = 0x71000000, .serial_base = 0x71100000, @@ -1360,254 +1428,67 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { .machine_id = sbook_id, .iommu_version = 0x05000000, .max_mem = 0x10000000, - }, -}; - -/* SPARCstation 5 hardware initialisation */ -static void ss5_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[0], machine); -} - -/* SPARCstation 10 hardware initialisation */ -static void ss10_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[1], machine); -} - -/* SPARCserver 600MP hardware initialisation */ -static void ss600mp_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[2], machine); -} - -/* SPARCstation 20 hardware initialisation */ -static void ss20_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[3], machine); -} - -/* SPARCstation Voyager hardware initialisation */ -static void vger_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[4], machine); -} - -/* SPARCstation LX hardware initialisation */ -static void ss_lx_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[5], machine); -} - -/* SPARCstation 4 hardware initialisation */ -static void ss4_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[6], machine); -} - -/* SPARCClassic hardware initialisation */ -static void scls_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[7], machine); -} - -/* SPARCbook hardware initialisation */ -static void sbook_init(MachineState *machine) -{ - sun4m_hw_init(&sun4m_hwdefs[8], machine); -} - -static void ss5_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCstation 5"; - mc->init = ss5_init; - mc->block_default_type = IF_SCSI; - mc->is_default = true; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo ss5_type = { - .name = MACHINE_TYPE_NAME("SS-5"), - .parent = TYPE_MACHINE, - .class_init = ss5_class_init, -}; - -static void ss10_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCstation 10"; - mc->init = ss10_init; - mc->block_default_type = IF_SCSI; - mc->max_cpus = 4; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo ss10_type = { - .name = MACHINE_TYPE_NAME("SS-10"), - .parent = TYPE_MACHINE, - .class_init = ss10_class_init, -}; - -static void ss600mp_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCserver 600MP"; - mc->init = ss600mp_init; - mc->block_default_type = IF_SCSI; - mc->max_cpus = 4; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo ss600mp_type = { - .name = MACHINE_TYPE_NAME("SS-600MP"), - .parent = TYPE_MACHINE, - .class_init = ss600mp_class_init, -}; - -static void ss20_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCstation 20"; - mc->init = ss20_init; - mc->block_default_type = IF_SCSI; - mc->max_cpus = 4; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo ss20_type = { - .name = MACHINE_TYPE_NAME("SS-20"), - .parent = TYPE_MACHINE, - .class_init = ss20_class_init, -}; - -static void voyager_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCstation Voyager"; - mc->init = vger_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo voyager_type = { - .name = MACHINE_TYPE_NAME("Voyager"), - .parent = TYPE_MACHINE, - .class_init = voyager_class_init, -}; - -static void ss_lx_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCstation LX"; - mc->init = ss_lx_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo ss_lx_type = { - .name = MACHINE_TYPE_NAME("LX"), - .parent = TYPE_MACHINE, - .class_init = ss_lx_class_init, -}; - -static void ss4_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCstation 4"; - mc->init = ss4_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo ss4_type = { - .name = MACHINE_TYPE_NAME("SS-4"), - .parent = TYPE_MACHINE, - .class_init = ss4_class_init, -}; - -static void scls_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "Sun4m platform, SPARCClassic"; - mc->init = scls_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; - mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; -} - -static const TypeInfo scls_type = { - .name = MACHINE_TYPE_NAME("SPARCClassic"), - .parent = TYPE_MACHINE, - .class_init = scls_class_init, -}; - -static void sbook_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); + }; mc->desc = "Sun4m platform, SPARCbook"; - mc->init = sbook_init; - mc->block_default_type = IF_SCSI; - mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); - mc->default_display = "tcx"; - mc->default_ram_id = "sun4m.ram"; + smc->hwdef = &sbook_hwdef; } -static const TypeInfo sbook_type = { - .name = MACHINE_TYPE_NAME("SPARCbook"), - .parent = TYPE_MACHINE, - .class_init = sbook_class_init, +static const TypeInfo sun4m_machine_types[] = { + { + .name = MACHINE_TYPE_NAME("SS-5"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss5_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-10"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss10_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-600MP"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss600mp_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-20"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss20_class_init, + }, { + .name = MACHINE_TYPE_NAME("Voyager"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = voyager_class_init, + }, { + .name = MACHINE_TYPE_NAME("LX"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss_lx_class_init, + }, { + .name = MACHINE_TYPE_NAME("SS-4"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = ss4_class_init, + }, { + .name = MACHINE_TYPE_NAME("SPARCClassic"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = scls_class_init, + }, { + .name = MACHINE_TYPE_NAME("SPARCbook"), + .parent = TYPE_SUN4M_MACHINE, + .class_init = sbook_class_init, + }, { + .name = TYPE_SUN4M_MACHINE, + .parent = TYPE_MACHINE, + .class_size = sizeof(Sun4mMachineClass), + .class_init = sun4m_machine_class_init, + .abstract = true, + } }; +DEFINE_TYPES(sun4m_machine_types) + static void sun4m_register_types(void) { type_register_static(&idreg_info); type_register_static(&afx_info); type_register_static(&prom_info); type_register_static(&ram_info); - - type_register_static(&ss5_type); - type_register_static(&ss10_type); - type_register_static(&ss600mp_type); - type_register_static(&ss20_type); - type_register_static(&voyager_type); - type_register_static(&ss_lx_type); - type_register_static(&ss4_type); - type_register_static(&scls_type); - type_register_static(&sbook_type); } type_init(sun4m_register_types) diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index 355b07ae05..d3a30a816a 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -1,8 +1,6 @@ # See docs/devel/tracing.txt for syntax documentation. # sun4m.c -sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" -sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" @@ -19,3 +17,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 # leon3.c leon3_set_irq(int intno) "Set CPU IRQ %d" leon3_reset_irq(int intno) "Reset CPU IRQ %d" +int_helper_icache_freeze(void) "Instruction cache: freeze" +int_helper_dcache_freeze(void) "Data cache: freeze" diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index a87d55f6bb..f3e42d0326 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -31,7 +31,6 @@ #include "hw/loader.h" #include "hw/sparc/sparc64.h" #include "hw/rtc/sun4v-rtc.h" -#include "exec/address-spaces.h" #include "sysemu/block-backend.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index e3f9219a10..8654e955eb 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -26,7 +26,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "hw/boards.h" -#include "hw/char/serial.h" #include "hw/sparc/sparc64.h" #include "qemu/timer.h" #include "sysemu/reset.h" @@ -35,68 +34,6 @@ #define TICK_MAX 0x7fffffffffffffffULL -void cpu_check_irqs(CPUSPARCState *env) -{ - CPUState *cs; - uint32_t pil = env->pil_in | - (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); - - /* We should be holding the BQL before we mess with IRQs */ - g_assert(qemu_mutex_iothread_locked()); - - /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ - if (env->ivec_status & 0x20) { - return; - } - cs = env_cpu(env); - /* check if TM or SM in SOFTINT are set - setting these also causes interrupt 14 */ - if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { - pil |= 1 << 14; - } - - /* The bit corresponding to psrpil is (1<< psrpil), the next bit - is (2 << psrpil). */ - if (pil < (2 << env->psrpil)) { - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); - env->interrupt_index = 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } - return; - } - - if (cpu_interrupts_enabled(env)) { - - unsigned int i; - - for (i = 15; i > env->psrpil; i--) { - if (pil & (1 << i)) { - int old_interrupt = env->interrupt_index; - int new_interrupt = TT_EXTINT | i; - - if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt - && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { - trace_sparc64_cpu_check_irqs_noset_irq(env->tl, - cpu_tsptr(env)->tt, - new_interrupt); - } else if (old_interrupt != new_interrupt) { - env->interrupt_index = new_interrupt; - trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, - new_interrupt); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - } - } - } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, - env->interrupt_index); - env->interrupt_index = 0; - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } -} - static void cpu_kick_irq(SPARCCPU *cpu) { CPUState *cs = CPU(cpu); diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index a0b29987d2..b85d14c30c 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -9,10 +9,6 @@ sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64 # sparc64.c -sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)" -sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x" -sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x" -sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x" sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d" sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d" sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled" diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 16addee4dc..331a2c5446 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -29,7 +29,6 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "qemu/units.h" #include "trace.h" @@ -127,6 +126,8 @@ /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) +#define DMA_CTRL_REQUEST (1 << 31) +#define DMA_CTRL_GRANT (1 << 30) #define DMA_CTRL_DELAY_MASK 0xf #define DMA_CTRL_DELAY_SHIFT 8 #define DMA_CTRL_FREQ_MASK 0xf @@ -178,10 +179,8 @@ * 0: 4 bytes * 0x7FFFFF: 32M bytes */ -#define DMA_DRAM_ADDR(s, val) ((s)->sdram_base | \ - ((val) & (s)->ctrl->dma_dram_mask)) -#define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \ - ((val) & (s)->ctrl->dma_flash_mask)) +#define DMA_DRAM_ADDR(s, val) ((val) & (s)->ctrl->dma_dram_mask) +#define DMA_FLASH_ADDR(s, val) ((val) & (s)->ctrl->dma_flash_mask) #define DMA_LENGTH(val) ((val) & 0x01FFFFFC) /* Flash opcodes. */ @@ -230,6 +229,7 @@ static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, const AspeedSegments *seg); static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, AspeedSegments *seg); +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t value); /* * AST2600 definitions @@ -259,6 +259,15 @@ static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, const AspeedSegments *seg); static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, AspeedSegments *seg); +static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t value); + +#define ASPEED_SMC_FEATURE_DMA 0x1 +#define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 + +static inline bool aspeed_smc_has_dma(const AspeedSMCState *s) +{ + return !!(s->ctrl->features & ASPEED_SMC_FEATURE_DMA); +} static const AspeedSMCController controllers[] = { { @@ -273,10 +282,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_legacy, .flash_window_base = ASPEED_SOC_SMC_FLASH_BASE, .flash_window_size = 0x6000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_SMC_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.fmc-ast2400", .r_conf = R_CONF, @@ -289,12 +299,13 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_fmc, .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x1FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.spi1-ast2400", .r_conf = R_SPI_CONF, @@ -307,10 +318,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_spi, .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_SPI_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.fmc-ast2500", .r_conf = R_CONF, @@ -323,12 +335,13 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2500_fmc, .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.spi1-ast2500", .r_conf = R_CONF, @@ -341,10 +354,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2500_spi1, .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE, .flash_window_size = 0x8000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.spi2-ast2500", .r_conf = R_CONF, @@ -357,10 +371,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2500_spi2, .flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE, .flash_window_size = 0x8000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.fmc-ast2600", .r_conf = R_CONF, @@ -373,12 +388,13 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2600_fmc, .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_2600_smc_segment_to_reg, .reg_to_segment = aspeed_2600_smc_reg_to_segment, + .dma_ctrl = aspeed_2600_smc_dma_ctrl, }, { .name = "aspeed.spi1-ast2600", .r_conf = R_CONF, @@ -391,12 +407,14 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2600_spi1, .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_GRANT, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_2600_smc_segment_to_reg, .reg_to_segment = aspeed_2600_smc_reg_to_segment, + .dma_ctrl = aspeed_2600_smc_dma_ctrl, }, { .name = "aspeed.spi2-ast2600", .r_conf = R_CONF, @@ -409,12 +427,14 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2600_spi2, .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_GRANT, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_2600_smc_segment_to_reg, .reg_to_segment = aspeed_2600_smc_reg_to_segment, + .dma_ctrl = aspeed_2600_smc_dma_ctrl, }, }; @@ -999,11 +1019,11 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == R_CE_CMD_CTRL || addr == R_INTR_CTRL || addr == R_DUMMY_DATA || - (s->ctrl->has_dma && addr == R_DMA_CTRL) || - (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) || - (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) || - (s->ctrl->has_dma && addr == R_DMA_LEN) || - (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) || + (aspeed_smc_has_dma(s) && addr == R_DMA_CTRL) || + (aspeed_smc_has_dma(s) && addr == R_DMA_FLASH_ADDR) || + (aspeed_smc_has_dma(s) && addr == R_DMA_DRAM_ADDR) || + (aspeed_smc_has_dma(s) && addr == R_DMA_LEN) || + (aspeed_smc_has_dma(s) && addr == R_DMA_CHECKSUM) || (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) || (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_peripherals)) { @@ -1236,7 +1256,7 @@ static void aspeed_smc_dma_done(AspeedSMCState *s) } } -static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl) +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) { if (!(dma_ctrl & DMA_CTRL_ENABLE)) { s->regs[R_DMA_CTRL] = dma_ctrl; @@ -1261,6 +1281,46 @@ static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl) aspeed_smc_dma_done(s); } +static inline bool aspeed_smc_dma_granted(AspeedSMCState *s) +{ + if (!(s->ctrl->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { + return true; + } + + if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n", __func__); + return false; + } + + return true; +} + +static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) +{ + /* Preserve DMA bits */ + dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); + + if (dma_ctrl == 0xAEED0000) { + /* automatically grant request */ + s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); + return; + } + + /* clear request */ + if (dma_ctrl == 0xDEEA0000) { + s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); + return; + } + + if (!aspeed_smc_dma_granted(s)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n", __func__); + return; + } + + aspeed_smc_dma_ctrl(s, dma_ctrl); + s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); +} + static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -1292,13 +1352,16 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, s->regs[addr] = value & 0xff; } else if (addr == R_INTR_CTRL) { s->regs[addr] = value; - } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) { - aspeed_smc_dma_ctrl(s, value); - } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) { + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_CTRL) { + s->ctrl->dma_ctrl(s, value); + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_DRAM_ADDR && + aspeed_smc_dma_granted(s)) { s->regs[addr] = DMA_DRAM_ADDR(s, value); - } else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) { + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_FLASH_ADDR && + aspeed_smc_dma_granted(s)) { s->regs[addr] = DMA_FLASH_ADDR(s, value); - } else if (s->ctrl->has_dma && addr == R_DMA_LEN) { + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_LEN && + aspeed_smc_dma_granted(s)) { s->regs[addr] = DMA_LENGTH(value); } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", @@ -1386,7 +1449,9 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->mmio_flash, OBJECT(s), &aspeed_smc_flash_default_ops, s, name, s->ctrl->flash_window_size); - sysbus_init_mmio(sbd, &s->mmio_flash); + memory_region_init_alias(&s->mmio_flash_alias, OBJECT(s), name, + &s->mmio_flash, 0, s->ctrl->flash_window_size); + sysbus_init_mmio(sbd, &s->mmio_flash_alias); s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_peripherals); @@ -1412,7 +1477,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) } /* DMA support */ - if (s->ctrl->has_dma) { + if (aspeed_smc_has_dma(s)) { aspeed_smc_dma_setup(s, errp); } } @@ -1432,7 +1497,6 @@ static const VMStateDescription vmstate_aspeed_smc = { static Property aspeed_smc_properties[] = { DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), - DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c index 0c9ebca3c8..03540cf5ca 100644 --- a/hw/ssi/sifive_spi.c +++ b/hw/ssi/sifive_spi.c @@ -24,7 +24,6 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "hw/ssi/ssi.h" -#include "sysemu/sysemu.h" #include "qemu/fifo8.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 49ff275593..b2819a7ff0 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/fifo8.h" diff --git a/hw/timer/mips_gictimer.c b/hw/timer/mips_gictimer.c index bc44cd934e..2b0696d4ac 100644 --- a/hw/timer/mips_gictimer.c +++ b/hw/timer/mips_gictimer.c @@ -7,7 +7,6 @@ */ #include "qemu/osdep.h" -#include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/timer/mips_gictimer.h" diff --git a/hw/timer/sse-counter.c b/hw/timer/sse-counter.c index 0384051f15..16c0e8ad15 100644 --- a/hw/timer/sse-counter.c +++ b/hw/timer/sse-counter.c @@ -33,7 +33,6 @@ #include "trace.h" #include "hw/timer/sse-counter.h" #include "hw/sysbus.h" -#include "hw/irq.h" #include "hw/registerfields.h" #include "hw/clock.h" #include "hw/qdev-clock.h" diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index aa9c00aad3..58ebd1469c 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -18,7 +18,6 @@ #include "qemu/module.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "hw/pci/pci_ids.h" #include "hw/acpi/tpm.h" diff --git a/hw/tricore/tc27x_soc.c b/hw/tricore/tc27x_soc.c index 8af079e6b2..ecd92717b5 100644 --- a/hw/tricore/tc27x_soc.c +++ b/hw/tricore/tc27x_soc.c @@ -21,13 +21,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "hw/boards.h" #include "hw/loader.h" #include "qemu/units.h" #include "hw/misc/unimp.h" -#include "exec/address-spaces.h" -#include "qemu/log.h" -#include "cpu.h" #include "hw/tricore/tc27x_soc.h" #include "hw/tricore/triboard.h" diff --git a/hw/tricore/triboard.c b/hw/tricore/triboard.c index 16e2fd7e27..4dba0259cd 100644 --- a/hw/tricore/triboard.c +++ b/hw/tricore/triboard.c @@ -22,11 +22,8 @@ #include "qemu/units.h" #include "qapi/error.h" #include "hw/qdev-properties.h" -#include "cpu.h" #include "net/net.h" -#include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "elf.h" #include "hw/tricore/tricore.h" #include "qemu/error-report.h" diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c index 12ea1490fd..51658d9e37 100644 --- a/hw/tricore/tricore_testboard.c +++ b/hw/tricore/tricore_testboard.c @@ -25,7 +25,6 @@ #include "net/net.h" #include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "elf.h" #include "hw/tricore/tricore.h" #include "qemu/error-report.h" diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index c1a90fcc7a..7212d0d7fb 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -374,7 +374,7 @@ static void passthru_realize(CCIDCardState *base, Error **errp) card->atr_length = sizeof(DEFAULT_ATR); } -static VMStateDescription passthru_vmstate = { +static const VMStateDescription passthru_vmstate = { .name = "ccid-card-passthru", .version_id = 1, .minimum_version_id = 1, diff --git a/hw/usb/chipidea.c b/hw/usb/chipidea.c index 3dcd22ccba..b1c85404d6 100644 --- a/hw/usb/chipidea.c +++ b/hw/usb/chipidea.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "hw/usb/hcd-ehci.h" #include "hw/usb/chipidea.h" -#include "qemu/log.h" #include "qemu/module.h" enum { diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c index bc3d94092a..f7043075be 100644 --- a/hw/usb/dev-smartcard-reader.c +++ b/hw/usb/dev-smartcard-reader.c @@ -1365,7 +1365,7 @@ static int ccid_pre_save(void *opaque) return 0; } -static VMStateDescription bulk_in_vmstate = { +static const VMStateDescription bulk_in_vmstate = { .name = "CCID BulkIn state", .version_id = 1, .minimum_version_id = 1, @@ -1377,7 +1377,7 @@ static VMStateDescription bulk_in_vmstate = { } }; -static VMStateDescription answer_vmstate = { +static const VMStateDescription answer_vmstate = { .name = "CCID Answer state", .version_id = 1, .minimum_version_id = 1, @@ -1388,7 +1388,7 @@ static VMStateDescription answer_vmstate = { } }; -static VMStateDescription usb_device_vmstate = { +static const VMStateDescription usb_device_vmstate = { .name = "usb_device", .version_id = 1, .minimum_version_id = 1, @@ -1400,7 +1400,7 @@ static VMStateDescription usb_device_vmstate = { } }; -static VMStateDescription ccid_vmstate = { +static const VMStateDescription ccid_vmstate = { .name = "usb-ccid", .version_id = 1, .minimum_version_id = 1, diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c index d547d0538d..279263489e 100644 --- a/hw/usb/hcd-dwc3.c +++ b/hw/usb/hcd-dwc3.c @@ -31,7 +31,6 @@ #include "hw/sysbus.h" #include "hw/register.h" #include "qemu/bitops.h" -#include "qemu/log.h" #include "qom/object.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c index e705a03a1f..5d7a549e34 100644 --- a/hw/usb/imx-usb-phy.c +++ b/hw/usb/imx-usb-phy.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "hw/usb/imx-usb-phy.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" static const VMStateDescription vmstate_imx_usbphy = { diff --git a/hw/usb/xen-usb.c b/hw/usb/xen-usb.c index 4d266d7bb4..0f7369e7ed 100644 --- a/hw/usb/xen-usb.c +++ b/hw/usb/xen-usb.c @@ -26,7 +26,6 @@ #include "qemu/config-file.h" #include "qemu/main-loop.h" #include "qemu/option.h" -#include "hw/sysbus.h" #include "hw/usb.h" #include "hw/xen/xen-legacy-backend.h" #include "monitor/qdev.h" diff --git a/hw/usb/xlnx-usb-subsystem.c b/hw/usb/xlnx-usb-subsystem.c index 568257370c..d8deeb6ced 100644 --- a/hw/usb/xlnx-usb-subsystem.c +++ b/hw/usb/xlnx-usb-subsystem.c @@ -24,10 +24,8 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" -#include "hw/irq.h" #include "hw/register.h" #include "qemu/bitops.h" -#include "qemu/log.h" #include "qom/object.h" #include "qapi/error.h" #include "hw/qdev-properties.h" diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-ctrl-regs.c index 9eaa59ebb8..1c094aa1a6 100644 --- a/hw/usb/xlnx-versal-usb2-ctrl-regs.c +++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c @@ -32,7 +32,6 @@ #include "hw/irq.h" #include "hw/register.h" #include "qemu/bitops.h" -#include "qemu/log.h" #include "qom/object.h" #include "migration/vmstate.h" #include "hw/usb/xlnx-versal-usb2-ctrl-regs.h" diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c index 9571c2f91f..4b32aca1a0 100644 --- a/hw/vfio/ap.c +++ b/hw/vfio/ap.c @@ -14,7 +14,6 @@ #include <linux/vfio.h> #include <sys/ioctl.h> #include "qapi/error.h" -#include "hw/sysbus.h" #include "hw/vfio/vfio.h" #include "hw/vfio/vfio-common.h" #include "hw/s390x/ap-device.h" @@ -22,7 +21,6 @@ #include "qemu/module.h" #include "qemu/option.h" #include "qemu/config-file.h" -#include "cpu.h" #include "kvm_s390x.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c index b2df708e4b..e752c845e9 100644 --- a/hw/vfio/ccw.c +++ b/hw/vfio/ccw.c @@ -20,7 +20,6 @@ #include <sys/ioctl.h> #include "qapi/error.h" -#include "hw/sysbus.h" #include "hw/vfio/vfio.h" #include "hw/vfio/vfio-common.h" #include "hw/s390x/s390-ccw.h" diff --git a/hw/vfio/display.c b/hw/vfio/display.c index f04473e3ce..89bc90508f 100644 --- a/hw/vfio/display.c +++ b/hw/vfio/display.c @@ -14,7 +14,6 @@ #include <linux/vfio.h> #include <sys/ioctl.h> -#include "sysemu/sysemu.h" #include "hw/display/edid.h" #include "ui/console.h" #include "qapi/error.h" diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index 384576cfc0..201642d75e 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -15,7 +15,6 @@ #include "sysemu/runstate.h" #include "hw/vfio/vfio-common.h" -#include "cpu.h" #include "migration/migration.h" #include "migration/vmstate.h" #include "migration/qemu-file.h" diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index b90cf3d37c..e21a6ede11 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -22,7 +22,6 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include <sys/ioctl.h> -#include "hw/hw.h" #include "hw/nvram/fw_cfg.h" #include "hw/qdev-properties.h" #include "pci.h" diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 5c65aa0a98..ab4077aad2 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -37,7 +37,6 @@ #include "qemu/units.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "pci.h" #include "trace.h" #include "qapi/error.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index 2900bd1941..ea3f70bd2f 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -9,7 +9,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include <sys/ioctl.h> #include <linux/vfio.h> diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index e2163a0d63..7b7bde7657 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -21,7 +21,6 @@ #include "qemu/error-report.h" #include "qemu/memfd.h" #include "standard-headers/linux/vhost_types.h" -#include "exec/address-spaces.h" #include "hw/virtio/virtio-bus.h" #include "hw/virtio/virtio-access.h" #include "migration/blocker.h" diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 07f4e60b30..9e13cb9e3a 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -15,7 +15,6 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "qemu/log.h" #include "qemu/main-loop.h" diff --git a/hw/xen/xen-bus-helper.c b/hw/xen/xen-bus-helper.c index b459bb9396..5a1e12b374 100644 --- a/hw/xen/xen-bus-helper.c +++ b/hw/xen/xen-bus-helper.c @@ -6,7 +6,6 @@ */ #include "qemu/osdep.h" -#include "hw/sysbus.h" #include "hw/xen/xen.h" #include "hw/xen/xen-bus.h" #include "hw/xen/xen-bus-helper.h" diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c index b61a4855b7..dd8ae1452d 100644 --- a/hw/xen/xen-legacy-backend.c +++ b/hw/xen/xen-legacy-backend.c @@ -27,7 +27,6 @@ #include "hw/sysbus.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "qemu/log.h" #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/xen/xen-legacy-backend.h" diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index a513fdd62d..232482d65f 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -64,7 +64,6 @@ #include "hw/xen/xen-legacy-backend.h" #include "xen_pt.h" #include "qemu/range.h" -#include "exec/address-spaces.h" static bool has_igd_gfx_passthru; diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index cbac50db2d..2028fe793d 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -27,14 +27,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "xtensa_memory.h" #include "xtensa_sim.h" diff --git a/hw/xtensa/virt.c b/hw/xtensa/virt.c index e47e1de676..a18e3fc910 100644 --- a/hw/xtensa/virt.c +++ b/hw/xtensa/virt.c @@ -27,16 +27,13 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "sysemu/reset.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/pci-host/gpex.h" #include "net/net.h" #include "elf.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "xtensa_memory.h" #include "xtensa_sim.h" diff --git a/hw/xtensa/xtensa_memory.c b/hw/xtensa/xtensa_memory.c index 1c5f62b014..2c1095f017 100644 --- a/hw/xtensa/xtensa_memory.c +++ b/hw/xtensa/xtensa_memory.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "exec/memory.h" #include "qemu/error-report.h" #include "xtensa_memory.h" diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 7be53f1895..17f087b395 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -35,7 +35,6 @@ #include "hw/qdev-properties.h" #include "elf.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "hw/char/serial.h" #include "net/net.h" #include "hw/sysbus.h" |