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-rw-r--r--hw/intc/sifive_plic.c26
-rw-r--r--hw/misc/Kconfig9
-rw-r--r--hw/misc/mchp_pfsoc_dmc.c216
-rw-r--r--hw/misc/mchp_pfsoc_ioscb.c242
-rw-r--r--hw/misc/mchp_pfsoc_sysreg.c99
-rw-r--r--hw/misc/meson.build3
-rw-r--r--hw/riscv/Kconfig3
-rw-r--r--hw/riscv/microchip_pfsoc.c125
-rw-r--r--hw/riscv/sifive_u.c28
-rw-r--r--hw/riscv/virt.c27
10 files changed, 747 insertions, 31 deletions
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f42fd695d8..97a1a27a9a 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -30,6 +30,7 @@
#include "hw/intc/sifive_plic.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
#define RISCV_DEBUG_PLIC 0
@@ -448,11 +449,12 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
TYPE_SIFIVE_PLIC, plic->aperture_size);
parse_hart_config(plic);
plic->bitfield_words = (plic->num_sources + 31) >> 5;
+ plic->num_enables = plic->bitfield_words * plic->num_addrs;
plic->source_priority = g_new0(uint32_t, plic->num_sources);
plic->target_priority = g_new(uint32_t, plic->num_addrs);
plic->pending = g_new0(uint32_t, plic->bitfield_words);
plic->claimed = g_new0(uint32_t, plic->bitfield_words);
- plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
+ plic->enable = g_new0(uint32_t, plic->num_enables);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
@@ -472,12 +474,34 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
msi_nonbroken = true;
}
+static const VMStateDescription vmstate_sifive_plic = {
+ .name = "riscv_sifive_plic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
+ num_sources, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
+ num_addrs, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
+ dc->vmsd = &vmstate_sifive_plic;
}
static const TypeInfo sifive_plic_info = {
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 877ecff447..dc44dc14f6 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -139,6 +139,15 @@ config MAC_VIA
config AVR_POWER
bool
+config MCHP_PFSOC_DMC
+ bool
+
+config MCHP_PFSOC_IOSCB
+ bool
+
+config MCHP_PFSOC_SYSREG
+ bool
+
config SIFIVE_TEST
bool
diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c
new file mode 100644
index 0000000000..15cf3d7725
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_dmc.c
@@ -0,0 +1,216 @@
+/*
+ * Microchip PolarFire SoC DDR Memory Controller module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_dmc.h"
+
+/* DDR SGMII PHY module */
+
+#define SGMII_PHY_IOC_REG1 0x208
+#define SGMII_PHY_TRAINING_STATUS 0x814
+#define SGMII_PHY_DQ_DQS_ERR_DONE 0x834
+#define SGMII_PHY_DQDQS_STATUS1 0x84c
+#define SGMII_PHY_PVT_STAT 0xc20
+
+static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+ static int training_status_bit;
+
+ switch (offset) {
+ case SGMII_PHY_IOC_REG1:
+ /* See ddr_pvt_calibration() in HSS */
+ val = BIT(4) | BIT(2);
+ break;
+ case SGMII_PHY_TRAINING_STATUS:
+ /*
+ * The codes logic emulates the training status change from
+ * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS.
+ *
+ * See ddr_setup() in mss_ddr.c in the HSS source codes.
+ */
+ val = 1 << training_status_bit;
+ training_status_bit = (training_status_bit + 1) % 5;
+ break;
+ case SGMII_PHY_DQ_DQS_ERR_DONE:
+ /*
+ * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
+ * check that DQ/DQS training passed without error.
+ */
+ val = 8;
+ break;
+ case SGMII_PHY_DQDQS_STATUS1:
+ /*
+ * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
+ * check that DQ/DQS calculated window is above 5 taps.
+ */
+ val = 0xff;
+ break;
+ case SGMII_PHY_PVT_STAT:
+ /* See sgmii_channel_setup() in HSS */
+ val = BIT(14) | BIT(6);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = {
+ .read = mchp_pfsoc_ddr_sgmii_phy_read,
+ .write = mchp_pfsoc_ddr_sgmii_phy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev);
+
+ memory_region_init_io(&s->sgmii_phy, OBJECT(dev),
+ &mchp_pfsoc_ddr_sgmii_phy_ops, s,
+ "mchp.pfsoc.ddr_sgmii_phy",
+ MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy);
+}
+
+static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module";
+ dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = {
+ .name = TYPE_MCHP_PFSOC_DDR_SGMII_PHY,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState),
+ .class_init = mchp_pfsoc_ddr_sgmii_phy_class_init,
+};
+
+static void mchp_pfsoc_ddr_sgmii_phy_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info);
+}
+
+type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)
+
+/* DDR CFG module */
+
+#define CFG_MT_DONE_ACK 0x4428
+#define CFG_STAT_DFI_INIT_COMPLETE 0x10034
+#define CFG_STAT_DFI_TRAINING_COMPLETE 0x10038
+
+static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case CFG_MT_DONE_ACK:
+ /* memory test in MTC_test() */
+ val = BIT(0);
+ break;
+ case CFG_STAT_DFI_INIT_COMPLETE:
+ /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */
+ val = BIT(0);
+ break;
+ case CFG_STAT_DFI_TRAINING_COMPLETE:
+ /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */
+ val = BIT(0);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = {
+ .read = mchp_pfsoc_ddr_cfg_read,
+ .write = mchp_pfsoc_ddr_cfg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev);
+
+ memory_region_init_io(&s->cfg, OBJECT(dev),
+ &mchp_pfsoc_ddr_cfg_ops, s,
+ "mchp.pfsoc.ddr_cfg",
+ MCHP_PFSOC_DDR_CFG_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg);
+}
+
+static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC DDR CFG module";
+ dc->realize = mchp_pfsoc_ddr_cfg_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ddr_cfg_info = {
+ .name = TYPE_MCHP_PFSOC_DDR_CFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCDdrCfgState),
+ .class_init = mchp_pfsoc_ddr_cfg_class_init,
+};
+
+static void mchp_pfsoc_ddr_cfg_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_ddr_cfg_info);
+}
+
+type_init(mchp_pfsoc_ddr_cfg_register_types)
diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
new file mode 100644
index 0000000000..8b0d1cacd7
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_ioscb.c
@@ -0,0 +1,242 @@
+/*
+ * Microchip PolarFire SoC IOSCB module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_ioscb.h"
+
+/*
+ * The whole IOSCB module registers map into the system address at 0x3000_0000,
+ * named as "System Port 0 (AXI-D0)".
+ */
+#define IOSCB_WHOLE_REG_SIZE 0x10000000
+#define IOSCB_SUBMOD_REG_SIZE 0x1000
+
+/*
+ * There are many sub-modules in the IOSCB module.
+ * See Microchip PolarFire SoC documentation (Register_Map.zip),
+ * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
+ *
+ * The following are sub-modules offsets that are of concern.
+ */
+#define IOSCB_LANE01_BASE 0x06500000
+#define IOSCB_LANE23_BASE 0x06510000
+#define IOSCB_CTRL_BASE 0x07020000
+#define IOSCB_CFG_BASE 0x07080000
+#define IOSCB_PLL_MSS_BASE 0x0E001000
+#define IOSCB_CFM_MSS_BASE 0x0E002000
+#define IOSCB_PLL_DDR_BASE 0x0E010000
+#define IOSCB_BC_DDR_BASE 0x0E020000
+#define IOSCB_IO_CALIB_DDR_BASE 0x0E040000
+#define IOSCB_PLL_SGMII_BASE 0x0E080000
+#define IOSCB_DLL_SGMII_BASE 0x0E100000
+#define IOSCB_CFM_SGMII_BASE 0x0E200000
+#define IOSCB_BC_SGMII_BASE 0x0E400000
+#define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000
+
+static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+
+ return 0;
+}
+
+static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
+ .read = mchp_pfsoc_dummy_read,
+ .write = mchp_pfsoc_dummy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* All PLL modules in IOSCB have the same register layout */
+
+#define PLL_CTRL 0x04
+
+static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case PLL_CTRL:
+ /* PLL is locked */
+ val = BIT(25);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static const MemoryRegionOps mchp_pfsoc_pll_ops = {
+ .read = mchp_pfsoc_pll_read,
+ .write = mchp_pfsoc_dummy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* IO_CALIB_DDR submodule */
+
+#define IO_CALIB_DDR_IOC_REG1 0x08
+
+static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case IO_CALIB_DDR_IOC_REG1:
+ /* calibration completed */
+ val = BIT(2);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
+ .read = mchp_pfsoc_io_calib_ddr_read,
+ .write = mchp_pfsoc_dummy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init(&s->container, OBJECT(s),
+ "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
+ sysbus_init_mmio(sbd, &s->container);
+
+ /* add subregions for all sub-modules in IOSCB */
+
+ memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
+
+ memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
+
+ memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
+
+ memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
+
+ memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+ "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
+
+ memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
+
+ memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+ "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
+
+ memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
+
+ memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
+ &mchp_pfsoc_io_calib_ddr_ops, s,
+ "mchp.pfsoc.ioscb.io_calib_ddr",
+ IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
+ &s->io_calib_ddr);
+
+ memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+ "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
+ &s->pll_sgmii);
+
+ memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
+ &s->dll_sgmii);
+
+ memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
+ &s->cfm_sgmii);
+
+ memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
+ &s->bc_sgmii);
+
+ memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
+ s, "mchp.pfsoc.ioscb.io_calib_sgmii",
+ IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
+ &s->io_calib_sgmii);
+}
+
+static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC IOSCB modules";
+ dc->realize = mchp_pfsoc_ioscb_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ioscb_info = {
+ .name = TYPE_MCHP_PFSOC_IOSCB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCIoscbState),
+ .class_init = mchp_pfsoc_ioscb_class_init,
+};
+
+static void mchp_pfsoc_ioscb_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_ioscb_info);
+}
+
+type_init(mchp_pfsoc_ioscb_register_types)
diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
new file mode 100644
index 0000000000..248a313345
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_sysreg.c
@@ -0,0 +1,99 @@
+/*
+ * Microchip PolarFire SoC SYSREG module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_sysreg.h"
+
+#define ENVM_CR 0xb8
+
+static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case ENVM_CR:
+ /* Indicate the eNVM is running at the configured divider rate */
+ val = BIT(6);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
+ .read = mchp_pfsoc_sysreg_read,
+ .write = mchp_pfsoc_sysreg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
+
+ memory_region_init_io(&s->sysreg, OBJECT(dev),
+ &mchp_pfsoc_sysreg_ops, s,
+ "mchp.pfsoc.sysreg",
+ MCHP_PFSOC_SYSREG_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
+}
+
+static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC SYSREG module";
+ dc->realize = mchp_pfsoc_sysreg_realize;
+}
+
+static const TypeInfo mchp_pfsoc_sysreg_info = {
+ .name = TYPE_MCHP_PFSOC_SYSREG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCSysregState),
+ .class_init = mchp_pfsoc_sysreg_class_init,
+};
+
+static void mchp_pfsoc_sysreg_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_sysreg_info);
+}
+
+type_init(mchp_pfsoc_sysreg_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 4a06cbabef..1cd48e8a0f 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -23,6 +23,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 2df978fe8d..facb0cbacc 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,7 +4,10 @@ config IBEX
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
+ select MCHP_PFSOC_DMC
+ select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
+ select MCHP_PFSOC_SYSREG
select MSI_NONBROKEN
select SIFIVE_CLINT
select SIFIVE_PDMA
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4627179cd3..37ac46a1af 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -15,6 +15,8 @@
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
* 5) SiFive Platform DMA (Direct Memory Access Controller)
* 6) GEM (Gigabit Ethernet MAC Controller)
+ * 7) DMC (DDR Memory Controller)
+ * 8) IOSCB modules
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -66,11 +68,30 @@
/* GEM version */
#define GEM_REVISION 0x0107010c
+/*
+ * The complete description of the whole PolarFire SoC memory map is scattered
+ * in different documents. There are several places to look at for memory maps:
+ *
+ * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
+ * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
+ * https://www.microsemi.com/document-portal/doc_download/
+ * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
+ * describes the whole picture of the PolarFire SoC memory map.
+ *
+ * 2 A zip file for PolarFire soC memory map, which can be downloaded from
+ * https://www.microsemi.com/document-portal/doc_download/
+ * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
+ * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
+ * describes the complete integrated peripherals memory map
+ * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
+ * describes the complete IOSCB modules memory maps
+ */
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} microchip_pfsoc_memmap[] = {
- [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
+ [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
+ [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
[MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
[MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
@@ -85,11 +106,14 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
+ [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
@@ -97,8 +121,11 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
- [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
- [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
+ [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
+ [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
+ [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
+ [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
+ [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
};
static void microchip_pfsoc_soc_instance_init(Object *obj)
@@ -131,11 +158,21 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "sysreg", &s->sysreg,
+ TYPE_MCHP_PFSOC_SYSREG);
+
+ object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
+ TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
+ object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
+ TYPE_MCHP_PFSOC_DDR_CFG);
+
object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
object_initialize_child(obj, "sd-controller", &s->sdhci,
TYPE_CADENCE_SDHCI);
+
+ object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
}
static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -144,6 +181,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
@@ -163,6 +201,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
+ /* Reserved Memory at address 0 */
+ memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem",
+ memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_RSVD0].base,
+ rsvd0_mem);
+
/* E51 DTIM */
memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
@@ -251,15 +296,25 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
}
/* SYSREG */
- create_unimplemented_device("microchip.pfsoc.sysreg",
- memmap[MICROCHIP_PFSOC_SYSREG].base,
- memmap[MICROCHIP_PFSOC_SYSREG].size);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
+ memmap[MICROCHIP_PFSOC_SYSREG].base);
/* MPUCFG */
create_unimplemented_device("microchip.pfsoc.mpucfg",
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* DDR SGMII PHY */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
+ memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
+
+ /* DDR CFG */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
+ memmap[MICROCHIP_PFSOC_DDR_CFG].base);
+
/* SDHCI */
sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
@@ -289,6 +344,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
serial_hd(4));
+ /* I2C1 */
+ create_unimplemented_device("microchip.pfsoc.i2c1",
+ memmap[MICROCHIP_PFSOC_I2C1].base,
+ memmap[MICROCHIP_PFSOC_I2C1].size);
+
/* GEMs */
nd = &nd_table[0];
@@ -337,10 +397,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
envm_data);
- /* IOSCBCFG */
- create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
- memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
- memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+ /* IOSCB */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+ memmap[MICROCHIP_PFSOC_IOSCB].base);
}
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
@@ -373,7 +433,11 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_low = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_high = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
+ uint64_t mem_high_size;
DriveInfo *dinfo = drive_get_next(IF_SD);
/* Sanity check on RAM size */
@@ -390,10 +454,33 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* Register RAM */
- memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
- machine->ram_size, &error_fatal);
+ memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
+ memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+ &error_fatal);
+ memory_region_init_alias(mem_low_alias, NULL,
+ "microchip.icicle.kit.ram_low.alias",
+ mem_low, 0,
+ memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+ mem_low);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
+ mem_low_alias);
+
+ mem_high_size = machine->ram_size - 1 * GiB;
+
+ memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
+ mem_high_size, &error_fatal);
+ memory_region_init_alias(mem_high_alias, NULL,
+ "microchip.icicle.kit.ram_high.alias",
+ mem_high, 0, mem_high_size);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM_HI].base,
+ mem_high);
memory_region_add_subregion(system_memory,
- memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
+ memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
+ mem_high_alias);
/* Load the firmware */
riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
@@ -419,7 +506,15 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpus = mc->min_cpus;
- mc->default_ram_size = 1 * GiB;
+
+ /*
+ * Map 513 MiB high memory, the mimimum required high memory size, because
+ * HSS will do memory test against the high memory address range regardless
+ * of physical memory installed.
+ *
+ * See memory_tests() in mss_ddr.c in the HSS source code.
+ */
+ mc->default_ram_size = 1537 * MiB;
}
static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b2472c6627..2f19a9cda2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -100,14 +100,25 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
int cpu;
uint32_t *cells;
char *nodename;
+ const char *dtb_filename;
char ethclk_names[] = "pclk\0hclk";
uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
- fdt = s->fdt = create_device_tree(&s->fdt_size);
- if (!fdt) {
- error_report("create_device_tree() failed");
- exit(1);
+ dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
+ if (dtb_filename) {
+ fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
+ if (!fdt) {
+ error_report("load_device_tree() failed");
+ exit(1);
+ }
+ goto update_bootargs;
+ } else {
+ fdt = s->fdt = create_device_tree(&s->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
}
qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
@@ -390,13 +401,14 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- if (cmdline) {
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
-
qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
g_free(nodename);
+
+update_bootargs:
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
}
static void sifive_u_machine_reset(void *opaque, int n, int level)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6bfd10dfc7..25cea7aa67 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -181,6 +181,7 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
{
void *fdt;
int i, cpu, socket;
+ const char *dtb_filename;
MachineState *mc = MACHINE(s);
uint64_t addr, size;
uint32_t *clint_cells, *plic_cells;
@@ -194,10 +195,20 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
- fdt = s->fdt = create_device_tree(&s->fdt_size);
- if (!fdt) {
- error_report("create_device_tree() failed");
- exit(1);
+ dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
+ if (dtb_filename) {
+ fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size);
+ if (!fdt) {
+ error_report("load_device_tree() failed");
+ exit(1);
+ }
+ goto update_bootargs;
+ } else {
+ fdt = s->fdt = create_device_tree(&s->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
}
qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
@@ -418,9 +429,6 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
- if (cmdline) {
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
g_free(name);
name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
@@ -441,6 +449,11 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
2, flashbase + flashsize, 2, flashsize);
qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4);
g_free(name);
+
+update_bootargs:
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-02 12:46:11 +0000