diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/apic.c | 33 | ||||
| -rw-r--r-- | hw/pc.c | 7 |
2 files changed, 37 insertions, 3 deletions
@@ -484,6 +484,25 @@ int apic_get_interrupt(CPUState *env) return intno; } +int apic_accept_pic_intr(CPUState *env) +{ + APICState *s = env->apic_state; + uint32_t lvt0; + + if (!s) + return -1; + + lvt0 = s->lvt[APIC_LVT_LINT0]; + + if (s->id == 0 && + ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || + ((lvt0 & APIC_LVT_MASKED) == 0 && + ((lvt0 >> 8) & 0x7) == APIC_DM_EXTINT))) + return 1; + + return 0; +} + static uint32_t apic_get_current_count(APICState *s) { int64_t d; @@ -790,6 +809,13 @@ static void apic_reset(void *opaque) { APICState *s = opaque; apic_init_ipi(s); + + /* + * LINT0 delivery mode is set to ExtInt at initialization time + * typically by BIOS, so PIC interrupt can be delivered to the + * processor when local APIC is enabled. + */ + s->lvt[APIC_LVT_LINT0] = 0x700; } static CPUReadMemoryFunc *apic_mem_read[3] = { @@ -821,6 +847,13 @@ int apic_init(CPUState *env) s->apicbase = 0xfee00000 | (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE; + /* + * LINT0 delivery mode is set to ExtInt at initialization time + * typically by BIOS, so PIC interrupt can be delivered to the + * processor when local APIC is enabled. + */ + s->lvt[APIC_LVT_LINT0] = 0x700; + /* XXX: mapping more APICs at the same memory location */ if (apic_io_memory == 0) { /* NOTE: the APIC is directly connected to the CPU - it is not @@ -93,6 +93,9 @@ int cpu_get_pic_interrupt(CPUState *env) return intno; } /* read the irq from the PIC */ + if (!apic_accept_pic_intr(env)) + return -1; + intno = pic_read_irq(isa_pic); return intno; } @@ -100,10 +103,8 @@ int cpu_get_pic_interrupt(CPUState *env) static void pic_irq_request(void *opaque, int irq, int level) { CPUState *env = opaque; - if (level) + if (level && apic_accept_pic_intr(env)) cpu_interrupt(env, CPU_INTERRUPT_HARD); - else - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); } /* PC cmos mappings */ |