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-rw-r--r--hw/gpio/max7310.c5
-rw-r--r--hw/ppc/ppc4xx_pci.c2
-rw-r--r--hw/timer/hpet.c27
3 files changed, 9 insertions, 25 deletions
diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c
index 256d833c3a..db6b5e3d76 100644
--- a/hw/gpio/max7310.c
+++ b/hw/gpio/max7310.c
@@ -8,9 +8,7 @@
*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/i2c/i2c.h"
-#include "hw/hw.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
@@ -173,8 +171,7 @@ static const VMStateDescription vmstate_max7310 = {
static void max7310_gpio_set(void *opaque, int line, int level)
{
MAX7310State *s = (MAX7310State *) opaque;
- if (line >= ARRAY_SIZE(s->handler) || line < 0)
- hw_error("bad GPIO line");
+ assert(line >= 0 && line < ARRAY_SIZE(s->handler));
if (level)
s->level |= s->direction & (1 << line);
diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c
index c812d3408f..28724c06f8 100644
--- a/hw/ppc/ppc4xx_pci.c
+++ b/hw/ppc/ppc4xx_pci.c
@@ -54,7 +54,7 @@ struct PPC4xxPCIState {
struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
- qemu_irq irq[4];
+ qemu_irq irq[PCI_NUM_PINS];
MemoryRegion container;
MemoryRegion iomem;
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index b5d4072490..05fd86af81 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -417,20 +417,6 @@ static void hpet_del_timer(HPETTimer *t)
update_irq(t, 0);
}
-#ifdef HPET_DEBUG
-static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
-{
- printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
- return 0;
-}
-
-static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
-{
- printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
- return 0;
-}
-#endif
-
static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
@@ -510,7 +496,8 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
HPETState *s = opaque;
uint64_t old_val, new_val, val, index;
- DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
+ DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = 0x%" PRIx64 "\n",
+ addr, value);
index = addr;
old_val = hpet_ram_read(opaque, addr, 4);
new_val = value;
@@ -520,7 +507,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
uint8_t timer_id = (addr - 0x100) / 0x20;
HPETTimer *timer = &s->timer[timer_id];
- DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
+ DPRINTF("qemu: hpet_ram_writel timer_id = 0x%x\n", timer_id);
if (timer_id > s->num_timers) {
DPRINTF("qemu: timer id out of range\n");
return;
@@ -652,8 +639,8 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
}
s->hpet_counter =
(s->hpet_counter & 0xffffffff00000000ULL) | value;
- DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
- value, s->hpet_counter);
+ DPRINTF("qemu: HPET counter written. ctr = 0x%" PRIx64 " -> "
+ "%" PRIx64 "\n", value, s->hpet_counter);
break;
case HPET_COUNTER + 4:
if (hpet_enabled(s)) {
@@ -661,8 +648,8 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
}
s->hpet_counter =
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
- DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
- value, s->hpet_counter);
+ DPRINTF("qemu: HPET counter + 4 written. ctr = 0x%" PRIx64 " -> "
+ "%" PRIx64 "\n", value, s->hpet_counter);
break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");