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-rw-r--r--hw/bonito.c24
-rw-r--r--hw/fmopl.c2
-rw-r--r--hw/hpet.c8
-rw-r--r--hw/integratorcp.c16
-rw-r--r--hw/loader.c4
-rw-r--r--hw/mips_fulong2e.c2
-rw-r--r--hw/mst_fpga.c4
-rw-r--r--hw/qdev.c6
-rw-r--r--hw/sun4u.c1
-rw-r--r--hw/vga.c8
-rw-r--r--hw/virtio.c10
-rw-r--r--hw/virtio.h9
-rw-r--r--hw/vt82c686.c12
13 files changed, 60 insertions, 46 deletions
diff --git a/hw/bonito.c b/hw/bonito.c
index 8708e95688..fdb8198f62 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -241,7 +241,7 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
saddr = (addr - BONITO_REGBASE) >> 2;
- DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x \n", addr, val, saddr);
+ DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
switch (saddr) {
case BONITO_BONPONCFG:
case BONITO_IODEVCFG:
@@ -287,10 +287,10 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
break;
case BONITO_INTEN:
case BONITO_INTISR:
- DPRINTF("write to readonly bonito register %x \n", saddr);
+ DPRINTF("write to readonly bonito register %x\n", saddr);
break;
default:
- DPRINTF("write to unknown bonito register %x \n", saddr);
+ DPRINTF("write to unknown bonito register %x\n", saddr);
break;
}
}
@@ -302,7 +302,7 @@ static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
saddr = (addr - BONITO_REGBASE) >> 2;
- DPRINTF("bonito_readl "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
switch (saddr) {
case BONITO_INTISR:
return s->regs[saddr];
@@ -328,7 +328,7 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
{
PCIBonitoState *s = opaque;
- DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
s->dev.config_write(&s->dev, addr, val, 4);
}
@@ -443,7 +443,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
exit(1);
}
pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno);
- DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d \n",
+ DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno);
return pciaddr;
@@ -456,7 +456,7 @@ static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
@@ -480,7 +480,7 @@ static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr&0x1)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@@ -506,7 +506,7 @@ static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
+ DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr&0x3)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@@ -531,7 +531,7 @@ static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
@@ -555,7 +555,7 @@ static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
assert((addr&0x1)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@@ -581,7 +581,7 @@ static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx" \n", addr);
+ DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
assert((addr&0x3) == 0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
diff --git a/hw/fmopl.c b/hw/fmopl.c
index d8a0f36b35..5ad52ab7d2 100644
--- a/hw/fmopl.c
+++ b/hw/fmopl.c
@@ -606,7 +606,7 @@ static void init_timetables( FM_OPL *OPL , int ARRATE , int DRRATE )
}
#if 0
for (i = 0;i < 64 ;i++){ /* make for overflow area */
- LOG(LOG_WAR,("rate %2d , ar %f ms , dr %f ms \n",i,
+ LOG(LOG_WAR, ("rate %2d , ar %f ms , dr %f ms\n", i,
((double)(EG_ENT<<ENV_BITS) / OPL->AR_TABLE[i]) * (1000.0 / OPL->rate),
((double)(EG_ENT<<ENV_BITS) / OPL->DR_TABLE[i]) * (1000.0 / OPL->rate) ));
}
diff --git a/hw/hpet.c b/hw/hpet.c
index 4eda33d900..12bd64d8b1 100644
--- a/hw/hpet.c
+++ b/hw/hpet.c
@@ -397,7 +397,7 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
case HPET_CFG:
return s->config;
case HPET_CFG + 4:
- DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
+ DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
return 0;
case HPET_COUNTER:
if (hpet_enabled(s)) {
@@ -458,7 +458,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
uint8_t timer_id = (addr - 0x100) / 0x20;
HPETTimer *timer = &s->timer[timer_id];
- DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
+ DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
if (timer_id > s->num_timers) {
DPRINTF("qemu: timer id out of range\n");
return;
@@ -485,7 +485,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
break;
case HPET_TN_CMP: // comparator register
- DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
+ DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
if (timer->config & HPET_TN_32BIT) {
new_val = (uint32_t)new_val;
}
@@ -570,7 +570,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
}
break;
case HPET_CFG + 4:
- DPRINTF("qemu: invalid HPET_CFG+4 write \n");
+ DPRINTF("qemu: invalid HPET_CFG+4 write\n");
break;
case HPET_STATUS:
val = new_val & s->isr;
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 3c8982ea29..9a289b4776 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -14,6 +14,7 @@
#include "arm-misc.h"
#include "net.h"
#include "exec-memory.h"
+#include "sysemu.h"
typedef struct {
SysBusDevice busdev;
@@ -126,15 +127,20 @@ static void integratorcm_do_remap(integratorcm_state *s, int flash)
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
{
if (value & 8) {
- hw_error("Board reset\n");
+ qemu_system_reset_request();
}
- if ((s->cm_init ^ value) & 4) {
+ if ((s->cm_ctrl ^ value) & 4) {
integratorcm_do_remap(s, (value & 4) == 0);
}
- if ((s->cm_init ^ value) & 1) {
- printf("Green LED %s\n", (value & 1) ? "on" : "off");
+ if ((s->cm_ctrl ^ value) & 1) {
+ /* (value & 1) != 0 means the green "MISC LED" is lit.
+ * We don't have any nice place to display LEDs. printf is a bad
+ * idea because Linux uses the LED as a heartbeat and the output
+ * will swamp anything else on the terminal.
+ */
}
- s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
+ /* Note that the RESET bit [3] always reads as zero */
+ s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
}
static void integratorcm_update(integratorcm_state *s)
diff --git a/hw/loader.c b/hw/loader.c
index 8efb1466cd..5676c18214 100644
--- a/hw/loader.c
+++ b/hw/loader.c
@@ -779,13 +779,13 @@ void do_info_roms(Monitor *mon)
QTAILQ_FOREACH(rom, &roms, next) {
if (!rom->fw_file) {
monitor_printf(mon, "addr=" TARGET_FMT_plx
- " size=0x%06zx mem=%s name=\"%s\" \n",
+ " size=0x%06zx mem=%s name=\"%s\"\n",
rom->addr, rom->romsize,
rom->isrom ? "rom" : "ram",
rom->name);
} else {
monitor_printf(mon, "fw=%s/%s"
- " size=0x%06zx name=\"%s\" \n",
+ " size=0x%06zx name=\"%s\"\n",
rom->fw_dir,
rom->fw_file,
rom->romsize,
diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index abe30569f2..f52b8c5083 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -343,7 +343,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
via_devfn = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0));
if (via_devfn < 0) {
- fprintf(stderr, "vt82c686b_init error \n");
+ fprintf(stderr, "vt82c686b_init error\n");
exit(1);
}
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 4e47574b63..7bcd5d75e8 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -118,7 +118,7 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr)
return s->pcmcia1;
default:
printf("Mainstone - mst_fpga_readb: Bad register offset "
- "0x" TARGET_FMT_plx " \n", addr);
+ "0x" TARGET_FMT_plx "\n", addr);
}
return 0;
}
@@ -171,7 +171,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
break;
default:
printf("Mainstone - mst_fpga_writeb: Bad register offset "
- "0x" TARGET_FMT_plx " \n", addr);
+ "0x" TARGET_FMT_plx "\n", addr);
}
}
diff --git a/hw/qdev.c b/hw/qdev.c
index c463c52150..a223d41cd3 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -207,6 +207,12 @@ int qdev_device_help(QemuOpts *opts)
}
error_printf("%s.%s=%s\n", info->name, prop->name, prop->info->name);
}
+ for (prop = info->bus_info->props; prop && prop->name; prop++) {
+ if (!prop->info->parse) {
+ continue; /* no way to set it, don't show */
+ }
+ error_printf("%s.%s=%s\n", info->name, prop->name, prop->info->name);
+ }
return 1;
}
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 32e6ab9beb..6afb0e7158 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -763,7 +763,6 @@ static void sun4uv_init(ram_addr_t RAM_size,
irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
&pci_bus3);
- isa_mem_base = APB_PCI_IO_BASE;
pci_vga_init(pci_bus);
// XXX Should be pci_bus3
diff --git a/hw/vga.c b/hw/vga.c
index 125fb293f2..f9a6014f4e 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -149,7 +149,7 @@ static uint16_t expand2[256];
static uint8_t expand4to8[16];
static void vga_screen_dump(void *opaque, const char *filename);
-static char *screen_dump_filename;
+static const char *screen_dump_filename;
static DisplayChangeListener *screen_dump_dcl;
static void vga_update_memory_access(VGACommonState *s)
@@ -181,6 +181,7 @@ static void vga_update_memory_access(VGACommonState *s)
size = 0x8000;
break;
}
+ base += isa_mem_base;
region = g_malloc(sizeof(*region));
memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
memory_region_add_subregion_overlap(s->legacy_address_space, base,
@@ -2318,7 +2319,6 @@ static void vga_save_dpy_update(DisplayState *ds,
{
if (screen_dump_filename) {
ppm_save(screen_dump_filename, ds->surface);
- screen_dump_filename = NULL;
}
}
@@ -2396,8 +2396,8 @@ static void vga_screen_dump(void *opaque, const char *filename)
if (!screen_dump_dcl)
screen_dump_dcl = vga_screen_dump_init(s->ds);
- screen_dump_filename = (char *)filename;
+ screen_dump_filename = filename;
vga_invalidate_display(s);
vga_hw_update();
+ screen_dump_filename = NULL;
}
-
diff --git a/hw/virtio.c b/hw/virtio.c
index c577bbe483..d9bf266492 100644
--- a/hw/virtio.c
+++ b/hw/virtio.c
@@ -498,6 +498,16 @@ void virtio_update_irq(VirtIODevice *vdev)
virtio_notify_vector(vdev, VIRTIO_NO_VECTOR);
}
+void virtio_set_status(VirtIODevice *vdev, uint8_t val)
+{
+ trace_virtio_set_status(vdev, val);
+
+ if (vdev->set_status) {
+ vdev->set_status(vdev, val);
+ }
+ vdev->status = val;
+}
+
void virtio_reset(void *opaque)
{
VirtIODevice *vdev = opaque;
diff --git a/hw/virtio.h b/hw/virtio.h
index 4d20d9b8f4..2d18209fb2 100644
--- a/hw/virtio.h
+++ b/hw/virtio.h
@@ -135,14 +135,6 @@ struct VirtIODevice
VMChangeStateEntry *vmstate;
};
-static inline void virtio_set_status(VirtIODevice *vdev, uint8_t val)
-{
- if (vdev->set_status) {
- vdev->set_status(vdev, val);
- }
- vdev->status = val;
-}
-
VirtQueue *virtio_add_queue(VirtIODevice *vdev, int queue_size,
void (*handle_output)(VirtIODevice *,
VirtQueue *));
@@ -190,6 +182,7 @@ int virtio_queue_get_num(VirtIODevice *vdev, int n);
void virtio_queue_notify(VirtIODevice *vdev, int n);
uint16_t virtio_queue_vector(VirtIODevice *vdev, int n);
void virtio_queue_set_vector(VirtIODevice *vdev, int n, uint16_t vector);
+void virtio_set_status(VirtIODevice *vdev, uint8_t val);
void virtio_reset(void *opaque);
void virtio_update_irq(VirtIODevice *vdev);
diff --git a/hw/vt82c686.c b/hw/vt82c686.c
index 5c973ed507..b9fcc0e4ac 100644
--- a/hw/vt82c686.c
+++ b/hw/vt82c686.c
@@ -49,7 +49,7 @@ static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
int can_write;
SuperIOConfig *superio_conf = opaque;
- DPRINTF("superio_ioport_writeb address 0x%x val 0x%x \n", addr, data);
+ DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
if (addr == 0x3f0) {
superio_conf->index = data & 0xff;
} else {
@@ -73,12 +73,12 @@ static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
switch (superio_conf->index) {
case 0xe7:
if ((data & 0xff) != 0xfe) {
- DPRINTF("chage uart 1 base. unsupported yet \n");
+ DPRINTF("chage uart 1 base. unsupported yet\n");
}
break;
case 0xe8:
if ((data & 0xff) != 0xbe) {
- DPRINTF("chage uart 2 base. unsupported yet \n");
+ DPRINTF("chage uart 2 base. unsupported yet\n");
}
break;
@@ -95,7 +95,7 @@ static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
{
SuperIOConfig *superio_conf = opaque;
- DPRINTF("superio_ioport_readb address 0x%x \n", addr);
+ DPRINTF("superio_ioport_readb address 0x%x\n", addr);
return (superio_conf->config[superio_conf->index]);
}
@@ -133,7 +133,7 @@ static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
{
VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
- DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x \n",
+ DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
address, val, len);
pci_default_write_config(d, address, val, len);
@@ -285,7 +285,7 @@ static void pm_io_space_update(VT686PMState *s)
static void pm_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
- DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x \n",
+ DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
address, val, len);
pci_default_write_config(d, address, val, len);
}
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-06 10:58:02 +0000