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-rw-r--r--hw/mips_jazz.c90
-rw-r--r--hw/mips_malta.c53
-rw-r--r--hw/mips_mipssim.c15
-rw-r--r--hw/mips_r4k.c39
-rw-r--r--hw/musicpal.c243
-rw-r--r--hw/omap.h32
-rw-r--r--hw/omap1.c859
-rw-r--r--hw/omap2.c6
-rw-r--r--hw/omap_lcdc.c7
-rw-r--r--hw/omap_sx1.c4
-rw-r--r--hw/palm.c4
-rw-r--r--hw/soc_dma.h8
12 files changed, 705 insertions, 655 deletions
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index f3c9f93204..7cac5da920 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -52,44 +52,42 @@ static void main_cpu_reset(void *opaque)
cpu_reset(env);
}
-static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
return cpu_inw(0x71);
}
-static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtc_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
cpu_outw(0x71, val & 0xff);
}
-static CPUReadMemoryFunc * const rtc_read[3] = {
- rtc_readb,
- rtc_readb,
- rtc_readb,
+static const MemoryRegionOps rtc_ops = {
+ .read = rtc_read,
+ .write = rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const rtc_write[3] = {
- rtc_writeb,
- rtc_writeb,
- rtc_writeb,
-};
-
-static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
+ return 0xff;
}
-static CPUReadMemoryFunc * const dma_dummy_read[3] = {
- NULL,
- NULL,
- NULL,
-};
+static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ /* Nothing to do. That is only to ensure that
+ * the current DMA acknowledge cycle is completed. */
+}
-static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
- dma_dummy_writeb,
- dma_dummy_writeb,
- dma_dummy_writeb,
+static const MemoryRegionOps dma_dummy_ops = {
+ .read = dma_dummy_read,
+ .write = dma_dummy_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
@@ -105,7 +103,7 @@ static void cpu_request_exit(void *opaque, int irq, int level)
}
static
-void mips_jazz_init (ram_addr_t ram_size,
+void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
@@ -115,7 +113,8 @@ void mips_jazz_init (ram_addr_t ram_size,
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
- int s_rtc, s_dma_dummy;
+ MemoryRegion *rtc = g_new(MemoryRegion, 1);
+ MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev;
SysBusDevice *sysbus;
@@ -123,8 +122,9 @@ void mips_jazz_init (ram_addr_t ram_size,
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
qemu_irq *cpu_exit_irq;
- ram_addr_t ram_offset;
- ram_addr_t bios_offset;
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
@@ -143,14 +143,15 @@ void mips_jazz_init (ram_addr_t ram_size,
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
- ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
+ memory_region_add_subregion(address_space, 0, ram);
- bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
- cpu_register_physical_memory(0x1fc00000LL,
- MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
- cpu_register_physical_memory(0xfff00000LL,
- MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
+ memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
+ memory_region_set_readonly(bios, true);
+ memory_region_init_alias(bios2, "mips_jazz.bios", bios,
+ 0, MAGNUM_BIOS_SIZE);
+ memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
+ memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
@@ -175,9 +176,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
- s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
+ memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
+ memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA devices */
i8259 = i8259_init(env->irq[4]);
@@ -203,10 +203,11 @@ void mips_jazz_init (ram_addr_t ram_size,
sysbus_connect_irq(sysbus, 0, rc4030[3]);
{
/* Simple ROM, so user doesn't have to provide one */
- ram_addr_t rom_offset = qemu_ram_alloc(NULL, "g364fb.rom", 0x80000);
- uint8_t *rom = qemu_get_ram_ptr(rom_offset);
- cpu_register_physical_memory(0x60000000, 0x80000,
- rom_offset | IO_MEM_ROM);
+ MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
+ memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
+ memory_region_set_readonly(rom_mr, true);
+ uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
+ memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
@@ -252,9 +253,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Real time clock */
rtc_init(1980, NULL);
- s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
+ memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
+ memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
@@ -299,7 +299,7 @@ void mips_magnum_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
+ mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_MAGNUM);
}
static
@@ -308,7 +308,7 @@ void mips_pica61_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
+ mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_PICA61);
}
static QEMUMachine mips_magnum_machine = {
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index e7cdf2091b..0110daa1a3 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -57,6 +57,9 @@
#define MAX_IDE_BUS 2
typedef struct {
+ MemoryRegion iomem;
+ MemoryRegion iomem_lo; /* 0 - 0x900 */
+ MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
uint32_t leds;
uint32_t brk;
uint32_t gpout;
@@ -215,7 +218,8 @@ static void eeprom24c0x_write(int scl, int sda)
eeprom.sda = sda;
}
-static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t val = 0;
@@ -302,8 +306,8 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
return val;
}
-static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t saddr;
@@ -328,7 +332,7 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
/* ASCIIWORD Register */
case 0x00410:
- snprintf(s->display_text, 9, "%08X", val);
+ snprintf(s->display_text, 9, "%08X", (uint32_t)val);
malta_fpga_update_display(s);
break;
@@ -388,16 +392,10 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const malta_fpga_read[] = {
- malta_fpga_readl,
- malta_fpga_readl,
- malta_fpga_readl
-};
-
-static CPUWriteMemoryFunc * const malta_fpga_write[] = {
- malta_fpga_writel,
- malta_fpga_writel,
- malta_fpga_writel
+static const MemoryRegionOps malta_fpga_ops = {
+ .read = malta_fpga_read,
+ .write = malta_fpga_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void malta_fpga_reset(void *opaque)
@@ -429,20 +427,22 @@ static void malta_fpga_led_init(CharDriverState *chr)
qemu_chr_fe_printf(chr, "+--------+\r\n");
}
-static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
+static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
+ target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
- int malta;
s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
- malta = cpu_register_io_memory(malta_fpga_read,
- malta_fpga_write, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &malta_fpga_ops, s,
+ "malta-fpga", 0x100000);
+ memory_region_init_alias(&s->iomem_lo, "malta-fpga",
+ &s->iomem, 0, 0x900);
+ memory_region_init_alias(&s->iomem_hi, "malta-fpga",
+ &s->iomem, 0xa00, 0x10000-0xa00);
- cpu_register_physical_memory(base, 0x900, malta);
- /* 0xa00 is less than a page, so will still get the right offsets. */
- cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
+ memory_region_add_subregion(address_space, base, &s->iomem_lo);
+ memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
@@ -771,8 +771,8 @@ void mips_malta_init (ram_addr_t ram_size,
{
char *filename;
pflash_t *fl;
- ram_addr_t ram_offset;
MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios, *bios_alias = g_new(MemoryRegion, 1);
target_long bios_size;
int64_t kernel_entry;
@@ -828,9 +828,8 @@ void mips_malta_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
- ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
-
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_init_ram(ram, NULL, "mips_malta.ram", ram_size);
+ memory_region_add_subregion(system_memory, 0, ram);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
@@ -838,7 +837,7 @@ void mips_malta_init (ram_addr_t ram_size,
be = 0;
#endif
/* FPGA */
- malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
+ malta_fpga_init(system_memory, 0x1f000000LL, env->irq[2], serial_hds[2]);
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
if (kernel_filename) {
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index ac65555b74..740715854b 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -137,8 +137,9 @@ mips_mipssim_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- ram_addr_t ram_offset;
- ram_addr_t bios_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
CPUState *env;
ResetData *reset_info;
int bios_size;
@@ -162,14 +163,14 @@ mips_mipssim_init (ram_addr_t ram_size,
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate RAM. */
- ram_offset = qemu_ram_alloc(NULL, "mips_mipssim.ram", ram_size);
- bios_offset = qemu_ram_alloc(NULL, "mips_mipssim.bios", BIOS_SIZE);
+ memory_region_init_ram(ram, NULL, "mips_mipssim.ram", ram_size);
+ memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE);
+ memory_region_set_readonly(bios, true);
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* Map the BIOS / boot exception handler. */
- cpu_register_physical_memory(0x1fc00000LL,
- BIOS_SIZE, bios_offset | IO_MEM_ROM);
+ memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* Load a BIOS / boot exception handler image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 5d002c5a2b..805d02a4eb 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -42,8 +42,8 @@ static struct _loaderparams {
const char *initrd_filename;
} loaderparams;
-static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_reset_request ();
@@ -51,25 +51,18 @@ static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
qemu_system_shutdown_request ();
}
-static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
return 0;
}
-static CPUWriteMemoryFunc * const mips_qemu_write[] = {
- &mips_qemu_writel,
- &mips_qemu_writel,
- &mips_qemu_writel,
+static const MemoryRegionOps mips_qemu_ops = {
+ .read = mips_qemu_read,
+ .write = mips_qemu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUReadMemoryFunc * const mips_qemu_read[] = {
- &mips_qemu_readl,
- &mips_qemu_readl,
- &mips_qemu_readl,
-};
-
-static int mips_qemu_iomemtype = 0;
-
typedef struct ResetData {
CPUState *env;
uint64_t vector;
@@ -163,8 +156,10 @@ void mips_r4k_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- ram_addr_t ram_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios;
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
int bios_size;
CPUState *env;
ResetData *reset_info;
@@ -199,16 +194,12 @@ void mips_r4k_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
- ram_offset = qemu_ram_alloc(NULL, "mips_r4k.ram", ram_size);
+ memory_region_init_ram(ram, NULL, "mips_r4k.ram", ram_size);
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
- if (!mips_qemu_iomemtype) {
- mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
- mips_qemu_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- }
- cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
+ memory_region_init_io(iomem, &mips_qemu_ops, NULL, "mips-qemu", 0x10000);
+ memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
/* Try to load a BIOS image. If this fails, we continue regardless,
but initialize the hardware ourselves. When a kernel gets
diff --git a/hw/musicpal.c b/hw/musicpal.c
index ade5a91feb..9b1f38062b 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -19,6 +19,7 @@
#include "console.h"
#include "i2c.h"
#include "blockdev.h"
+#include "exec-memory.h"
#define MP_MISC_BASE 0x80002000
#define MP_MISC_SIZE 0x00001000
@@ -142,6 +143,7 @@ typedef struct mv88w8618_rx_desc {
typedef struct mv88w8618_eth_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
qemu_irq irq;
uint32_t smir;
uint32_t icr;
@@ -260,7 +262,8 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
} while (desc_addr != s->tx_queue[queue_index]);
}
-static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -302,7 +305,7 @@ static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -353,16 +356,10 @@ static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
- mv88w8618_eth_read,
- mv88w8618_eth_read,
- mv88w8618_eth_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
- mv88w8618_eth_write,
- mv88w8618_eth_write,
- mv88w8618_eth_write
+static const MemoryRegionOps mv88w8618_eth_ops = {
+ .read = mv88w8618_eth_read,
+ .write = mv88w8618_eth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void eth_cleanup(VLANClientState *nc)
@@ -387,10 +384,9 @@ static int mv88w8618_eth_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
- s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
- mv88w8618_eth_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
+ memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
+ MP_ETH_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -444,6 +440,7 @@ static SysBusDeviceInfo mv88w8618_eth_info = {
typedef struct musicpal_lcd_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t brightness;
uint32_t mode;
uint32_t irqctrl;
@@ -528,7 +525,8 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
s->brightness |= level << irq;
}
-static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
+static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -542,7 +540,7 @@ static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -581,29 +579,21 @@ static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
- musicpal_lcd_read,
- musicpal_lcd_read,
- musicpal_lcd_read
-};
-
-static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
- musicpal_lcd_write,
- musicpal_lcd_write,
- musicpal_lcd_write
+static const MemoryRegionOps musicpal_lcd_ops = {
+ .read = musicpal_lcd_read,
+ .write = musicpal_lcd_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int musicpal_lcd_init(SysBusDevice *dev)
{
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
- int iomemtype;
s->brightness = 7;
- iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
- musicpal_lcd_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
+ "musicpal-lcd", MP_LCD_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
@@ -645,6 +635,7 @@ static SysBusDeviceInfo musicpal_lcd_info = {
typedef struct mv88w8618_pic_state
{
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t level;
uint32_t enabled;
qemu_irq parent_irq;
@@ -667,7 +658,8 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
mv88w8618_pic_update(s);
}
-static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -681,7 +673,7 @@ static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -707,29 +699,21 @@ static void mv88w8618_pic_reset(DeviceState *d)
s->enabled = 0;
}
-static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
- mv88w8618_pic_read,
- mv88w8618_pic_read,
- mv88w8618_pic_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
- mv88w8618_pic_write,
- mv88w8618_pic_write,
- mv88w8618_pic_write
+static const MemoryRegionOps mv88w8618_pic_ops = {
+ .read = mv88w8618_pic_read,
+ .write = mv88w8618_pic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_pic_init(SysBusDevice *dev)
{
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
- int iomemtype;
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
- iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
- mv88w8618_pic_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
+ "musicpal-pic", MP_PIC_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -775,6 +759,7 @@ typedef struct mv88w8618_timer_state {
typedef struct mv88w8618_pit_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
mv88w8618_timer_state timer[4];
} mv88w8618_pit_state;
@@ -797,7 +782,8 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
s->ptimer = ptimer_init(bh);
}
-static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@@ -813,7 +799,7 @@ static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@@ -864,21 +850,14 @@ static void mv88w8618_pit_reset(DeviceState *d)
}
}
-static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
- mv88w8618_pit_read,
- mv88w8618_pit_read,
- mv88w8618_pit_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
- mv88w8618_pit_write,
- mv88w8618_pit_write,
- mv88w8618_pit_write
+static const MemoryRegionOps mv88w8618_pit_ops = {
+ .read = mv88w8618_pit_read,
+ .write = mv88w8618_pit_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_pit_init(SysBusDevice *dev)
{
- int iomemtype;
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
int i;
@@ -888,10 +867,9 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
}
- iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
- mv88w8618_pit_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
+ "musicpal-pit", MP_PIT_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -932,11 +910,13 @@ static SysBusDeviceInfo mv88w8618_pit_info = {
typedef struct mv88w8618_flashcfg_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t cfgr0;
} mv88w8618_flashcfg_state;
-static uint32_t mv88w8618_flashcfg_read(void *opaque,
- target_phys_addr_t offset)
+static uint64_t mv88w8618_flashcfg_read(void *opaque,
+ target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -950,7 +930,7 @@ static uint32_t mv88w8618_flashcfg_read(void *opaque,
}
static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -961,28 +941,20 @@ static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
- mv88w8618_flashcfg_read,
- mv88w8618_flashcfg_read,
- mv88w8618_flashcfg_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
- mv88w8618_flashcfg_write,
- mv88w8618_flashcfg_write,
- mv88w8618_flashcfg_write
+static const MemoryRegionOps mv88w8618_flashcfg_ops = {
+ .read = mv88w8618_flashcfg_read,
+ .write = mv88w8618_flashcfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_flashcfg_init(SysBusDevice *dev)
{
- int iomemtype;
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
- iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
- mv88w8618_flashcfg_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
+ "musicpal-flashcfg", MP_FLASHCFG_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -1009,7 +981,8 @@ static SysBusDeviceInfo mv88w8618_flashcfg_info = {
#define MP_BOARD_REVISION 0x31
-static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
+static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
switch (offset) {
case MP_MISC_BOARD_REVISION:
@@ -1021,37 +994,31 @@ static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
}
-static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
- musicpal_misc_read,
- musicpal_misc_read,
- musicpal_misc_read,
-};
-
-static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
- musicpal_misc_write,
- musicpal_misc_write,
- musicpal_misc_write,
+static const MemoryRegionOps musicpal_misc_ops = {
+ .read = musicpal_misc_read,
+ .write = musicpal_misc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void musicpal_misc_init(void)
+static void musicpal_misc_init(SysBusDevice *dev)
{
- int iomemtype;
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
- iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
- musicpal_misc_writefn, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
+ memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
+ "musicpal-misc", MP_MISC_SIZE);
+ sysbus_add_memory(dev, MP_MISC_BASE, iomem);
}
/* WLAN register offsets */
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
-static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
switch (offset) {
/* Workaround to allow loading the binary-only wlandrv.ko crap
@@ -1067,30 +1034,23 @@ static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
}
-static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
- mv88w8618_wlan_read,
- mv88w8618_wlan_read,
- mv88w8618_wlan_read,
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
- mv88w8618_wlan_write,
- mv88w8618_wlan_write,
- mv88w8618_wlan_write,
+static const MemoryRegionOps mv88w8618_wlan_ops = {
+ .read = mv88w8618_wlan_read,
+ .write =mv88w8618_wlan_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_wlan_init(SysBusDevice *dev)
{
- int iomemtype;
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
- iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
- mv88w8618_wlan_writefn, NULL,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
+ memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
+ "musicpal-wlan", MP_WLAN_SIZE);
+ sysbus_init_mmio_region(dev, iomem);
return 0;
}
@@ -1118,6 +1078,7 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
typedef struct musicpal_gpio_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t lcd_brightness;
uint32_t out_state;
uint32_t in_state;
@@ -1190,7 +1151,8 @@ static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
}
}
-static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
+static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
musicpal_gpio_state *s = opaque;
@@ -1229,7 +1191,7 @@ static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
musicpal_gpio_state *s = opaque;
switch (offset) {
@@ -1267,16 +1229,10 @@ static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
- musicpal_gpio_read,
- musicpal_gpio_read,
- musicpal_gpio_read,
-};
-
-static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
- musicpal_gpio_write,
- musicpal_gpio_write,
- musicpal_gpio_write,
+static const MemoryRegionOps musicpal_gpio_ops = {
+ .read = musicpal_gpio_read,
+ .write = musicpal_gpio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void musicpal_gpio_reset(DeviceState *d)
@@ -1295,14 +1251,12 @@ static void musicpal_gpio_reset(DeviceState *d)
static int musicpal_gpio_init(SysBusDevice *dev)
{
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
- int iomemtype;
sysbus_init_irq(dev, &s->irq);
- iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
- musicpal_gpio_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
+ "musicpal-gpio", MP_GPIO_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
@@ -1501,7 +1455,9 @@ static void musicpal_init(ram_addr_t ram_size,
int i;
unsigned long flash_size;
DriveInfo *dinfo;
- ram_addr_t sram_off;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model) {
cpu_model = "arm926";
@@ -1514,12 +1470,11 @@ static void musicpal_init(ram_addr_t ram_size,
cpu_pic = arm_pic_init_cpu(env);
/* For now we use a fixed - the original - RAM size */
- cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
- qemu_ram_alloc(NULL, "musicpal.ram",
- MP_RAM_DEFAULT_SIZE));
+ memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
+ memory_region_add_subregion(address_space_mem, 0, ram);
- sram_off = qemu_ram_alloc(NULL, "musicpal.sram", MP_SRAM_SIZE);
- cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
+ memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE);
+ memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
cpu_pic[ARM_PIC_CPU_IRQ]);
@@ -1594,7 +1549,7 @@ static void musicpal_init(ram_addr_t ram_size,
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
- musicpal_misc_init();
+ musicpal_misc_init(sysbus_from_qdev(dev));
dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
diff --git a/hw/omap.h b/hw/omap.h
index d9ab006ae0..0260cc0d4a 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -678,7 +678,8 @@ void omap_uart_reset(struct omap_uart_s *s);
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
struct omap_mpuio_s;
-struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
+struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk);
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
@@ -691,7 +692,8 @@ struct uWireSlave {
void *opaque;
};
struct omap_uwire_s;
-struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
+struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq *irq, qemu_irq dma, omap_clk clk);
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect);
@@ -730,7 +732,8 @@ struct I2SCodec {
} in, out;
};
struct omap_mcbsp_s;
-struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
+struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk);
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
@@ -741,8 +744,7 @@ void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
- struct omap_dma_lcd_channel_s *dma,
- ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
+ struct omap_dma_lcd_channel_s *dma, omap_clk clk);
/* omap_dss.c */
struct rfbi_chip_s {
@@ -826,6 +828,22 @@ struct omap_mpu_state_s {
qemu_irq wakeup;
+ MemoryRegion ulpd_pm_iomem;
+ MemoryRegion pin_cfg_iomem;
+ MemoryRegion id_iomem;
+ MemoryRegion id_iomem_e18;
+ MemoryRegion id_iomem_ed4;
+ MemoryRegion id_iomem_e20;
+ MemoryRegion mpui_iomem;
+ MemoryRegion tcmi_iomem;
+ MemoryRegion clkm_iomem;
+ MemoryRegion clkdsp_iomem;
+ MemoryRegion pwl_iomem;
+ MemoryRegion pwt_iomem;
+ MemoryRegion mpui_io_iomem;
+ MemoryRegion imif_ram;
+ MemoryRegion emiff_ram;
+
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset);
@@ -907,6 +925,7 @@ struct omap_mpu_state_s {
uint32_t tcmi_regs[17];
struct dpll_ctl_s {
+ MemoryRegion iomem;
uint16_t mode;
omap_clk dpll;
} dpll[3];
@@ -947,7 +966,8 @@ struct omap_mpu_state_s {
};
/* omap1.c */
-struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
+ unsigned long sdram_size,
const char *core);
/* omap2.c */
diff --git a/hw/omap1.c b/hw/omap1.c
index 614fd31b01..f747321e97 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -84,6 +84,7 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
/* MPU OS timers */
struct omap_mpu_timer_s {
+ MemoryRegion iomem;
qemu_irq irq;
omap_clk clk;
uint32_t val;
@@ -179,10 +180,15 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
timer->rate = omap_clk_getrate(timer->clk);
}
-static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
@@ -199,10 +205,14 @@ static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(s);
@@ -226,16 +236,10 @@ static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_mpu_timer_read,
-};
-
-static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_mpu_timer_write,
+static const MemoryRegionOps omap_mpu_timer_ops = {
+ .read = omap_mpu_timer_read,
+ .write = omap_mpu_timer_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
@@ -250,10 +254,10 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
s->it_ena = 1;
}
-static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
+static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
- int iomemtype;
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
g_malloc0(sizeof(struct omap_mpu_timer_s));
@@ -264,9 +268,10 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
omap_mpu_timer_reset(s);
omap_timer_clk_setup(s);
- iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
- omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
+ "omap-mpu-timer", 0x100);
+
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
@@ -274,16 +279,22 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
/* Watchdog timer */
struct omap_watchdog_timer_s {
struct omap_mpu_timer_s timer;
+ MemoryRegion iomem;
uint8_t last_wr;
int mode;
int free;
int reset;
};
-static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->timer.ptv << 9) | (s->timer.ar << 8) |
@@ -301,10 +312,14 @@ static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
}
static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(&s->timer);
@@ -344,16 +359,10 @@ static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = {
- omap_badwidth_read16,
- omap_wd_timer_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {
- omap_badwidth_write16,
- omap_wd_timer_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_wd_timer_ops = {
+ .read = omap_wd_timer_read,
+ .write = omap_wd_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
@@ -374,10 +383,10 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
omap_timer_update(&s->timer);
}
-static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
+static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
+ target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
- int iomemtype;
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
g_malloc0(sizeof(struct omap_watchdog_timer_s));
@@ -387,9 +396,9 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
- iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
- omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
+ "omap-wd-timer", 0x100);
+ memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
@@ -397,13 +406,19 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
/* 32-kHz timer */
struct omap_32khz_timer_s {
struct omap_mpu_timer_s timer;
+ MemoryRegion iomem;
};
-static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* TVR */
return s->timer.reset_val;
@@ -422,11 +437,15 @@ static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
}
static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* TVR */
s->timer.reset_val = value & 0x00ffffff;
@@ -452,16 +471,10 @@ static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_os_timer_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_os_timer_read,
-};
-
-static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_os_timer_write,
+static const MemoryRegionOps omap_os_timer_ops = {
+ .read = omap_os_timer_read,
+ .write = omap_os_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
@@ -476,10 +489,10 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
s->timer.ar = 1;
}
-static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
+static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
+ target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
- int iomemtype;
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
g_malloc0(sizeof(struct omap_32khz_timer_s));
@@ -489,19 +502,24 @@ static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
- iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
- omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
+ "omap-os-timer", 0x800);
+ memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
/* Ultra Low-Power Device Module */
-static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
@@ -560,7 +578,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
}
static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int64_t now, ticks;
@@ -568,6 +586,10 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
static const int bypass_div[4] = { 1, 2, 4, 4 };
uint16_t diff;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
@@ -674,16 +696,10 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = {
- omap_badwidth_read16,
- omap_ulpd_pm_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {
- omap_badwidth_write16,
- omap_ulpd_pm_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_ulpd_pm_ops = {
+ .read = omap_ulpd_pm_read,
+ .write = omap_ulpd_pm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
@@ -713,21 +729,26 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
}
-static void omap_ulpd_pm_init(target_phys_addr_t base,
+static void omap_ulpd_pm_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
- omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
+ "omap-ulpd-pm", 0x800);
+ memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
omap_ulpd_pm_reset(mpu);
}
/* OMAP Pin Configuration */
-static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
case 0x04: /* FUNC_MUX_CTRL_1 */
@@ -827,11 +848,15 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
}
static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t diff;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
diff = s->func_mux_ctrl[addr >> 2] ^ value;
@@ -900,16 +925,10 @@ static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_pin_cfg_read,
-};
-
-static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_pin_cfg_write,
+static const MemoryRegionOps omap_pin_cfg_ops = {
+ .read = omap_pin_cfg_read,
+ .write = omap_pin_cfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
@@ -928,21 +947,26 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
}
-static void omap_pin_cfg_init(target_phys_addr_t base,
+static void omap_pin_cfg_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
- omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
+ "omap-pin-cfg", 0x800);
+ memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
omap_pin_cfg_reset(mpu);
}
/* Device Identification, Die Identification */
-static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0xfffe1800: /* DIE_ID_LSB */
return 0xc9581f0e;
@@ -982,38 +1006,48 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
}
static void omap_id_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap_id_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_id_read,
+static const MemoryRegionOps omap_id_ops = {
+ .read = omap_id_read,
+ .write = omap_id_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const omap_id_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_id_write,
-};
-
-static void omap_id_init(struct omap_mpu_state_s *mpu)
+static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_id_readfn,
- omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
- cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
- if (!cpu_is_omap15xx(mpu))
- cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000);
+ memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
+ "omap-id", 0x100000000ULL);
+ memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
+ 0xfffe1800, 0x800);
+ memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
+ memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
+ 0xfffed400, 0x100);
+ memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
+ if (!cpu_is_omap15xx(mpu)) {
+ memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
+ &mpu->id_iomem, 0xfffe2000, 0x800);
+ memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
+ }
}
/* MPUI Control (Dummy) */
-static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* CTRL */
return s->mpui_ctrl;
@@ -1039,10 +1073,14 @@ static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* CTRL */
s->mpui_ctrl = value & 0x007fffff;
@@ -1064,16 +1102,10 @@ static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_mpui_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_mpui_read,
-};
-
-static CPUWriteMemoryFunc * const omap_mpui_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_mpui_write,
+static const MemoryRegionOps omap_mpui_ops = {
+ .read = omap_mpui_read,
+ .write = omap_mpui_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mpui_reset(struct omap_mpu_state_s *s)
@@ -1081,13 +1113,12 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
s->mpui_ctrl = 0x0003ff1b;
}
-static void omap_mpui_init(target_phys_addr_t base,
+static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
- omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
+ "omap-mpui", 0x100);
+ memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
omap_mpui_reset(mpu);
}
@@ -1095,6 +1126,7 @@ static void omap_mpui_init(target_phys_addr_t base,
/* TIPB Bridges */
struct omap_tipb_bridge_s {
qemu_irq abort;
+ MemoryRegion iomem;
int width_intr;
uint16_t control;
@@ -1103,10 +1135,15 @@ struct omap_tipb_bridge_s {
uint16_t enh_control;
};
-static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+ if (size < 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* TIPB_CNTL */
return s->control;
@@ -1129,10 +1166,14 @@ static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
}
static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+ if (size < 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* TIPB_CNTL */
s->control = value & 0xffff;
@@ -1163,16 +1204,10 @@ static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = {
- omap_badwidth_read16,
- omap_tipb_bridge_read,
- omap_tipb_bridge_read,
-};
-
-static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = {
- omap_badwidth_write16,
- omap_tipb_bridge_write,
- omap_tipb_bridge_write,
+static const MemoryRegionOps omap_tipb_bridge_ops = {
+ .read = omap_tipb_bridge_read,
+ .write = omap_tipb_bridge_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
@@ -1183,29 +1218,34 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
s->enh_control = 0x000f;
}
-static struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
- qemu_irq abort_irq, omap_clk clk)
+static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
+ MemoryRegion *memory, target_phys_addr_t base,
+ qemu_irq abort_irq, omap_clk clk)
{
- int iomemtype;
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
g_malloc0(sizeof(struct omap_tipb_bridge_s));
s->abort = abort_irq;
omap_tipb_bridge_reset(s);
- iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
- omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
+ "omap-tipb-bridge", 0x100);
+ memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
/* Dummy Traffic Controller's Memory Interface */
-static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t ret;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
@@ -1235,10 +1275,14 @@ static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
}
static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
@@ -1265,16 +1309,10 @@ static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_tcmi_read,
-};
-
-static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_tcmi_write,
+static const MemoryRegionOps omap_tcmi_ops = {
+ .read = omap_tcmi_read,
+ .write = omap_tcmi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
@@ -1296,21 +1334,25 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(target_phys_addr_t base,
+static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
- omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
+ "omap-tcmi", 0x100);
+ memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
omap_tcmi_reset(mpu);
}
/* Digital phase-locked loops control */
-static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
if (addr == 0x00) /* CTL_REG */
return s->mode;
@@ -1319,13 +1361,17 @@ static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
}
static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
uint16_t diff;
static const int bypass_div[4] = { 1, 2, 4, 4 };
int div, mult;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
if (addr == 0x00) { /* CTL_REG */
/* See omap_ulpd_pm_write() too */
diff = s->mode & value;
@@ -1351,16 +1397,10 @@ static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
- omap_badwidth_read16,
- omap_dpll_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
- omap_badwidth_write16,
- omap_dpll_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_dpll_ops = {
+ .read = omap_dpll_read,
+ .write = omap_dpll_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_dpll_reset(struct dpll_ctl_s *s)
@@ -1369,23 +1409,27 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
omap_clk_setrate(s->dpll, 1, 1);
}
-static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
- omap_clk clk)
+static void omap_dpll_init(MemoryRegion *memory, struct dpll_ctl_s *s,
+ target_phys_addr_t base, omap_clk clk)
{
- int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
- omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
s->dpll = clk;
omap_dpll_reset(s);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_add_subregion(memory, base, &s->iomem);
}
/* MPU Clock/Reset/Power Mode Control */
-static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* ARM_CKCTL */
return s->clkm.arm_ckctl;
@@ -1579,7 +1623,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
}
static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
@@ -1589,6 +1633,10 @@ static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
};
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* ARM_CKCTL */
diff = s->clkm.arm_ckctl ^ value;
@@ -1655,22 +1703,21 @@ static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
- omap_badwidth_read16,
- omap_clkm_read,
- omap_badwidth_read16,
+static const MemoryRegionOps omap_clkm_ops = {
+ .read = omap_clkm_read,
+ .write = omap_clkm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
- omap_badwidth_write16,
- omap_clkm_write,
- omap_badwidth_write16,
-};
-
-static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
return s->clkm.dsp_idlect1;
@@ -1707,11 +1754,15 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
}
static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
diff = s->clkm.dsp_idlect1 ^ value;
@@ -1738,16 +1789,10 @@ static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
- omap_badwidth_read16,
- omap_clkdsp_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
- omap_badwidth_write16,
- omap_clkdsp_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_clkdsp_ops = {
+ .read = omap_clkdsp_read,
+ .write = omap_clkdsp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_clkm_reset(struct omap_mpu_state_s *s)
@@ -1773,15 +1818,13 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(target_phys_addr_t mpu_base,
+static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
{
- int iomemtype[2] = {
- cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s,
- DEVICE_NATIVE_ENDIAN),
- cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s,
- DEVICE_NATIVE_ENDIAN),
- };
+ memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
+ "omap-clkm", 0x100);
+ memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s,
+ "omap-clkdsp", 0x1000);
s->clkm.arm_idlect1 = 0x03ff;
s->clkm.arm_idlect2 = 0x0100;
@@ -1789,8 +1832,8 @@ static void omap_clkm_init(target_phys_addr_t mpu_base,
omap_clkm_reset(s);
s->clkm.cold_start = 0x3a;
- cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
- cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
+ memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
+ memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
}
/* MPU I/O */
@@ -1800,6 +1843,7 @@ struct omap_mpuio_s {
qemu_irq *in;
qemu_irq handler[16];
qemu_irq wakeup;
+ MemoryRegion iomem;
uint16_t inputs;
uint16_t outputs;
@@ -1854,12 +1898,17 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
s->row_latch = ~rows;
}
-static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* INPUT_LATCH */
return s->inputs;
@@ -1910,13 +1959,17 @@ static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (offset) {
case 0x04: /* OUTPUT_REG */
diff = (s->outputs ^ value) & ~s->dir;
@@ -1982,16 +2035,10 @@ static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
- omap_badwidth_read16,
- omap_mpuio_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
- omap_badwidth_write16,
- omap_mpuio_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_mpuio_ops = {
+ .read = omap_mpuio_read,
+ .write = omap_mpuio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mpuio_reset(struct omap_mpuio_s *s)
@@ -2019,11 +2066,11 @@ static void omap_mpuio_onoff(void *opaque, int line, int on)
omap_mpuio_kbd_update(s);
}
-struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
+struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
+ target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
- int iomemtype;
struct omap_mpuio_s *s = (struct omap_mpuio_s *)
g_malloc0(sizeof(struct omap_mpuio_s));
@@ -2033,9 +2080,9 @@ struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
omap_mpuio_reset(s);
- iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
- omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mpuio_ops, s,
+ "omap-mpuio", 0x800);
+ memory_region_add_subregion(memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
@@ -2069,6 +2116,7 @@ void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
/* MicroWire Interface */
struct omap_uwire_s {
+ MemoryRegion iomem;
qemu_irq txirq;
qemu_irq rxirq;
qemu_irq txdrq;
@@ -2106,11 +2154,16 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
}
}
-static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* RDR */
s->control &= ~(1 << 15); /* RDRB */
@@ -2136,11 +2189,15 @@ static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
}
static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* TDR */
s->txbuf = value; /* TD */
@@ -2184,16 +2241,10 @@ static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_uwire_readfn[] = {
- omap_badwidth_read16,
- omap_uwire_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_uwire_writefn[] = {
- omap_badwidth_write16,
- omap_uwire_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_uwire_ops = {
+ .read = omap_uwire_read,
+ .write = omap_uwire_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_uwire_reset(struct omap_uwire_s *s)
@@ -2206,10 +2257,10 @@ static void omap_uwire_reset(struct omap_uwire_s *s)
s->setup[4] = 0;
}
-struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
+struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq *irq, qemu_irq dma, omap_clk clk)
{
- int iomemtype;
struct omap_uwire_s *s = (struct omap_uwire_s *)
g_malloc0(sizeof(struct omap_uwire_s));
@@ -2218,9 +2269,8 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
s->txdrq = dma;
omap_uwire_reset(s);
- iomemtype = cpu_register_io_memory(omap_uwire_readfn,
- omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_uwire_ops, s, "omap-uwire", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
@@ -2247,11 +2297,16 @@ static void omap_pwl_update(struct omap_mpu_state_s *s)
}
}
-static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* PWL_LEVEL */
return s->pwl.level;
@@ -2263,11 +2318,15 @@ static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
}
static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* PWL_LEVEL */
s->pwl.level = value;
@@ -2283,16 +2342,10 @@ static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_pwl_readfn[] = {
- omap_pwl_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_pwl_writefn[] = {
- omap_pwl_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_pwl_ops = {
+ .read = omap_pwl_read,
+ .write = omap_pwl_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pwl_reset(struct omap_mpu_state_s *s)
@@ -2312,26 +2365,30 @@ static void omap_pwl_clk_update(void *opaque, int line, int on)
omap_pwl_update(s);
}
-static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
+static void omap_pwl_init(MemoryRegion *system_memory,
+ target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_clk clk)
{
- int iomemtype;
-
omap_pwl_reset(s);
- iomemtype = cpu_register_io_memory(omap_pwl_readfn,
- omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->pwl_iomem, &omap_pwl_ops, s,
+ "omap-pwl", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->pwl_iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
}
/* Pulse-Width Tone module */
-static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* FRC */
return s->pwt.frc;
@@ -2345,11 +2402,15 @@ static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
}
static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* FRC */
s->pwt.frc = value & 0x3f;
@@ -2387,16 +2448,10 @@ static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_pwt_readfn[] = {
- omap_pwt_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_pwt_writefn[] = {
- omap_pwt_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_pwt_ops = {
+ .read =omap_pwt_read,
+ .write = omap_pwt_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pwt_reset(struct omap_mpu_state_s *s)
@@ -2406,21 +2461,21 @@ static void omap_pwt_reset(struct omap_mpu_state_s *s)
s->pwt.gcr = 0;
}
-static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
+static void omap_pwt_init(MemoryRegion *system_memory,
+ target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_clk clk)
{
- int iomemtype;
-
s->pwt.clk = clk;
omap_pwt_reset(s);
- iomemtype = cpu_register_io_memory(omap_pwt_readfn,
- omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->pwt_iomem, &omap_pwt_ops, s,
+ "omap-pwt", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->pwt_iomem);
}
/* Real-time Clock module */
struct omap_rtc_s {
+ MemoryRegion iomem;
qemu_irq irq;
qemu_irq alarm;
QEMUTimer *clk;
@@ -2453,12 +2508,17 @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
printf("%s: conversion failed\n", __FUNCTION__);
}
-static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint8_t i;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* SECONDS_REG */
return to_bcd(s->current_tm.tm_sec);
@@ -2531,13 +2591,17 @@ static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
}
static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
struct tm new_tm;
time_t ti[2];
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* SECONDS_REG */
#ifdef ALMDEBUG
@@ -2718,16 +2782,10 @@ static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_rtc_readfn[] = {
- omap_rtc_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_rtc_writefn[] = {
- omap_rtc_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_rtc_ops = {
+ .read = omap_rtc_read,
+ .write = omap_rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_rtc_tick(void *opaque)
@@ -2814,10 +2872,10 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
omap_rtc_tick(s);
}
-static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
+static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq *irq, omap_clk clk)
{
- int iomemtype;
struct omap_rtc_s *s = (struct omap_rtc_s *)
g_malloc0(sizeof(struct omap_rtc_s));
@@ -2827,15 +2885,16 @@ static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
omap_rtc_reset(s);
- iomemtype = cpu_register_io_memory(omap_rtc_readfn,
- omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_rtc_ops, s,
+ "omap-rtc", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
/* Multi-channel Buffered Serial Port interfaces */
struct omap_mcbsp_s {
+ MemoryRegion iomem;
qemu_irq txirq;
qemu_irq rxirq;
qemu_irq txdrq;
@@ -3041,12 +3100,17 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
omap_mcbsp_rx_stop(s);
}
-static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* DRR2 */
if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
@@ -3303,16 +3367,20 @@ static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
omap_badwidth_write16(opaque, addr, value);
}
-static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = {
- omap_badwidth_read16,
- omap_mcbsp_read,
- omap_badwidth_read16,
-};
+static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
+{
+ switch (size) {
+ case 2: return omap_mcbsp_writeh(opaque, addr, value);
+ case 4: return omap_mcbsp_writew(opaque, addr, value);
+ default: return omap_badwidth_write16(opaque, addr, value);
+ }
+}
-static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = {
- omap_badwidth_write16,
- omap_mcbsp_writeh,
- omap_mcbsp_writew,
+static const MemoryRegionOps omap_mcbsp_ops = {
+ .read = omap_mcbsp_read,
+ .write = omap_mcbsp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
@@ -3334,10 +3402,10 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
qemu_del_timer(s->sink_timer);
}
-struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
+struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk)
{
- int iomemtype;
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
g_malloc0(sizeof(struct omap_mcbsp_s));
@@ -3349,9 +3417,8 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s);
- iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
- omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
@@ -3385,6 +3452,7 @@ void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
/* LED Pulse Generators */
struct omap_lpg_s {
+ MemoryRegion iomem;
QEMUTimer *tm;
uint8_t control;
@@ -3449,11 +3517,16 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
omap_lpg_update(s);
}
-static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_read8(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* LCR */
return s->control;
@@ -3467,11 +3540,15 @@ static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
}
static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* LCR */
if (~value & (1 << 6)) /* LPGRES */
@@ -3491,16 +3568,10 @@ static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
- omap_lpg_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
- omap_lpg_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_lpg_ops = {
+ .read = omap_lpg_read,
+ .write = omap_lpg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_lpg_clk_update(void *opaque, int line, int on)
@@ -3511,9 +3582,9 @@ static void omap_lpg_clk_update(void *opaque, int line, int on)
omap_lpg_update(s);
}
-static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
+static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
+ target_phys_addr_t base, omap_clk clk)
{
- int iomemtype;
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
@@ -3521,9 +3592,8 @@ static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
omap_lpg_reset(s);
- iomemtype = cpu_register_io_memory(omap_lpg_readfn,
- omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
@@ -3531,8 +3601,13 @@ static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
}
/* MPUI Peripheral Bridge configuration */
-static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
if (addr == OMAP_MPUI_BASE) /* CMR */
return 0xfe4d;
@@ -3540,23 +3615,26 @@ static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
return 0;
}
-static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
- omap_badwidth_read16,
- omap_mpui_io_read,
- omap_badwidth_read16,
-};
+static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
+{
+ /* FIXME: infinite loop */
+ omap_badwidth_write16(opaque, addr, value);
+}
-static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
- omap_badwidth_write16,
- omap_badwidth_write16,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_mpui_io_ops = {
+ .read = omap_mpui_io_read,
+ .write = omap_mpui_io_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
+static void omap_setup_mpui_io(MemoryRegion *system_memory,
+ struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
- omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
+ memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu,
+ "omap-mpui-io", 0x7fff);
+ memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
+ &mpu->mpui_io_iomem);
}
/* General chip reset */
@@ -3630,14 +3708,16 @@ static const struct omap_map_s {
{ 0 }
};
-static void omap_setup_dsp_mapping(const struct omap_map_s *map)
+static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
+ const struct omap_map_s *map)
{
- int io;
+ MemoryRegion *io;
for (; map->phys_dsp; map ++) {
- io = cpu_get_physical_page_desc(map->phys_mpu);
-
- cpu_register_physical_memory(map->phys_dsp, map->size, io);
+ io = g_new(MemoryRegion, 1);
+ memory_region_init_alias(io, map->name,
+ system_memory, map->phys_mpu, map->size);
+ memory_region_add_subregion(system_memory, map->phys_dsp, io);
}
}
@@ -3706,13 +3786,13 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
-struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
+ unsigned long sdram_size,
const char *core)
{
int i;
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
g_malloc0(sizeof(struct omap_mpu_state_s));
- ram_addr_t imif_base, emiff_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
@@ -3736,14 +3816,12 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
omap_clk_init(s);
/* Memory-mapped stuff */
- cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
- (emiff_base = qemu_ram_alloc(NULL, "omap1.dram",
- s->sdram_size)) | IO_MEM_RAM);
- cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
- (imif_base = qemu_ram_alloc(NULL, "omap1.sram",
- s->sram_size)) | IO_MEM_RAM);
+ memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size);
+ memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
+ memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size);
+ memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
- omap_clkm_init(0xfffece00, 0xe1008000, s);
+ omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
cpu_irq = arm_pic_init_cpu(s->env);
s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
@@ -3767,47 +3845,46 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
/* Register SDRAM and SRAM DMA ports for fast transfers. */
- soc_dma_port_add_mem_ram(s->dma,
- emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
- soc_dma_port_add_mem_ram(s->dma,
- imif_base, OMAP_IMIF_BASE, s->sram_size);
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram),
+ OMAP_EMIFF_BASE, s->sdram_size);
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
+ OMAP_IMIF_BASE, s->sram_size);
- s->timer[0] = omap_mpu_timer_init(0xfffec500,
+ s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
s->irq[0][OMAP_INT_TIMER1],
omap_findclk(s, "mputim_ck"));
- s->timer[1] = omap_mpu_timer_init(0xfffec600,
+ s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
s->irq[0][OMAP_INT_TIMER2],
omap_findclk(s, "mputim_ck"));
- s->timer[2] = omap_mpu_timer_init(0xfffec700,
+ s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
s->irq[0][OMAP_INT_TIMER3],
omap_findclk(s, "mputim_ck"));
- s->wdt = omap_wd_timer_init(0xfffec800,
+ s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
s->irq[0][OMAP_INT_WD_TIMER],
omap_findclk(s, "armwdt_ck"));
- s->os_timer = omap_os_timer_init(0xfffb9000,
+ s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
s->irq[1][OMAP_INT_OS_TIMER],
omap_findclk(s, "clk32-kHz"));
s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
- omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
- omap_findclk(s, "lcd_ck"));
+ omap_dma_get_lcdch(s->dma), omap_findclk(s, "lcd_ck"));
- omap_ulpd_pm_init(0xfffe0800, s);
- omap_pin_cfg_init(0xfffe1000, s);
- omap_id_init(s);
+ omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
+ omap_pin_cfg_init(system_memory, 0xfffe1000, s);
+ omap_id_init(system_memory, s);
- omap_mpui_init(0xfffec900, s);
+ omap_mpui_init(system_memory, 0xfffec900, s);
- s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
+ s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
s->irq[0][OMAP_INT_BRIDGE_PRIV],
omap_findclk(s, "tipb_ck"));
- s->public_tipb = omap_tipb_bridge_init(0xfffed300,
+ s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
s->irq[0][OMAP_INT_BRIDGE_PUB],
omap_findclk(s, "tipb_ck"));
- omap_tcmi_init(0xfffecc00, s);
+ omap_tcmi_init(system_memory, 0xfffecc00, s);
s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
omap_findclk(s, "uart1_ck"),
@@ -3828,9 +3905,12 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
"uart3",
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
- omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
- omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
- omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
+ omap_dpll_init(system_memory,
+ &s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
+ omap_dpll_init(system_memory,
+ &s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
+ omap_dpll_init(system_memory,
+ &s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
dinfo = drive_get(IF_SD, 0, 0);
if (!dinfo) {
@@ -3841,7 +3921,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
omap_findclk(s, "mmc_ck"));
- s->mpuio = omap_mpuio_init(0xfffb5000,
+ s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
s->wakeup, omap_findclk(s, "clk32-kHz"));
@@ -3852,27 +3932,34 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
s->irq[0][OMAP_INT_GPIO_BANK1]);
sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000);
- s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
+ s->microwire = omap_uwire_init(system_memory,
+ 0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
- omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
- omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
+ omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck"));
+ omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck"));
s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
- s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
+ s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
+ &s->irq[1][OMAP_INT_RTC_TIMER],
omap_findclk(s, "clk32-kHz"));
- s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
+ s->mcbsp1 = omap_mcbsp_init(system_memory,
+ 0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
&s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
- s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
+ s->mcbsp2 = omap_mcbsp_init(system_memory,
+ 0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
&s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
- s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
+ s->mcbsp3 = omap_mcbsp_init(system_memory,
+ 0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
&s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
- s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
- s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
+ s->led[0] = omap_lpg_init(system_memory,
+ 0xfffbd000, omap_findclk(s, "clk32-kHz"));
+ s->led[1] = omap_lpg_init(system_memory,
+ 0xfffbd800, omap_findclk(s, "clk32-kHz"));
/* Register mappings not currenlty implemented:
* MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
@@ -3889,8 +3976,8 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
* DSP MMU fffed200 - fffed2ff
*/
- omap_setup_dsp_mapping(omap15xx_dsp_mm);
- omap_setup_mpui_io(s);
+ omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm);
+ omap_setup_mpui_io(system_memory, s);
qemu_register_reset(omap1_mpu_reset, s);
diff --git a/hw/omap2.c b/hw/omap2.c
index ca088d9f53..3d529cefd6 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -2284,8 +2284,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
s->port->addr_valid = omap2_validate_addr;
/* Register SDRAM and SRAM ports for fast DMA transfers. */
- soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
- soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
+ soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(q2_base),
+ OMAP2_Q2_BASE, s->sdram_size);
+ soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(sram_base),
+ OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
s->irq[0][OMAP_INT_24XX_UART1_IRQ],
diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
index a9054227e2..29e604863d 100644
--- a/hw/omap_lcdc.c
+++ b/hw/omap_lcdc.c
@@ -24,8 +24,6 @@
struct omap_lcd_panel_s {
qemu_irq irq;
DisplayState *state;
- ram_addr_t imif_base;
- ram_addr_t emiff_base;
int plm;
int tft;
@@ -436,8 +434,7 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
}
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
- struct omap_dma_lcd_channel_s *dma,
- ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
+ struct omap_dma_lcd_channel_s *dma, omap_clk clk)
{
int iomemtype;
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
@@ -445,8 +442,6 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
s->irq = irq;
s->dma = dma;
- s->imif_base = imif_base;
- s->emiff_base = emiff_base;
omap_lcdc_reset(s);
iomemtype = cpu_register_io_memory(omap_lcdc_readfn,
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index 15cfbb52f3..fe535459df 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -32,6 +32,7 @@
#include "arm-misc.h"
#include "flash.h"
#include "blockdev.h"
+#include "exec-memory.h"
/*****************************************************************************/
/* Siemens SX1 Cellphone V1 */
@@ -121,6 +122,7 @@ static void sx1_init(ram_addr_t ram_size,
const int version)
{
struct omap_mpu_state_s *cpu;
+ MemoryRegion *address_space = get_system_memory();
int io;
static uint32_t cs0val = 0x00213090;
static uint32_t cs1val = 0x00215070;
@@ -135,7 +137,7 @@ static void sx1_init(ram_addr_t ram_size,
flash_size = flash2_size;
}
- cpu = omap310_mpu_init(sx1_binfo.ram_size, cpu_model);
+ cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
diff --git a/hw/palm.c b/hw/palm.c
index 4c67e75c83..d8f50e3413 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -25,6 +25,7 @@
#include "arm-misc.h"
#include "devices.h"
#include "loader.h"
+#include "exec-memory.h"
static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{
@@ -198,6 +199,7 @@ static void palmte_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
+ MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *cpu;
int flash_size = 0x00800000;
int sdram_size = palmte_binfo.ram_size;
@@ -209,7 +211,7 @@ static void palmte_init(ram_addr_t ram_size,
int rom_size, rom_loaded = 0;
DisplayState *ds = get_displaystate();
- cpu = omap310_mpu_init(sdram_size, cpu_model);
+ cpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
diff --git a/hw/soc_dma.h b/hw/soc_dma.h
index c0ebb8d715..904b26c5a8 100644
--- a/hw/soc_dma.h
+++ b/hw/soc_dma.h
@@ -18,6 +18,8 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "memory.h"
+
struct soc_dma_s;
struct soc_dma_ch_s;
typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
@@ -105,9 +107,3 @@ static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
}
-
-static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma,
- ram_addr_t offset, target_phys_addr_t virt_base, size_t size)
-{
- return soc_dma_port_add_mem(dma, qemu_get_ram_ptr(offset), virt_base, size);
-}
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-22 09:29:12 +0000