diff options
Diffstat (limited to 'hw')
87 files changed, 962 insertions, 938 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c index 163822617b..6ee2068128 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -31,7 +31,6 @@ #include "pci_host.h" #include "pci_bridge.h" #include "pci_internals.h" -#include "rwhandler.h" #include "apb_pci.h" #include "sysemu.h" #include "exec-memory.h" @@ -70,7 +69,9 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) typedef struct APBState { SysBusDevice busdev; PCIBus *bus; - ReadWriteHandler pci_config_handler; + MemoryRegion apb_config; + MemoryRegion pci_config; + MemoryRegion pci_ioport; uint32_t iommu[4]; uint32_t pci_control[16]; uint32_t pci_irq_map[8]; @@ -81,7 +82,7 @@ typedef struct APBState { } APBState; static void apb_config_writel (void *opaque, target_phys_addr_t addr, - uint32_t val) + uint64_t val, unsigned size) { APBState *s = opaque; @@ -128,8 +129,8 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr, } } -static uint32_t apb_config_readl (void *opaque, - target_phys_addr_t addr) +static uint64_t apb_config_readl (void *opaque, + target_phys_addr_t addr, unsigned size) { APBState *s = opaque; uint32_t val; @@ -176,33 +177,27 @@ static uint32_t apb_config_readl (void *opaque, return val; } -static CPUWriteMemoryFunc * const apb_config_write[] = { - &apb_config_writel, - &apb_config_writel, - &apb_config_writel, +static const MemoryRegionOps apb_config_ops = { + .read = apb_config_readl, + .write = apb_config_writel, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUReadMemoryFunc * const apb_config_read[] = { - &apb_config_readl, - &apb_config_readl, - &apb_config_readl, -}; - -static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr, - uint32_t val, int size) +static void apb_pci_config_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { - APBState *s = container_of(h, APBState, pci_config_handler); + APBState *s = opaque; val = qemu_bswap_len(val, size); APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val); pci_data_write(s->bus, addr, val, size); } -static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr, - int size) +static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr, + unsigned size) { uint32_t ret; - APBState *s = container_of(h, APBState, pci_config_handler); + APBState *s = opaque; ret = pci_data_read(s->bus, addr, size); ret = qemu_bswap_len(ret, size); @@ -252,16 +247,12 @@ static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) return val; } -static CPUWriteMemoryFunc * const pci_apb_iowrite[] = { - &pci_apb_iowriteb, - &pci_apb_iowritew, - &pci_apb_iowritel, -}; - -static CPUReadMemoryFunc * const pci_apb_ioread[] = { - &pci_apb_ioreadb, - &pci_apb_ioreadw, - &pci_apb_ioreadl, +static const MemoryRegionOps pci_ioport_ops = { + .old_mmio = { + .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl }, + .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* The APB host has an IRQ line for each IRQ line of each slot. */ @@ -393,10 +384,15 @@ static void pci_pbm_reset(DeviceState *d) } } +static const MemoryRegionOps pci_config_ops = { + .read = apb_pci_config_read, + .write = apb_pci_config_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + static int pci_pbm_init_device(SysBusDevice *dev) { APBState *s; - int pci_config, apb_config, pci_ioport; unsigned int i; s = FROM_SYSBUS(APBState, dev); @@ -408,27 +404,21 @@ static int pci_pbm_init_device(SysBusDevice *dev) } /* apb_config */ - apb_config = cpu_register_io_memory(apb_config_read, - apb_config_write, s, - DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config", + 0x10000); /* at region 0 */ - sysbus_init_mmio(dev, 0x10000ULL, apb_config); + sysbus_init_mmio_region(dev, &s->apb_config); - /* PCI configuration space */ - s->pci_config_handler.read = apb_pci_config_read; - s->pci_config_handler.write = apb_pci_config_write; - pci_config = cpu_register_io_memory_simple(&s->pci_config_handler, - DEVICE_NATIVE_ENDIAN); - assert(pci_config >= 0); + memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config", + 0x1000000); /* at region 1 */ - sysbus_init_mmio(dev, 0x1000000ULL, pci_config); + sysbus_init_mmio_region(dev, &s->pci_config); /* pci_ioport */ - pci_ioport = cpu_register_io_memory(pci_apb_ioread, - pci_apb_iowrite, s, - DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s, + "apb-pci-ioport", 0x10000); /* at region 2 */ - sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); + sysbus_init_mmio_region(dev, &s->pci_ioport); return 0; } @@ -80,6 +80,7 @@ typedef struct APICState APICState; struct APICState { SysBusDevice busdev; + MemoryRegion io_memory; void *cpu_env; uint32_t apicbase; uint8_t id; @@ -222,8 +223,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level) } static void apic_bus_deliver(const uint32_t *deliver_bitmask, - uint8_t delivery_mode, - uint8_t vector_num, uint8_t polarity, + uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) { APICState *apic_iter; @@ -280,18 +280,16 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask, apic_set_irq(apic_iter, vector_num, trigger_mode) ); } -void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, - uint8_t delivery_mode, uint8_t vector_num, - uint8_t polarity, uint8_t trigger_mode) +void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, + uint8_t vector_num, uint8_t trigger_mode) { uint32_t deliver_bitmask[MAX_APIC_WORDS]; trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, - polarity, trigger_mode); + trigger_mode); apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); - apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, - trigger_mode); + apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); } void cpu_set_apic_base(DeviceState *d, uint64_t val) @@ -548,7 +546,7 @@ void apic_sipi(DeviceState *d) static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, - uint8_t polarity, uint8_t trigger_mode) + uint8_t trigger_mode) { APICState *s = DO_UPCAST(APICState, busdev.qdev, d); uint32_t deliver_bitmask[MAX_APIC_WORDS]; @@ -591,8 +589,7 @@ static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, return; } - apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, - trigger_mode); + apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); } int apic_get_interrupt(DeviceState *d) @@ -794,7 +791,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32_t data) uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; /* XXX: Ignore redirection hint. */ - apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode); + apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) @@ -855,7 +852,7 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) s->icr[0] = val; apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), - (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); + (s->icr[0] >> 15) & 1); break; case 0x31: s->icr[1] = val; @@ -979,31 +976,25 @@ static void apic_reset(DeviceState *d) } } -static CPUReadMemoryFunc * const apic_mem_read[3] = { - apic_mem_readb, - apic_mem_readw, - apic_mem_readl, -}; - -static CPUWriteMemoryFunc * const apic_mem_write[3] = { - apic_mem_writeb, - apic_mem_writew, - apic_mem_writel, +static const MemoryRegionOps apic_io_ops = { + .old_mmio = { + .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, + .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int apic_init1(SysBusDevice *dev) { APICState *s = FROM_SYSBUS(APICState, dev); - int apic_io_memory; static int last_apic_idx; if (last_apic_idx >= MAX_APICS) { return -1; } - apic_io_memory = cpu_register_io_memory(apic_mem_read, - apic_mem_write, NULL, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory); + memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic", + MSI_ADDR_SIZE); + sysbus_init_mmio_region(dev, &s->io_memory); s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); s->idx = last_apic_idx++; @@ -4,10 +4,8 @@ #include "qemu-common.h" /* apic.c */ -void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, - uint8_t delivery_mode, - uint8_t vector_num, uint8_t polarity, - uint8_t trigger_mode); +void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, + uint8_t vector_num, uint8_t trigger_mode); int apic_accept_pic_intr(DeviceState *s); void apic_deliver_pic_intr(DeviceState *s, int level); int apic_get_interrupt(DeviceState *s); diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index b47707f7bb..7d60ef6ba8 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -54,6 +54,11 @@ static void mpcore_rirq_map(SysBusDevice *dev, target_phys_addr_t base) sysbus_mmio_map(s->priv, 0, base); } +static void mpcore_rirq_unmap(SysBusDevice *dev, target_phys_addr_t base) +{ + /* nothing to do */ +} + static int realview_mpcore_init(SysBusDevice *dev) { mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); @@ -79,7 +84,7 @@ static int realview_mpcore_init(SysBusDevice *dev) } } qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); - sysbus_init_mmio_cb(dev, 0x2000, mpcore_rirq_map); + sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap); return 0; } diff --git a/hw/arm_gic.c b/hw/arm_gic.c index fb07314d52..83213dd406 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -104,7 +104,7 @@ typedef struct gic_state int num_cpu; #endif - int iomemtype; + MemoryRegion iomem; } gic_state; /* TODO: Many places that call this routine could be optimized. */ @@ -567,16 +567,12 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset, gic_dist_writew(opaque, offset + 2, value >> 16); } -static CPUReadMemoryFunc * const gic_dist_readfn[] = { - gic_dist_readb, - gic_dist_readw, - gic_dist_readl -}; - -static CPUWriteMemoryFunc * const gic_dist_writefn[] = { - gic_dist_writeb, - gic_dist_writew, - gic_dist_writel +static const MemoryRegionOps gic_dist_ops = { + .old_mmio = { + .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, + .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; #ifndef NVIC @@ -741,9 +737,7 @@ static void gic_init(gic_state *s) for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(&s->busdev, &s->parent_irq[i]); } - s->iomemtype = cpu_register_io_memory(gic_dist_readfn, - gic_dist_writefn, s, - DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); gic_reset(s); register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s); } diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c index 22c62dfebb..17cf6f72ad 100644 --- a/hw/arm_sysctl.c +++ b/hw/arm_sysctl.c @@ -17,6 +17,7 @@ typedef struct { SysBusDevice busdev; + MemoryRegion iomem; qemu_irq pl110_mux_ctrl; uint32_t sys_id; @@ -91,7 +92,8 @@ static void arm_sysctl_reset(DeviceState *d) } } -static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) +static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset, + unsigned size) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; @@ -188,7 +190,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) } static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, - uint32_t val) + uint64_t val, unsigned size) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; @@ -327,16 +329,10 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, } } -static CPUReadMemoryFunc * const arm_sysctl_readfn[] = { - arm_sysctl_read, - arm_sysctl_read, - arm_sysctl_read -}; - -static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = { - arm_sysctl_write, - arm_sysctl_write, - arm_sysctl_write +static const MemoryRegionOps arm_sysctl_ops = { + .read = arm_sysctl_read, + .write = arm_sysctl_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void arm_sysctl_gpio_set(void *opaque, int line, int level) @@ -370,12 +366,9 @@ static void arm_sysctl_gpio_set(void *opaque, int line, int level) static int arm_sysctl_init1(SysBusDevice *dev) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); - int iomemtype; - iomemtype = cpu_register_io_memory(arm_sysctl_readfn, - arm_sysctl_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2); qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1); return 0; diff --git a/hw/arm_timer.c b/hw/arm_timer.c index f2832f9c31..09a4b247bd 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -176,6 +176,7 @@ static arm_timer_state *arm_timer_init(uint32_t freq) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; arm_timer_state *timer[2]; int level[2]; qemu_irq irq; @@ -190,7 +191,8 @@ static void sp804_set_irq(void *opaque, int irq, int level) qemu_set_irq(s->irq, s->level[0] || s->level[1]); } -static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) +static uint64_t sp804_read(void *opaque, target_phys_addr_t offset, + unsigned size) { sp804_state *s = (sp804_state *)opaque; @@ -203,7 +205,7 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) } static void sp804_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { sp804_state *s = (sp804_state *)opaque; @@ -214,19 +216,12 @@ static void sp804_write(void *opaque, target_phys_addr_t offset, } } -static CPUReadMemoryFunc * const sp804_readfn[] = { - sp804_read, - sp804_read, - sp804_read +static const MemoryRegionOps sp804_ops = { + .read = sp804_read, + .write = sp804_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const sp804_writefn[] = { - sp804_write, - sp804_write, - sp804_write -}; - - static const VMStateDescription vmstate_sp804 = { .name = "sp804", .version_id = 1, @@ -240,7 +235,6 @@ static const VMStateDescription vmstate_sp804 = { static int sp804_init(SysBusDevice *dev) { - int iomemtype; sp804_state *s = FROM_SYSBUS(sp804_state, dev); qemu_irq *qi; @@ -252,9 +246,8 @@ static int sp804_init(SysBusDevice *dev) s->timer[1] = arm_timer_init(1000000); s->timer[0]->irq = qi[0]; s->timer[1]->irq = qi[1]; - iomemtype = cpu_register_io_memory(sp804_readfn, - sp804_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); vmstate_register(&dev->qdev, -1, &vmstate_sp804, s); return 0; } @@ -264,10 +257,12 @@ static int sp804_init(SysBusDevice *dev) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; arm_timer_state *timer[3]; } icp_pit_state; -static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) +static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset, + unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; @@ -282,7 +277,7 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) } static void icp_pit_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; @@ -295,22 +290,14 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset, arm_timer_write(s->timer[n], offset & 0xff, value); } - -static CPUReadMemoryFunc * const icp_pit_readfn[] = { - icp_pit_read, - icp_pit_read, - icp_pit_read -}; - -static CPUWriteMemoryFunc * const icp_pit_writefn[] = { - icp_pit_write, - icp_pit_write, - icp_pit_write +static const MemoryRegionOps icp_pit_ops = { + .read = icp_pit_read, + .write = icp_pit_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int icp_pit_init(SysBusDevice *dev) { - int iomemtype; icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); /* Timer 0 runs at the system clock speed (40MHz). */ @@ -323,10 +310,8 @@ static int icp_pit_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->timer[1]->irq); sysbus_init_irq(dev, &s->timer[2]->irq); - iomemtype = cpu_register_io_memory(icp_pit_readfn, - icp_pit_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); /* This device has no state to save/restore. The component timers will save themselves. */ return 0; diff --git a/hw/armv7m.c b/hw/armv7m.c index 83f3393eab..a932f16a44 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -106,31 +106,27 @@ static void bitband_writel(void *opaque, target_phys_addr_t offset, cpu_physical_memory_write(addr, (uint8_t *)&v, 4); } -static CPUReadMemoryFunc * const bitband_readfn[] = { - bitband_readb, - bitband_readw, - bitband_readl -}; - -static CPUWriteMemoryFunc * const bitband_writefn[] = { - bitband_writeb, - bitband_writew, - bitband_writel +static const MemoryRegionOps bitband_ops = { + .old_mmio = { + .read = { bitband_readb, bitband_readw, bitband_readl, }, + .write = { bitband_writeb, bitband_writew, bitband_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; typedef struct { SysBusDevice busdev; + MemoryRegion iomem; uint32_t base; } BitBandState; static int bitband_init(SysBusDevice *dev) { BitBandState *s = FROM_SYSBUS(BitBandState, dev); - int iomemtype; - iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn, - &s->base, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x02000000, iomemtype); + memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband", + 0x02000000); + sysbus_init_mmio_region(dev, &s->iomem); return 0; } diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 1df8d4db45..bf8c3c50dc 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -13,6 +13,7 @@ #include "sysbus.h" #include "qemu-timer.h" #include "arm-misc.h" +#include "exec-memory.h" /* 32 internal lines (16 used for system exceptions) plus 64 external interrupt lines. */ @@ -384,7 +385,7 @@ static int armv7m_nvic_init(SysBusDevice *dev) nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev); gic_init(&s->gic); - cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype); + memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem); s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s); vmstate_register(&dev->qdev, -1, &vmstate_nvic, s); return 0; @@ -223,7 +223,7 @@ static void baum_accept_input(struct CharDriverState *chr) if (!baum->out_buf_used) return; - room = qemu_chr_can_read(chr); + room = qemu_chr_be_can_write(chr); if (!room) return; if (room > baum->out_buf_used) @@ -231,12 +231,12 @@ static void baum_accept_input(struct CharDriverState *chr) first = BUF_SIZE - baum->out_buf_ptr; if (room > first) { - qemu_chr_read(chr, baum->out_buf + baum->out_buf_ptr, first); + qemu_chr_be_write(chr, baum->out_buf + baum->out_buf_ptr, first); baum->out_buf_ptr = 0; baum->out_buf_used -= first; room -= first; } - qemu_chr_read(chr, baum->out_buf + baum->out_buf_ptr, room); + qemu_chr_be_write(chr, baum->out_buf + baum->out_buf_ptr, room); baum->out_buf_ptr += room; baum->out_buf_used -= room; } @@ -250,16 +250,16 @@ static void baum_write_packet(BaumDriverState *baum, const uint8_t *buf, int len while (len--) if ((*cur++ = *buf++) == ESC) *cur++ = ESC; - room = qemu_chr_can_read(baum->chr); + room = qemu_chr_be_can_write(baum->chr); len = cur - io_buf; if (len <= room) { /* Fits */ - qemu_chr_read(baum->chr, io_buf, len); + qemu_chr_be_write(baum->chr, io_buf, len); } else { int first; uint8_t out; /* Can't fit all, send what can be, and store the rest. */ - qemu_chr_read(baum->chr, io_buf, room); + qemu_chr_be_write(baum->chr, io_buf, room); len -= room; cur = io_buf + room; if (len > BUF_SIZE - baum->out_buf_used) { @@ -468,20 +468,6 @@ static int baum_write(CharDriverState *chr, const uint8_t *buf, int len) return orig_len; } -/* The other end sent us some event */ -static void baum_send_event(CharDriverState *chr, int event) -{ - BaumDriverState *baum = chr->opaque; - switch (event) { - case CHR_EVENT_BREAK: - break; - case CHR_EVENT_OPENED: - /* Reset state */ - baum->in_buf_used = 0; - break; - } -} - /* Send the key code to the other end */ static void baum_send_key(BaumDriverState *baum, uint8_t type, uint8_t value) { uint8_t packet[] = { type, value }; @@ -591,7 +577,6 @@ int chr_baum_init(QemuOpts *opts, CharDriverState **_chr) chr->opaque = baum; chr->chr_write = baum_write; - chr->chr_send_event = baum_send_event; chr->chr_accept_input = baum_accept_input; chr->chr_close = baum_close; diff --git a/hw/ccid-card-passthru.c b/hw/ccid-card-passthru.c index 28eb9d18f8..2cbc81b9f4 100644 --- a/hw/ccid-card-passthru.c +++ b/hw/ccid-card-passthru.c @@ -72,8 +72,8 @@ static void ccid_card_vscard_send_msg(PassthruState *s, scr_msg_header.type = htonl(type); scr_msg_header.reader_id = htonl(reader_id); scr_msg_header.length = htonl(length); - qemu_chr_write(s->cs, (uint8_t *)&scr_msg_header, sizeof(VSCMsgHeader)); - qemu_chr_write(s->cs, payload, length); + qemu_chr_fe_write(s->cs, (uint8_t *)&scr_msg_header, sizeof(VSCMsgHeader)); + qemu_chr_fe_write(s->cs, payload, length); } static void ccid_card_vscard_send_apdu(PassthruState *s, @@ -198,7 +198,7 @@ static void ccid_card_vscard_handle_message(PassthruState *card, static void ccid_card_vscard_drop_connection(PassthruState *card) { - qemu_chr_close(card->cs); + qemu_chr_delete(card->cs); card->vscard_in_pos = card->vscard_in_hdr = 0; } diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index 0f911127c5..4d0ef0d54c 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -32,7 +32,6 @@ #include "console.h" #include "vga_int.h" #include "loader.h" -#include "exec-memory.h" /* * TODO: @@ -2801,7 +2800,8 @@ static const MemoryRegionOps cirrus_linear_io_ops = { }, }; -static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) +static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci, + MemoryRegion *system_memory) { int i; static int inited; @@ -2854,7 +2854,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s, "cirrus-low-memory", 0x20000); memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem); - memory_region_add_subregion_overlap(get_system_memory(), + memory_region_add_subregion_overlap(system_memory, isa_mem_base + 0x000a0000, &s->low_mem_container, 1); @@ -2897,14 +2897,14 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) * ***************************************/ -void isa_cirrus_vga_init(void) +void isa_cirrus_vga_init(MemoryRegion *system_memory) { CirrusVGAState *s; s = g_malloc0(sizeof(CirrusVGAState)); vga_common_init(&s->vga, VGA_RAM_SIZE); - cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0); + cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0, system_memory); s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, s->vga.screen_dump, s->vga.text_update, &s->vga); @@ -2928,7 +2928,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev) /* setup VGA */ vga_common_init(&s->vga, VGA_RAM_SIZE); - cirrus_init_common(s, device_id, 1); + cirrus_init_common(s, device_id, 1, pci_address_space(dev)); s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, s->vga.screen_dump, s->vga.text_update, &s->vga); diff --git a/hw/debugcon.c b/hw/debugcon.c index 5ee6821206..c9ee6d90b0 100644 --- a/hw/debugcon.c +++ b/hw/debugcon.c @@ -51,7 +51,7 @@ static void debugcon_ioport_write(void *opaque, uint32_t addr, uint32_t val) printf("debugcon: write addr=0x%04x val=0x%02x\n", addr, val); #endif - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); } diff --git a/hw/devices.h b/hw/devices.h index c788373c8c..07fda83169 100644 --- a/hw/devices.h +++ b/hw/devices.h @@ -47,13 +47,6 @@ void *tahvo_init(qemu_irq irq, int betty); void retu_key_event(void *retu, int state); -/* tusb6010.c */ -typedef struct TUSBState TUSBState; -TUSBState *tusb6010_init(qemu_irq intr); -int tusb6010_sync_io(TUSBState *s); -int tusb6010_async_io(TUSBState *s); -void tusb6010_power(TUSBState *s, int on); - /* tc6393xb.c */ typedef struct TC6393xbState TC6393xbState; #define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */ diff --git a/hw/e1000.c b/hw/e1000.c index 29b453f7b1..a6d12c55fb 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -617,10 +617,13 @@ e1000_set_link_status(VLANClientState *nc) E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque; uint32_t old_status = s->mac_reg[STATUS]; - if (nc->link_down) + if (nc->link_down) { s->mac_reg[STATUS] &= ~E1000_STATUS_LU; - else + s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS; + } else { s->mac_reg[STATUS] |= E1000_STATUS_LU; + s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS; + } if (s->mac_reg[STATUS] != old_status) set_ics(s, 0, E1000_ICR_LSC); diff --git a/hw/e1000_hw.h b/hw/e1000_hw.h index 9bd8a4bdfd..2e341ac27e 100644 --- a/hw/e1000_hw.h +++ b/hw/e1000_hw.h @@ -349,6 +349,23 @@ #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ +/* PHY Status Register */ +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ + /* Interrupt Cause Read */ #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ @@ -460,7 +460,7 @@ static void escc_update_parameters(ChannelState *s) ssp.data_bits = data_bits; ssp.stop_bits = stop_bits; trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits); - qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); } static void escc_mem_write(void *opaque, target_phys_addr_t addr, @@ -551,7 +551,7 @@ static void escc_mem_write(void *opaque, target_phys_addr_t addr, s->tx = val; if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled if (s->chr) - qemu_chr_write(s->chr, &s->tx, 1); + qemu_chr_fe_write(s->chr, &s->tx, 1); else if (s->type == kbd && !s->disabled) { handle_kbd_command(s, val); } diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c index 28b86ea2d4..00360371e3 100644 --- a/hw/etraxfs_ser.c +++ b/hw/etraxfs_ser.c @@ -119,7 +119,7 @@ ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value) switch (addr) { case RW_DOUT: - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); s->regs[R_INTR] |= 3; s->pending_tx = 1; s->regs[addr] = value; diff --git a/hw/grlib_apbuart.c b/hw/grlib_apbuart.c index 169a56eb1b..c90b810413 100644 --- a/hw/grlib_apbuart.c +++ b/hw/grlib_apbuart.c @@ -114,7 +114,7 @@ grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value) switch (addr) { case DATA_OFFSET: c = value & 0xFF; - qemu_chr_write(uart->chr, &c, 1); + qemu_chr_fe_write(uart->chr, &c, 1); return; case STATUS_OFFSET: diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c index d5415580e4..1c3425372a 100644 --- a/hw/gt64xxx.c +++ b/hw/gt64xxx.c @@ -227,7 +227,7 @@ #define PCI_MAPPING_ENTRY(regname) \ target_phys_addr_t regname ##_start; \ target_phys_addr_t regname ##_length; \ - int regname ##_handle + MemoryRegion regname ##_mem typedef struct GT64120State { SysBusDevice busdev; @@ -269,9 +269,9 @@ static void gt64120_isd_mapping(GT64120State *s) target_phys_addr_t start = s->regs[GT_ISD] << 21; target_phys_addr_t length = 0x1000; - if (s->ISD_length) - cpu_register_physical_memory(s->ISD_start, s->ISD_length, - IO_MEM_UNASSIGNED); + if (s->ISD_length) { + memory_region_del_subregion(get_system_memory(), &s->ISD_mem); + } check_reserved_space(&start, &length); length = 0x1000; /* Map new address */ @@ -279,7 +279,7 @@ static void gt64120_isd_mapping(GT64120State *s) length, start, s->ISD_handle); s->ISD_start = start; s->ISD_length = length; - cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle); + memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); } static void gt64120_pci_mapping(GT64120State *s) @@ -290,18 +290,23 @@ static void gt64120_pci_mapping(GT64120State *s) /* Unmap old IO address */ if (s->PCI0IO_length) { - cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); + memory_region_destroy(&s->PCI0IO_mem); } /* Map new IO address */ s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; isa_mem_base = s->PCI0IO_start; - isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); + if (s->PCI0IO_length) { + isa_mmio_setup(&s->PCI0IO_mem, s->PCI0IO_length); + memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, + &s->PCI0IO_mem); + } } } static void gt64120_writel (void *opaque, target_phys_addr_t addr, - uint32_t val) + uint64_t val, unsigned size) { GT64120State *s = opaque; uint32_t saddr; @@ -579,8 +584,8 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr, } } -static uint32_t gt64120_readl (void *opaque, - target_phys_addr_t addr) +static uint64_t gt64120_readl (void *opaque, + target_phys_addr_t addr, unsigned size) { GT64120State *s = opaque; uint32_t val; @@ -851,16 +856,10 @@ static uint32_t gt64120_readl (void *opaque, return val; } -static CPUWriteMemoryFunc * const gt64120_write[] = { - >64120_writel, - >64120_writel, - >64120_writel, -}; - -static CPUReadMemoryFunc * const gt64120_read[] = { - >64120_readl, - >64120_readl, - >64120_readl, +static const MemoryRegionOps isd_mem_ops = { + .read = gt64120_readl, + .write = gt64120_writel, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) @@ -1097,8 +1096,7 @@ PCIBus *gt64120_register(qemu_irq *pic) get_system_memory(), get_system_io(), PCI_DEVFN(18, 0), 4); - d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d, - DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000); pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci"); return d->pci.bus; diff --git a/hw/ioapic.c b/hw/ioapic.c index 6c26e820e0..61991d7679 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -104,7 +104,6 @@ static void ioapic_service(IOAPICState *s) uint64_t entry; uint8_t dest; uint8_t dest_mode; - uint8_t polarity; for (i = 0; i < IOAPIC_NUM_PINS; i++) { mask = 1 << i; @@ -116,7 +115,6 @@ static void ioapic_service(IOAPICState *s) dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; - polarity = (entry >> IOAPIC_LVT_POLARITY_SHIFT) & 1; if (trig_mode == IOAPIC_TRIGGER_EDGE) { s->irr &= ~mask; } else { @@ -128,7 +126,7 @@ static void ioapic_service(IOAPICState *s) vector = entry & IOAPIC_VECTOR_MASK; } apic_deliver_irq(dest, dest_mode, delivery_mode, - vector, polarity, trig_mode); + vector, trig_mode); } } } @@ -150,6 +148,9 @@ static void ioapic_set_irq(void *opaque, int vector, int level) uint32_t mask = 1 << vector; uint64_t entry = s->ioredtbl[vector]; + if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) { + level = !level; + } if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == IOAPIC_TRIGGER_LEVEL) { /* level triggered */ diff --git a/hw/isa-bus.c b/hw/isa-bus.c index 27655436a0..1cb497f5ca 100644 --- a/hw/isa-bus.c +++ b/hw/isa-bus.c @@ -20,6 +20,7 @@ #include "monitor.h" #include "sysbus.h" #include "isa.h" +#include "exec-memory.h" struct ISABus { BusState qbus; @@ -202,4 +203,9 @@ static char *isabus_get_fw_dev_path(DeviceState *dev) return strdup(path); } +MemoryRegion *isa_address_space(ISADevice *dev) +{ + return get_system_memory(); +} + device_init(isabus_register_devices) @@ -32,6 +32,7 @@ void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq); void isa_init_ioport(ISADevice *dev, uint16_t ioport); void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length); void isa_qdev_register(ISADeviceInfo *info); +MemoryRegion *isa_address_space(ISADevice *dev); ISADevice *isa_create(const char *name); ISADevice *isa_try_create(const char *name); ISADevice *isa_create_simple(const char *name); diff --git a/hw/ivshmem.c b/hw/ivshmem.c index f4ae0d2b95..242fbea3a5 100644 --- a/hw/ivshmem.c +++ b/hw/ivshmem.c @@ -401,7 +401,7 @@ static void ivshmem_read(void *opaque, const uint8_t * buf, int flags) memcpy(&incoming_posn, buf, sizeof(long)); /* pick off s->server_chr->msgfd and store it, posn should accompany msg */ - tmp_fd = qemu_chr_get_msgfd(s->server_chr); + tmp_fd = qemu_chr_fe_get_msgfd(s->server_chr); IVSHMEM_DPRINTF("posn is %ld, fd is %d\n", incoming_posn, tmp_fd); /* make sure we have enough space for this guest */ diff --git a/hw/lm32_juart.c b/hw/lm32_juart.c index fddcf7ea14..5454aa4e4d 100644 --- a/hw/lm32_juart.c +++ b/hw/lm32_juart.c @@ -72,7 +72,7 @@ void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx) s->jtx = jtx; if (s->chr) { - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); } } diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c index 09090e93b2..367854550c 100644 --- a/hw/lm32_uart.c +++ b/hw/lm32_uart.c @@ -169,7 +169,7 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) switch (addr) { case R_RXTX: if (s->chr) { - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); } break; case R_IER: diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c index 6118ccb604..e6b2ab067a 100644 --- a/hw/mcf_uart.c +++ b/hw/mcf_uart.c @@ -110,7 +110,7 @@ static void mcf_uart_do_tx(mcf_uart_state *s) { if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) { if (s->chr) - qemu_chr_write(s->chr, (unsigned char *)&s->tb, 1); + qemu_chr_fe_write(s->chr, (unsigned char *)&s->tb, 1); s->sr |= MCF_UART_TxEMP; } if (s->tx_enabled) { diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c index 7c59382fbe..9ad48b4b95 100644 --- a/hw/microblaze_pic_cpu.c +++ b/hw/microblaze_pic_cpu.c @@ -24,6 +24,7 @@ #include "hw.h" #include "pc.h" +#include "microblaze_pic_cpu.h" #define D(x) @@ -43,7 +44,6 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) cpu_reset_interrupt(env, type); } -qemu_irq *microblaze_pic_init_cpu(CPUState *env); qemu_irq *microblaze_pic_init_cpu(CPUState *env) { return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2); diff --git a/hw/microblaze_pic_cpu.h b/hw/microblaze_pic_cpu.h new file mode 100644 index 0000000000..4c76275976 --- /dev/null +++ b/hw/microblaze_pic_cpu.h @@ -0,0 +1,8 @@ +#ifndef MICROBLAZE_PIC_CPU_H +#define MICROBLAZE_PIC_CPU_H + +#include "qemu-common.h" + +qemu_irq *microblaze_pic_init_cpu(CPUState *env); + +#endif /* MICROBLAZE_PIC_CPU_H */ diff --git a/hw/milkymist-uart.c b/hw/milkymist-uart.c index 56c90da0b6..e8e309de7c 100644 --- a/hw/milkymist-uart.c +++ b/hw/milkymist-uart.c @@ -77,7 +77,7 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) switch (addr) { case R_RXTX: if (s->chr) { - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); } trace_milkymist_uart_pulse_irq_tx(); qemu_irq_pulse(s->tx_irq); diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index ea20510cb4..84ce0613a3 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -38,6 +38,7 @@ #include "mc146818rtc.h" #include "blockdev.h" #include "sysbus.h" +#include "exec-memory.h" enum jazz_model_e { @@ -197,7 +198,7 @@ void mips_jazz_init (ram_addr_t ram_size, g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]); break; case JAZZ_PICA61: - isa_vga_mm_init(0x40000000, 0x60000000, 0); + isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); break; default: break; diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 5bdb45b747..86a8ba07d3 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -92,8 +92,8 @@ static void malta_fpga_update_display(void *opaque) } leds_text[8] = '\0'; - qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text); - qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text); + qemu_chr_fe_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text); + qemu_chr_fe_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text); } /* @@ -417,15 +417,15 @@ static void malta_fpga_reset(void *opaque) static void malta_fpga_led_init(CharDriverState *chr) { - qemu_chr_printf(chr, "\e[HMalta LEDBAR\r\n"); - qemu_chr_printf(chr, "+--------+\r\n"); - qemu_chr_printf(chr, "+ +\r\n"); - qemu_chr_printf(chr, "+--------+\r\n"); - qemu_chr_printf(chr, "\n"); - qemu_chr_printf(chr, "Malta ASCII\r\n"); - qemu_chr_printf(chr, "+--------+\r\n"); - qemu_chr_printf(chr, "+ +\r\n"); - qemu_chr_printf(chr, "+--------+\r\n"); + qemu_chr_fe_printf(chr, "\e[HMalta LEDBAR\r\n"); + qemu_chr_fe_printf(chr, "+--------+\r\n"); + qemu_chr_fe_printf(chr, "+ +\r\n"); + qemu_chr_fe_printf(chr, "+--------+\r\n"); + qemu_chr_fe_printf(chr, "\n"); + qemu_chr_fe_printf(chr, "Malta ASCII\r\n"); + qemu_chr_fe_printf(chr, "+--------+\r\n"); + qemu_chr_fe_printf(chr, "+ +\r\n"); + qemu_chr_fe_printf(chr, "+--------+\r\n"); } static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr) @@ -443,7 +443,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir /* 0xa00 is less than a page, so will still get the right offsets. */ cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta); - s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init); + s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init); #ifdef TARGET_WORDS_BIGENDIAN s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 1); @@ -784,7 +784,7 @@ void mips_malta_init (ram_addr_t ram_size, if (!serial_hds[i]) { char label[32]; snprintf(label, sizeof(label), "serial%d", i); - serial_hds[i] = qemu_chr_open(label, "null", NULL); + serial_hds[i] = qemu_chr_new(label, "null", NULL); } } diff --git a/hw/mpcore.c b/hw/mpcore.c index d778507516..d6175cfc2d 100644 --- a/hw/mpcore.c +++ b/hw/mpcore.c @@ -40,6 +40,8 @@ typedef struct mpcore_priv_state { int iomemtype; mpcore_timer_state timer[8]; uint32_t num_cpu; + MemoryRegion iomem; + MemoryRegion container; } mpcore_priv_state; /* Per-CPU Timers. */ @@ -151,7 +153,8 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore, /* Per-CPU private memory mapped IO. */ -static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset) +static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset, + unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; @@ -203,7 +206,7 @@ bad_reg: } static void mpcore_priv_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; @@ -250,23 +253,19 @@ bad_reg: hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); } -static CPUReadMemoryFunc * const mpcore_priv_readfn[] = { - mpcore_priv_read, - mpcore_priv_read, - mpcore_priv_read +static const MemoryRegionOps mpcore_priv_ops = { + .read = mpcore_priv_read, + .write = mpcore_priv_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = { - mpcore_priv_write, - mpcore_priv_write, - mpcore_priv_write -}; - -static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base) +static void mpcore_priv_map_setup(mpcore_priv_state *s) { - mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev); - cpu_register_physical_memory(base, 0x1000, s->iomemtype); - cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype); + memory_region_init(&s->container, "mpcode-priv-container", 0x2000); + memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv", + 0x1000); + memory_region_add_subregion(&s->container, 0, &s->iomem); + memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem); } static int mpcore_priv_init(SysBusDevice *dev) @@ -275,10 +274,8 @@ static int mpcore_priv_init(SysBusDevice *dev) int i; gic_init(&s->gic, s->num_cpu); - s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn, - mpcore_priv_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map); + mpcore_priv_map_setup(s); + sysbus_init_mmio_region(dev, &s->container); for (i = 0; i < s->num_cpu * 2; i++) { mpcore_timer_init(s, &s->timer[i], i); } diff --git a/hw/msmouse.c b/hw/msmouse.c index b611c2f236..c3b57ea31c 100644 --- a/hw/msmouse.c +++ b/hw/msmouse.c @@ -50,7 +50,7 @@ static void msmouse_event(void *opaque, /* We always send the packet of, so that we do not have to keep track of previous state of the middle button. This can potentially confuse some very old drivers for two button mice though. */ - qemu_chr_read(chr, bytes, 4); + qemu_chr_be_write(chr, bytes, 4); } static int msmouse_chr_write (struct CharDriverState *s, const uint8_t *buf, int len) diff --git a/hw/nseries.c b/hw/nseries.c index 144fd5a426..f7aae7a59e 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -32,6 +32,7 @@ #include "bt.h" #include "loader.h" #include "blockdev.h" +#include "tusb6010.h" /* Nokia N8x0 support */ struct n800_s { @@ -17,6 +17,7 @@ * with this program; if not, see <http://www.gnu.org/licenses/>. */ #ifndef hw_omap_h +#include "memory.h" # define hw_omap_h "omap.h" # define OMAP_EMIFS_BASE 0x00000000 @@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s); struct omap_gpmc_s; struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq); void omap_gpmc_reset(struct omap_gpmc_s *s); -void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, +void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem, void (*base_upd)(void *opaque, target_phys_addr_t new), void (*unmap)(void *opaque), void *opaque); diff --git a/hw/omap2.c b/hw/omap2.c index 3b51ac525f..7e5820a97b 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -748,14 +748,14 @@ static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, if (ch == STI_TRACE_CONTROL_CHANNEL) { /* Flush channel <i>value</i>. */ - qemu_chr_write(s->chr, (const uint8_t *) "\r", 1); + qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1); } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { if (value == 0xc0 || value == 0xc3) { /* Open channel <i>ch</i>. */ } else if (value == 0x00) - qemu_chr_write(s->chr, (const uint8_t *) "\n", 1); + qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1); else - qemu_chr_write(s->chr, &byte, 1); + qemu_chr_fe_write(s->chr, &byte, 1); } } @@ -782,7 +782,7 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, s->irq = irq; omap_sti_reset(s); - s->chr = chr ?: qemu_chr_open("null", "null", NULL); + s->chr = chr ?: qemu_chr_new("null", "null", NULL); iomemtype = l4_register_io_memory(omap_sti_readfn, omap_sti_writefn, s); diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c index 13e3e00b6c..673dddd237 100644 --- a/hw/omap_gpmc.c +++ b/hw/omap_gpmc.c @@ -21,10 +21,13 @@ #include "hw.h" #include "flash.h" #include "omap.h" +#include "memory.h" +#include "exec-memory.h" /* General-Purpose Memory Controller */ struct omap_gpmc_s { qemu_irq irq; + MemoryRegion iomem; uint8_t sysconfig; uint16_t irqst; @@ -39,7 +42,8 @@ struct omap_gpmc_s { uint32_t config[7]; target_phys_addr_t base; size_t size; - int iomemtype; + MemoryRegion *iomem; + MemoryRegion container; void (*base_update)(void *opaque, target_phys_addr_t new); void (*unmap)(void *opaque); void *opaque; @@ -75,8 +79,12 @@ static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask) * constant), the mask should cause wrapping of the address space, so * that the same memory becomes accessible at every <i>size</i> bytes * starting from <i>base</i>. */ - if (f->iomemtype) - cpu_register_physical_memory(f->base, f->size, f->iomemtype); + if (f->iomem) { + memory_region_init(&f->container, "omap-gpmc-file", f->size); + memory_region_add_subregion(&f->container, 0, f->iomem); + memory_region_add_subregion(get_system_memory(), f->base, + &f->container); + } if (f->base_update) f->base_update(f->opaque, f->base); @@ -87,8 +95,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f) if (f->size) { if (f->unmap) f->unmap(f->opaque); - if (f->iomemtype) - cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED); + if (f->iomem) { + memory_region_del_subregion(get_system_memory(), &f->container); + memory_region_del_subregion(&f->container, f->iomem); + memory_region_destroy(&f->container); + } f->base = 0; f->size = 0; } @@ -124,7 +135,6 @@ void omap_gpmc_reset(struct omap_gpmc_s *s) s->cs_file[i].config[6] & 0x1f, /* MASKADDR */ (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */ } - omap_gpmc_cs_map(s->cs_file, 0, 0xf); s->ecc_cs = 0; s->ecc_ptr = 0; s->ecc_cfg = 0x3fcff000; @@ -132,12 +142,17 @@ void omap_gpmc_reset(struct omap_gpmc_s *s) ecc_reset(&s->ecc[i]); } -static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr) +static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr, + unsigned size) { struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; int cs; struct omap_gpmc_cs_file_s *f; + if (size != 4) { + return omap_badwidth_read32(opaque, addr); + } + switch (addr) { case 0x000: /* GPMC_REVISION */ return 0x20; @@ -230,12 +245,16 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr) } static void omap_gpmc_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; int cs; struct omap_gpmc_cs_file_s *f; + if (size != 4) { + return omap_badwidth_write32(opaque, addr, value); + } + switch (addr) { case 0x000: /* GPMC_REVISION */ case 0x014: /* GPMC_SYSSTATUS */ @@ -249,7 +268,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr, case 0x010: /* GPMC_SYSCONFIG */ if ((value >> 3) == 0x3) - fprintf(stderr, "%s: bad SDRAM idle mode %i\n", + fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n", __FUNCTION__, value >> 3); if (value & 2) omap_gpmc_reset(s); @@ -369,34 +388,26 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const omap_gpmc_readfn[] = { - omap_badwidth_read32, /* TODO */ - omap_badwidth_read32, /* TODO */ - omap_gpmc_read, -}; - -static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = { - omap_badwidth_write32, /* TODO */ - omap_badwidth_write32, /* TODO */ - omap_gpmc_write, +static const MemoryRegionOps omap_gpmc_ops = { + .read = omap_gpmc_read, + .write = omap_gpmc_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq) { - int iomemtype; struct omap_gpmc_s *s = (struct omap_gpmc_s *) g_malloc0(sizeof(struct omap_gpmc_s)); omap_gpmc_reset(s); - iomemtype = cpu_register_io_memory(omap_gpmc_readfn, - omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000); + memory_region_add_subregion(get_system_memory(), base, &s->iomem); return s; } -void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, +void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem, void (*base_upd)(void *opaque, target_phys_addr_t new), void (*unmap)(void *opaque), void *opaque) { @@ -408,7 +419,7 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, } f = &s->cs_file[cs]; - f->iomemtype = iomemtype; + f->iomem = iomem; f->base_update = base_upd; f->unmap = unmap; f->opaque = opaque; diff --git a/hw/omap_uart.c b/hw/omap_uart.c index 09ae9f8abf..191a0c2ccd 100644 --- a/hw/omap_uart.c +++ b/hw/omap_uart.c @@ -62,11 +62,11 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base, s->irq = irq; #ifdef TARGET_WORDS_BIGENDIAN s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, - chr ?: qemu_chr_open(label, "null", NULL), 1, + chr ?: qemu_chr_new(label, "null", NULL), 1, 1); #else s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, - chr ?: qemu_chr_open(label, "null", NULL), 1, + chr ?: qemu_chr_new(label, "null", NULL), 1, 0); #endif return s; @@ -185,12 +185,12 @@ void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) #ifdef TARGET_WORDS_BIGENDIAN s->serial = serial_mm_init(s->base, 2, s->irq, omap_clk_getrate(s->fclk) / 16, - chr ?: qemu_chr_open("null", "null", NULL), 1, + chr ?: qemu_chr_new("null", "null", NULL), 1, 1); #else s->serial = serial_mm_init(s->base, 2, s->irq, omap_clk_getrate(s->fclk) / 16, - chr ?: qemu_chr_open("null", "null", NULL), 1, + chr ?: qemu_chr_new("null", "null", NULL), 1, 0); #endif } diff --git a/hw/onenand.c b/hw/onenand.c index c37cf59bef..00276a03cb 100644 --- a/hw/onenand.c +++ b/hw/onenand.c @@ -23,6 +23,8 @@ #include "flash.h" #include "irq.h" #include "blockdev.h" +#include "memory.h" +#include "exec-memory.h" /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */ #define PAGE_SHIFT 11 @@ -45,10 +47,12 @@ typedef struct { uint8_t *image; uint8_t *otp; uint8_t *current; - ram_addr_t ram; + MemoryRegion ram; + MemoryRegion mapped_ram; uint8_t *boot[2]; uint8_t *data[2][2]; - int iomemtype; + MemoryRegion iomem; + MemoryRegion container; int cycle; int otpmode; @@ -100,31 +104,36 @@ enum { ONEN_LOCK_UNLOCKED = 1 << 2, }; +static void onenand_mem_setup(OneNANDState *s) +{ + /* XXX: We should use IO_MEM_ROMD but we broke it earlier... + * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to + * write boot commands. Also take note of the BWPS bit. */ + memory_region_init(&s->container, "onenand", 0x10000 << s->shift); + memory_region_add_subregion(&s->container, 0, &s->iomem); + memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram", + &s->ram, 0x0200 << s->shift, + 0xbe00 << s->shift); + memory_region_add_subregion_overlap(&s->container, + 0x0200 << s->shift, + &s->mapped_ram, + 1); +} + void onenand_base_update(void *opaque, target_phys_addr_t new) { OneNANDState *s = (OneNANDState *) opaque; s->base = new; - /* XXX: We should use IO_MEM_ROMD but we broke it earlier... - * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to - * write boot commands. Also take note of the BWPS bit. */ - cpu_register_physical_memory(s->base + (0x0000 << s->shift), - 0x0200 << s->shift, s->iomemtype); - cpu_register_physical_memory(s->base + (0x0200 << s->shift), - 0xbe00 << s->shift, - (s->ram +(0x0200 << s->shift)) | IO_MEM_RAM); - if (s->iomemtype) - cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift), - 0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift)); + memory_region_add_subregion(get_system_memory(), s->base, &s->container); } void onenand_base_unmap(void *opaque) { OneNANDState *s = (OneNANDState *) opaque; - cpu_register_physical_memory(s->base, - 0x10000 << s->shift, IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &s->container); } static void onenand_intr_update(OneNANDState *s) @@ -524,7 +533,8 @@ static void onenand_command(OneNANDState *s, int cmd) onenand_intr_update(s); } -static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) +static uint64_t onenand_read(void *opaque, target_phys_addr_t addr, + unsigned size) { OneNANDState *s = (OneNANDState *) opaque; int offset = addr >> s->shift; @@ -589,7 +599,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) } static void onenand_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { OneNANDState *s = (OneNANDState *) opaque; int offset = addr >> s->shift; @@ -628,7 +638,7 @@ static void onenand_write(void *opaque, target_phys_addr_t addr, break; default: - fprintf(stderr, "%s: unknown OneNAND boot command %x\n", + fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n", __FUNCTION__, value); } break; @@ -684,16 +694,10 @@ static void onenand_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const onenand_readfn[] = { - onenand_read, /* TODO */ - onenand_read, - onenand_read, -}; - -static CPUWriteMemoryFunc * const onenand_writefn[] = { - onenand_write, /* TODO */ - onenand_write, - onenand_write, +static const MemoryRegionOps onenand_ops = { + .read = onenand_read, + .write = onenand_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; void *onenand_init(BlockDriverState *bdrv, @@ -714,8 +718,8 @@ void *onenand_init(BlockDriverState *bdrv, s->secs = size >> 9; s->blockwp = g_malloc(s->blocks); s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0; - s->iomemtype = cpu_register_io_memory(onenand_readfn, - onenand_writefn, s, DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand", + 0x10000 << s->shift); s->bdrv = bdrv; if (!s->bdrv) { s->image = memset(g_malloc(size + (size >> 5)), @@ -723,14 +727,15 @@ void *onenand_init(BlockDriverState *bdrv, } s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT), 0xff, (64 + 2) << PAGE_SHIFT); - s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift); - ram = qemu_get_ram_ptr(s->ram); + memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift); + ram = memory_region_get_ram_ptr(&s->ram); s->boot[0] = ram + (0x0000 << s->shift); s->boot[1] = ram + (0x8000 << s->shift); s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); + onenand_mem_setup(s); onenand_reset(s, 1); diff --git a/hw/parallel.c b/hw/parallel.c index 71f30ea1e8..ecbc8c3b77 100644 --- a/hw/parallel.c +++ b/hw/parallel.c @@ -120,7 +120,7 @@ parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) if (val & PARA_CTR_STROBE) { s->status &= ~PARA_STS_BUSY; if ((s->control & PARA_CTR_STROBE) == 0) - qemu_chr_write(s->chr, &s->dataw, 1); + qemu_chr_fe_write(s->chr, &s->dataw, 1); } else { if (s->control & PARA_CTR_INTEN) { s->irq_pending = 1; @@ -150,7 +150,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) if (s->dataw == val) return; pdebug("wd%02x\n", val); - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); s->dataw = val; break; case PARA_REG_STS: @@ -170,11 +170,11 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) } else { dir = 0; } - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); parm &= ~PARA_CTR_DIR; } - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); s->control = val; break; case PARA_REG_EPP_ADDR: @@ -183,7 +183,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) pdebug("wa%02x s\n", val); else { struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { + if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { s->epp_timeout = 1; pdebug("wa%02x t\n", val); } @@ -197,7 +197,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) pdebug("we%02x s\n", val); else { struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { + if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { s->epp_timeout = 1; pdebug("we%02x t\n", val); } @@ -222,7 +222,7 @@ parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) pdebug("we%04x s\n", val); return; } - err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); + err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); if (err) { s->epp_timeout = 1; pdebug("we%04x t\n", val); @@ -245,7 +245,7 @@ parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) pdebug("we%08x s\n", val); return; } - err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); + err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); if (err) { s->epp_timeout = 1; pdebug("we%08x t\n", val); @@ -297,13 +297,13 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) addr &= 7; switch(addr) { case PARA_REG_DATA: - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); if (s->last_read_offset != addr || s->datar != ret) pdebug("rd%02x\n", ret); s->datar = ret; break; case PARA_REG_STS: - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); ret &= ~PARA_STS_TMOUT; if (s->epp_timeout) ret |= PARA_STS_TMOUT; @@ -315,7 +315,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) /* s->control has some bits fixed to 1. It is zero only when it has not been yet written to. */ if (s->control == 0) { - qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); if (s->last_read_offset != addr) pdebug("rc%02x\n", ret); s->control = ret; @@ -332,7 +332,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) pdebug("ra%02x s\n", ret); else { struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { + if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { s->epp_timeout = 1; pdebug("ra%02x t\n", ret); } @@ -346,7 +346,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) pdebug("re%02x s\n", ret); else { struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { + if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { s->epp_timeout = 1; pdebug("re%02x t\n", ret); } @@ -374,7 +374,7 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) pdebug("re%04x s\n", eppdata); return eppdata; } - err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); + err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); ret = le16_to_cpu(eppdata); if (err) { @@ -401,7 +401,7 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) pdebug("re%08x s\n", eppdata); return eppdata; } - err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); + err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); ret = le32_to_cpu(eppdata); if (err) { @@ -473,7 +473,7 @@ static int parallel_isa_initfn(ISADevice *dev) isa_init_irq(dev, &s->irq, isa->isairq); qemu_register_reset(parallel_reset, s); - if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { + if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { s->hw_driver = 1; s->status = dummy; } @@ -42,6 +42,7 @@ #include "blockdev.h" #include "ui/qemu-spice.h" #include "memory.h" +#include "exec-memory.h" /* output Bochs bios info messages */ //#define DEBUG_BIOS @@ -963,7 +964,9 @@ void pc_memory_init(MemoryRegion *system_memory, const char *kernel_cmdline, const char *initrd_filename, ram_addr_t below_4g_mem_size, - ram_addr_t above_4g_mem_size) + ram_addr_t above_4g_mem_size, + MemoryRegion *pci_memory, + MemoryRegion **ram_memory) { char *filename; int ret, linux_boot, i; @@ -981,6 +984,7 @@ void pc_memory_init(MemoryRegion *system_memory, ram = g_malloc(sizeof(*ram)); memory_region_init_ram(ram, NULL, "pc.ram", below_4g_mem_size + above_4g_mem_size); + *ram_memory = ram; ram_below_4g = g_malloc(sizeof(*ram_below_4g)); memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, 0, below_4g_mem_size); @@ -1025,7 +1029,7 @@ void pc_memory_init(MemoryRegion *system_memory, isa_bios = g_malloc(sizeof(*isa_bios)); memory_region_init_alias(isa_bios, "isa-bios", bios, bios_size - isa_bios_size, isa_bios_size); - memory_region_add_subregion_overlap(system_memory, + memory_region_add_subregion_overlap(pci_memory, 0x100000 - isa_bios_size, isa_bios, 1); @@ -1033,13 +1037,13 @@ void pc_memory_init(MemoryRegion *system_memory, option_rom_mr = g_malloc(sizeof(*option_rom_mr)); memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE); - memory_region_add_subregion_overlap(system_memory, + memory_region_add_subregion_overlap(pci_memory, PC_ROM_MIN_VGA, option_rom_mr, 1); /* map all the bios at the top of memory */ - memory_region_add_subregion(system_memory, + memory_region_add_subregion(pci_memory, (uint32_t)(-bios_size), bios); @@ -1066,7 +1070,7 @@ void pc_vga_init(PCIBus *pci_bus) if (pci_bus) { pci_cirrus_vga_init(pci_bus); } else { - isa_cirrus_vga_init(); + isa_cirrus_vga_init(get_system_memory()); } } else if (vmsvga_enabled) { if (pci_bus) { @@ -136,7 +136,9 @@ void pc_memory_init(MemoryRegion *system_memory, const char *kernel_cmdline, const char *initrd_filename, ram_addr_t below_4g_mem_size, - ram_addr_t above_4g_mem_size); + ram_addr_t above_4g_mem_size, + MemoryRegion *pci_memory, + MemoryRegion **ram_memory); qemu_irq *pc_allocate_cpu_irq(void); void pc_vga_init(PCIBus *pci_bus); void pc_basic_device_init(qemu_irq *isa_irq, @@ -182,8 +184,13 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, - ram_addr_t ram_size); -void i440fx_init_memory_mappings(PCII440FXState *d); + ram_addr_t ram_size, + target_phys_addr_t pci_hole_start, + target_phys_addr_t pci_hole_size, + target_phys_addr_t pci_hole64_start, + target_phys_addr_t pci_hole64_size, + MemoryRegion *pci_memory, + MemoryRegion *ram_memory); /* piix4.c */ extern PCIDevice *piix4_dev; @@ -212,11 +219,12 @@ static inline int isa_vga_init(void) int pci_vga_init(PCIBus *bus); int isa_vga_mm_init(target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift); + target_phys_addr_t ctrl_base, int it_shift, + MemoryRegion *address_space); /* cirrus_vga.c */ void pci_cirrus_vga_init(PCIBus *bus); -void isa_cirrus_vga_init(void); +void isa_cirrus_vga_init(MemoryRegion *address_space); /* ne2000.c */ static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd) diff --git a/hw/pc_piix.c b/hw/pc_piix.c index a9fe5964d8..75d96d97c6 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ +#include <glib.h> + #include "hw.h" #include "pc.h" #include "apic.h" @@ -93,6 +95,8 @@ static void pc_init1(MemoryRegion *system_memory, DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; BusState *idebus[MAX_IDE_BUS]; ISADevice *rtc_state; + MemoryRegion *ram_memory; + MemoryRegion *pci_memory; pc_cpus_init(cpu_model); @@ -108,11 +112,15 @@ static void pc_init1(MemoryRegion *system_memory, below_4g_mem_size = ram_size; } + pci_memory = g_new(MemoryRegion, 1); + memory_region_init(pci_memory, "pci", INT64_MAX); + /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(system_memory, kernel_filename, kernel_cmdline, initrd_filename, - below_4g_mem_size, above_4g_mem_size); + below_4g_mem_size, above_4g_mem_size, + pci_memory, &ram_memory); } if (!xen_enabled()) { @@ -130,7 +138,14 @@ static void pc_init1(MemoryRegion *system_memory, if (pci_enabled) { pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, - system_memory, system_io, ram_size); + system_memory, system_io, ram_size, + below_4g_mem_size, + 0x100000000ULL - below_4g_mem_size, + 0x100000000ULL + above_4g_mem_size, + (sizeof(target_phys_addr_t) == 4 + ? 0 + : ((uint64_t)1 << 62)), + pci_memory, ram_memory); } else { pci_bus = NULL; i440fx_state = NULL; @@ -202,10 +217,6 @@ static void pc_init1(MemoryRegion *system_memory, smbus_eeprom_init(smbus, 8, NULL, 0); } - if (i440fx_state) { - i440fx_init_memory_mappings(i440fx_state); - } - if (pci_enabled) { pc_pci_device_init(pci_bus); } @@ -2165,3 +2165,8 @@ int pci_qdev_find_device(const char *id, PCIDevice **pdev) return rc; } + +MemoryRegion *pci_address_space(PCIDevice *dev) +{ + return dev->bus->address_space_mem; +} @@ -220,6 +220,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len); void pci_device_save(PCIDevice *s, QEMUFile *f); int pci_device_load(PCIDevice *s, QEMUFile *f); +MemoryRegion *pci_address_space(PCIDevice *dev); typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); diff --git a/hw/pcie_host.c b/hw/pcie_host.c index f9fea3d918..28bbe72b37 100644 --- a/hw/pcie_host.c +++ b/hw/pcie_host.c @@ -22,6 +22,7 @@ #include "hw.h" #include "pci.h" #include "pcie_host.h" +#include "exec-memory.h" /* * PCI express mmcfig address @@ -52,9 +53,11 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, PCIE_MMCFG_DEVFN(mmcfg_addr)); } -static void pcie_mmcfg_data_write(PCIBus *s, - uint32_t mmcfg_addr, uint32_t val, int len) +static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr, + uint64_t val, unsigned len) { + PCIExpressHost *e = opaque; + PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); uint32_t addr; uint32_t limit; @@ -72,8 +75,12 @@ static void pcie_mmcfg_data_write(PCIBus *s, pci_host_config_write_common(pci_dev, addr, limit, val, len); } -static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len) +static uint64_t pcie_mmcfg_data_read(void *opaque, + target_phys_addr_t mmcfg_addr, + unsigned len) { + PCIExpressHost *e = opaque; + PCIBus *s = e->pci.bus; PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); uint32_t addr; uint32_t limit; @@ -91,72 +98,23 @@ static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len) return pci_host_config_read_common(pci_dev, addr, limit, len); } -static void pcie_mmcfg_data_writeb(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1); -} - -static void pcie_mmcfg_data_writew(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2); -} - -static void pcie_mmcfg_data_writel(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - PCIExpressHost *e = opaque; - pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4); -} - -static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1); -} - -static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2); -} - -static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr) -{ - PCIExpressHost *e = opaque; - return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4); -} - - -static CPUWriteMemoryFunc * const pcie_mmcfg_write[] = -{ - pcie_mmcfg_data_writeb, - pcie_mmcfg_data_writew, - pcie_mmcfg_data_writel, -}; - -static CPUReadMemoryFunc * const pcie_mmcfg_read[] = -{ - pcie_mmcfg_data_readb, - pcie_mmcfg_data_readw, - pcie_mmcfg_data_readl, +static const MemoryRegionOps pcie_mmcfg_ops = { + .read = pcie_mmcfg_data_read, + .write = pcie_mmcfg_data_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL) -int pcie_host_init(PCIExpressHost *e) +int pcie_host_init(PCIExpressHost *e, uint32_t size) { + assert(!(size & (size - 1))); /* power of 2 */ + assert(size >= PCIE_MMCFG_SIZE_MIN); + assert(size <= PCIE_MMCFG_SIZE_MAX); e->base_addr = PCIE_BASE_ADDR_UNMAPPED; - e->mmio_index = - cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e, - DEVICE_NATIVE_ENDIAN); - if (e->mmio_index < 0) { - return -1; - } + e->size = size; + memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size); return 0; } @@ -164,29 +122,23 @@ int pcie_host_init(PCIExpressHost *e) void pcie_host_mmcfg_unmap(PCIExpressHost *e) { if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) { - cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &e->mmio); e->base_addr = PCIE_BASE_ADDR_UNMAPPED; } } -void pcie_host_mmcfg_map(PCIExpressHost *e, - target_phys_addr_t addr, uint32_t size) +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr) { - assert(!(size & (size - 1))); /* power of 2 */ - assert(size >= PCIE_MMCFG_SIZE_MIN); - assert(size <= PCIE_MMCFG_SIZE_MAX); - e->base_addr = addr; - e->size = size; - cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index); + memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio); } void pcie_host_mmcfg_update(PCIExpressHost *e, int enable, - target_phys_addr_t addr, uint32_t size) + target_phys_addr_t addr) { pcie_host_mmcfg_unmap(e); if (enable) { - pcie_host_mmcfg_map(e, addr, size); + pcie_host_mmcfg_map(e, addr); } } diff --git a/hw/pcie_host.h b/hw/pcie_host.h index a2026617b7..0074508b43 100644 --- a/hw/pcie_host.h +++ b/hw/pcie_host.h @@ -22,6 +22,7 @@ #define PCIE_HOST_H #include "pci_host.h" +#include "memory.h" struct PCIExpressHost { PCIHostState pci; @@ -34,16 +35,15 @@ struct PCIExpressHost { /* the size of MMCONFIG area. It's host bridge dependent */ target_phys_addr_t size; - /* result of cpu_register_io_memory() to map MMCONFIG area */ - int mmio_index; + /* MMCONFIG mmio area */ + MemoryRegion mmio; }; -int pcie_host_init(PCIExpressHost *e); +int pcie_host_init(PCIExpressHost *e, uint32_t size); void pcie_host_mmcfg_unmap(PCIExpressHost *e); -void pcie_host_mmcfg_map(PCIExpressHost *e, - target_phys_addr_t addr, uint32_t size); +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr); void pcie_host_mmcfg_update(PCIExpressHost *e, int enable, - target_phys_addr_t addr, uint32_t size); + target_phys_addr_t addr); #endif /* PCIE_HOST_H */ diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c index 13d9380b00..51e132050f 100644 --- a/hw/pcnet-pci.c +++ b/hw/pcnet-pci.c @@ -290,10 +290,10 @@ static int pci_pcnet_init(PCIDevice *pci_dev) pci_conf[PCI_MAX_LAT] = 0xff; /* Handler for memory-mapped I/O */ - memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, d, "pcnet-mmio", + memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio", PCNET_PNPMMIO_SIZE); - memory_region_init_io(&d->io_bar, &pcnet_io_ops, d, "pcnet-io", + memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io", PCNET_IOPORT_SIZE); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index e3a66e51b6..e3ca310efd 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -39,6 +39,7 @@ #include "blockdev.h" #include "pc.h" +#include "microblaze_pic_cpu.h" #include "xilinx_axidma.h" #define LMB_BRAM_SIZE (128 * 1024) diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 589e8cabb0..a43fb4c95c 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -36,6 +36,8 @@ #include "elf.h" #include "blockdev.h" +#include "microblaze_pic_cpu.h" + #define LMB_BRAM_SIZE (128 * 1024) #define FLASH_SIZE (16 * 1024 * 1024) diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 28a3ee2e9c..c563c6e1a3 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -66,10 +66,22 @@ typedef struct PIIX3State { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; } PIIX3State; +typedef struct PAMMemoryRegion { + MemoryRegion mem; + bool initialized; +} PAMMemoryRegion; + struct PCII440FXState { PCIDevice dev; - target_phys_addr_t isa_page_descs[384 / 4]; + MemoryRegion *system_memory; + MemoryRegion *pci_address_space; + MemoryRegion *ram_memory; + MemoryRegion pci_hole; + MemoryRegion pci_hole_64bit; + PAMMemoryRegion pam_regions[13]; + MemoryRegion smram_region; uint8_t smm_enabled; + bool smram_enabled; PIIX3State *piix3; }; @@ -92,50 +104,62 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) return (pci_intx + slot_addend) & 3; } -static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) +static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r, + PAMMemoryRegion *mem) { - uint32_t addr; + if (mem->initialized) { + memory_region_del_subregion(d->system_memory, &mem->mem); + memory_region_destroy(&mem->mem); + } // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r); switch(r) { case 3: /* RAM */ - cpu_register_physical_memory(start, end - start, - start); + memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory, + start, end - start); break; case 1: /* ROM (XXX: not quite correct) */ - cpu_register_physical_memory(start, end - start, - start | IO_MEM_ROM); + memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory, + start, end - start); + memory_region_set_readonly(&mem->mem, true); break; case 2: case 0: /* XXX: should distinguish read/write cases */ - for(addr = start; addr < end; addr += 4096) { - cpu_register_physical_memory(addr, 4096, - d->isa_page_descs[(addr - 0xa0000) >> 12]); - } + memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space, + start, end - start); break; } + memory_region_add_subregion_overlap(d->system_memory, + start, &mem->mem, 1); + mem->initialized = true; } static void i440fx_update_memory_mappings(PCII440FXState *d) { int i, r; - uint32_t smram, addr; + uint32_t smram; - update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3); + update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3, + &d->pam_regions[0]); for(i = 0; i < 12; i++) { r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3; - update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); + update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r, + &d->pam_regions[i+1]); } smram = d->dev.config[I440FX_SMRAM]; if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) { - cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); + if (!d->smram_enabled) { + memory_region_del_subregion(d->system_memory, &d->smram_region); + d->smram_enabled = true; + } } else { - for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { - cpu_register_physical_memory(addr, 4096, - d->isa_page_descs[(addr - 0xa0000) >> 12]); + if (d->smram_enabled) { + memory_region_add_subregion_overlap(d->system_memory, 0xa0000, + &d->smram_region, 1); + d->smram_enabled = false; } } } @@ -152,17 +176,6 @@ static void i440fx_set_smm(int val, void *arg) } -/* XXX: suppress when better memory API. We make the assumption that - no device (in particular the VGA) changes the memory mappings in - the 0xa0000-0x100000 range */ -void i440fx_init_memory_mappings(PCII440FXState *d) -{ - int i; - for(i = 0; i < 96; i++) { - d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); - } -} - static void i440fx_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len) { @@ -244,24 +257,48 @@ static PCIBus *i440fx_common_init(const char *device_name, qemu_irq *pic, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, - ram_addr_t ram_size) + ram_addr_t ram_size, + target_phys_addr_t pci_hole_start, + target_phys_addr_t pci_hole_size, + target_phys_addr_t pci_hole64_start, + target_phys_addr_t pci_hole64_size, + MemoryRegion *pci_address_space, + MemoryRegion *ram_memory) { DeviceState *dev; PCIBus *b; PCIDevice *d; I440FXState *s; PIIX3State *piix3; + PCII440FXState *f; dev = qdev_create(NULL, "i440FX-pcihost"); s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); s->address_space = address_space_mem; - b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space, + b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space, address_space_io, 0); s->bus = b; qdev_init_nofail(dev); d = pci_create_simple(b, 0, device_name); *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); + f = *pi440fx_state; + f->system_memory = address_space_mem; + f->pci_address_space = pci_address_space; + f->ram_memory = ram_memory; + memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space, + pci_hole_start, pci_hole_size); + memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); + memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64", + f->pci_address_space, + pci_hole64_start, pci_hole64_size); + if (pci_hole64_size) { + memory_region_add_subregion(f->system_memory, pci_hole64_start, + &f->pci_hole_64bit); + } + memory_region_init_alias(&f->smram_region, "smram-region", + f->pci_address_space, 0xa0000, 0x20000); + f->smram_enabled = true; /* Xen supports additional interrupt routes from the PCI devices to * the IOAPIC: the four pins of each PCI device on the bus are also @@ -289,6 +326,8 @@ static PCIBus *i440fx_common_init(const char *device_name, ram_size = 255; (*pi440fx_state)->dev.config[0x57]=ram_size; + i440fx_update_memory_mappings(f); + return b; } @@ -296,12 +335,21 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, - ram_addr_t ram_size) + ram_addr_t ram_size, + target_phys_addr_t pci_hole_start, + target_phys_addr_t pci_hole_size, + target_phys_addr_t pci_hole64_start, + target_phys_addr_t pci_hole64_size, + MemoryRegion *pci_memory, MemoryRegion *ram_memory) + { PCIBus *b; b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, - address_space_mem, address_space_io, ram_size); + address_space_mem, address_space_io, ram_size, + pci_hole_start, pci_hole_size, + pci_hole64_size, pci_hole64_size, + pci_memory, ram_memory); return b; } diff --git a/hw/pl011.c b/hw/pl011.c index 997ce848f8..707a161046 100644 --- a/hw/pl011.c +++ b/hw/pl011.c @@ -133,7 +133,7 @@ static void pl011_write(void *opaque, target_phys_addr_t offset, /* ??? Check if transmitter is enabled. */ ch = value; if (s->chr) - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); s->int_level |= PL011_INT_TX; pl011_update(s); break; diff --git a/hw/ppc405.h b/hw/ppc405.h index e042a05b3b..f0e81a6495 100644 --- a/hw/ppc405.h +++ b/hw/ppc405.h @@ -59,16 +59,19 @@ struct ppc4xx_bd_info_t { ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, uint32_t flags); -CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], +CPUState *ppc405cr_init (MemoryRegion ram_memories[4], + target_phys_addr_t ram_bases[4], target_phys_addr_t ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init); -CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], +CPUState *ppc405ep_init (MemoryRegion ram_memories[2], + target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init); /* IBM STBxxx microcontrollers */ -CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2], +CPUState *ppc_stb025_init (MemoryRegion ram_memories[2], + target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, ram_addr_t *offsetp); diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 34f9350864..dec165e40f 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -182,6 +182,7 @@ static void ref405ep_init (ram_addr_t ram_size, CPUPPCState *env; qemu_irq *pic; ram_addr_t sram_offset, bios_offset, bdloc; + MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); target_phys_addr_t ram_bases[2], ram_sizes[2]; target_ulong sram_size; long bios_size; @@ -194,15 +195,17 @@ static void ref405ep_init (ram_addr_t ram_size, DriveInfo *dinfo; /* XXX: fix this */ - ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000); + memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000); + ram_bases[0] = 0; ram_sizes[0] = 0x08000000; + memory_region_init(&ram_memories[1], "ef405ep.ram1", 0); ram_bases[1] = 0x00000000; ram_sizes[1] = 0x00000000; ram_size = 128 * 1024 * 1024; #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, + env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ sram_size = 512 * 1024; @@ -505,6 +508,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, char *filename; qemu_irq *pic; ram_addr_t bios_offset; + MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); target_phys_addr_t ram_bases[2], ram_sizes[2]; long bios_size; target_ulong kernel_base, initrd_base; @@ -514,15 +518,19 @@ static void taihu_405ep_init(ram_addr_t ram_size, DriveInfo *dinfo; /* RAM is soldered to the board so the size cannot be changed */ - ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000); + memory_region_init_ram(&ram_memories[0], NULL, + "taihu_405ep.ram-0", 0x04000000); + ram_bases[0] = 0; ram_sizes[0] = 0x04000000; - ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000); + memory_region_init_ram(&ram_memories[1], NULL, + "taihu_405ep.ram-1", 0x04000000); + ram_bases[1] = 0x04000000; ram_sizes[1] = 0x04000000; ram_size = 0x08000000; #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, + ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate and load BIOS */ #ifdef DEBUG_BOARD_INIT diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 68c7cbd3a8..9d5d2af5d8 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -28,6 +28,7 @@ #include "qemu-timer.h" #include "sysemu.h" #include "qemu-log.h" +#include "exec-memory.h" #define DEBUG_OPBA #define DEBUG_SDRAM @@ -259,6 +260,7 @@ static void ppc4xx_pob_init(CPUState *env) /* OPB arbitrer */ typedef struct ppc4xx_opba_t ppc4xx_opba_t; struct ppc4xx_opba_t { + MemoryRegion io; uint8_t cr; uint8_t pr; }; @@ -357,16 +359,12 @@ static void opba_writel (void *opaque, opba_writeb(opaque, addr + 1, value >> 16); } -static CPUReadMemoryFunc * const opba_read[] = { - &opba_readb, - &opba_readw, - &opba_readl, -}; - -static CPUWriteMemoryFunc * const opba_write[] = { - &opba_writeb, - &opba_writew, - &opba_writel, +static const MemoryRegionOps opba_ops = { + .old_mmio = { + .read = { opba_readb, opba_readw, opba_readl, }, + .write = { opba_writeb, opba_writew, opba_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc4xx_opba_reset (void *opaque) @@ -381,15 +379,13 @@ static void ppc4xx_opba_reset (void *opaque) static void ppc4xx_opba_init(target_phys_addr_t base) { ppc4xx_opba_t *opba; - int io; opba = g_malloc0(sizeof(ppc4xx_opba_t)); #ifdef DEBUG_OPBA printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(opba_read, opba_write, opba, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x002, io); + memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002); + memory_region_add_subregion(get_system_memory(), base, &opba->io); qemu_register_reset(ppc4xx_opba_reset, opba); } @@ -722,6 +718,7 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) /* GPIO */ typedef struct ppc405_gpio_t ppc405_gpio_t; struct ppc405_gpio_t { + MemoryRegion io; uint32_t or; uint32_t tcr; uint32_t osrh; @@ -789,16 +786,12 @@ static void ppc405_gpio_writel (void *opaque, #endif } -static CPUReadMemoryFunc * const ppc405_gpio_read[] = { - &ppc405_gpio_readb, - &ppc405_gpio_readw, - &ppc405_gpio_readl, -}; - -static CPUWriteMemoryFunc * const ppc405_gpio_write[] = { - &ppc405_gpio_writeb, - &ppc405_gpio_writew, - &ppc405_gpio_writel, +static const MemoryRegionOps ppc405_gpio_ops = { + .old_mmio = { + .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, }, + .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc405_gpio_reset (void *opaque) @@ -808,15 +801,13 @@ static void ppc405_gpio_reset (void *opaque) static void ppc405_gpio_init(target_phys_addr_t base) { ppc405_gpio_t *gpio; - int io; gpio = g_malloc0(sizeof(ppc405_gpio_t)); #ifdef DEBUG_GPIO printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x038, io); + memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038); + memory_region_add_subregion(get_system_memory(), base, &gpio->io); qemu_register_reset(&ppc405_gpio_reset, gpio); } @@ -831,7 +822,9 @@ enum { typedef struct ppc405_ocm_t ppc405_ocm_t; struct ppc405_ocm_t { - target_ulong offset; + MemoryRegion ram; + MemoryRegion isarc_ram; + MemoryRegion dsarc_ram; uint32_t isarc; uint32_t isacntl; uint32_t dsarc; @@ -854,16 +847,15 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, if (ocm->isacntl & 0x80000000) { /* Unmap previously assigned memory region */ printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); - cpu_register_physical_memory(ocm->isarc, 0x04000000, - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); } if (isacntl & 0x80000000) { /* Map new instruction memory region */ #ifdef DEBUG_OCM printf("OCM map ISA %08" PRIx32 "\n", isarc); #endif - cpu_register_physical_memory(isarc, 0x04000000, - ocm->offset | IO_MEM_RAM); + memory_region_add_subregion(get_system_memory(), isarc, + &ocm->isarc_ram); } } if (ocm->dsarc != dsarc || @@ -875,8 +867,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, #ifdef DEBUG_OCM printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); #endif - cpu_register_physical_memory(ocm->dsarc, 0x04000000, - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), + &ocm->dsarc_ram); } } if (dsacntl & 0x80000000) { @@ -886,8 +878,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, #ifdef DEBUG_OCM printf("OCM map DSA %08" PRIx32 "\n", dsarc); #endif - cpu_register_physical_memory(dsarc, 0x04000000, - ocm->offset | IO_MEM_RAM); + memory_region_add_subregion(get_system_memory(), dsarc, + &ocm->dsarc_ram); } } } @@ -973,7 +965,10 @@ static void ppc405_ocm_init(CPUState *env) ppc405_ocm_t *ocm; ocm = g_malloc0(sizeof(ppc405_ocm_t)); - ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096); + /* XXX: Size is 4096 or 0x04000000 */ + memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096); + memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram, + 0, 4096); qemu_register_reset(&ocm_reset, ocm); ppc_dcr_register(env, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm); @@ -990,6 +985,7 @@ static void ppc405_ocm_init(CPUState *env) typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; struct ppc4xx_i2c_t { qemu_irq irq; + MemoryRegion iomem; uint8_t mdata; uint8_t lmadr; uint8_t hmadr; @@ -1186,16 +1182,12 @@ static void ppc4xx_i2c_writel (void *opaque, ppc4xx_i2c_writeb(opaque, addr + 3, value); } -static CPUReadMemoryFunc * const i2c_read[] = { - &ppc4xx_i2c_readb, - &ppc4xx_i2c_readw, - &ppc4xx_i2c_readl, -}; - -static CPUWriteMemoryFunc * const i2c_write[] = { - &ppc4xx_i2c_writeb, - &ppc4xx_i2c_writew, - &ppc4xx_i2c_writel, +static const MemoryRegionOps i2c_ops = { + .old_mmio = { + .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, }, + .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc4xx_i2c_reset (void *opaque) @@ -1217,16 +1209,14 @@ static void ppc4xx_i2c_reset (void *opaque) static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) { ppc4xx_i2c_t *i2c; - int io; i2c = g_malloc0(sizeof(ppc4xx_i2c_t)); i2c->irq = irq; #ifdef DEBUG_I2C printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(i2c_read, i2c_write, i2c, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x011, io); + memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011); + memory_region_add_subregion(get_system_memory(), base, &i2c->iomem); qemu_register_reset(ppc4xx_i2c_reset, i2c); } @@ -1234,6 +1224,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) /* General purpose timers */ typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; struct ppc4xx_gpt_t { + MemoryRegion iomem; int64_t tb_offset; uint32_t tb_freq; struct QEMUTimer *timer; @@ -1454,16 +1445,12 @@ static void ppc4xx_gpt_writel (void *opaque, } } -static CPUReadMemoryFunc * const gpt_read[] = { - &ppc4xx_gpt_readb, - &ppc4xx_gpt_readw, - &ppc4xx_gpt_readl, -}; - -static CPUWriteMemoryFunc * const gpt_write[] = { - &ppc4xx_gpt_writeb, - &ppc4xx_gpt_writew, - &ppc4xx_gpt_writel, +static const MemoryRegionOps gpt_ops = { + .old_mmio = { + .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, }, + .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc4xx_gpt_cb (void *opaque) @@ -1498,7 +1485,6 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) { ppc4xx_gpt_t *gpt; int i; - int io; gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); for (i = 0; i < 5; i++) { @@ -1508,8 +1494,8 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) #ifdef DEBUG_GPT printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x0d4, io); + memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4); + memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); qemu_register_reset(ppc4xx_gpt_reset, gpt); } @@ -2121,7 +2107,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], qemu_register_reset(ppc405cr_cpc_reset, cpc); } -CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], +CPUState *ppc405cr_init (MemoryRegion ram_memories[4], + target_phys_addr_t ram_bases[4], target_phys_addr_t ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init) @@ -2150,7 +2137,8 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); *picp = pic; /* SDRAM controller */ - ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[14], 1, ram_memories, + ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ @@ -2465,7 +2453,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], #endif } -CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], +CPUState *ppc405ep_init (MemoryRegion ram_memories[2], + target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init) @@ -2499,7 +2488,8 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], *picp = pic; /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[17], 2, ram_memories, + ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ diff --git a/hw/ppc440.c b/hw/ppc440.c index baf991f2d4..5885ff057c 100644 --- a/hw/ppc440.c +++ b/hw/ppc440.c @@ -38,6 +38,8 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip, const unsigned int pci_irq_nrs[4], int do_init, const char *cpu_model) { + MemoryRegion *ram_memories + = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories)); target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; CPUState *env; @@ -66,11 +68,12 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip, memset(ram_bases, 0, sizeof(ram_bases)); memset(ram_sizes, 0, sizeof(ram_sizes)); *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, + ram_memories, ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ - ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases, - ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, + ram_bases, ram_sizes, do_init); /* PCI */ pci_irqs = g_malloc(sizeof(qemu_irq) * 4); diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h index bc4ee019a5..f969e44e1b 100644 --- a/hw/ppc4xx.h +++ b/hw/ppc4xx.h @@ -42,11 +42,13 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, + MemoryRegion ram_memories[], target_phys_addr_t ram_bases[], target_phys_addr_t ram_sizes[], const unsigned int sdram_bank_sizes[]); void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, + MemoryRegion ram_memories[], target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, int do_init); diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 1af5f2e79f..349f046b2f 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -25,6 +25,7 @@ #include "ppc.h" #include "ppc4xx.h" #include "qemu-log.h" +#include "exec-memory.h" //#define DEBUG_MMIO //#define DEBUG_UNASSIGNED @@ -313,6 +314,8 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; struct ppc4xx_sdram_t { uint32_t addr; int nbanks; + MemoryRegion containers[4]; /* used for clipping */ + MemoryRegion *ram_memories; target_phys_addr_t ram_bases[4]; target_phys_addr_t ram_sizes[4]; uint32_t besr0; @@ -395,16 +398,22 @@ static target_ulong sdram_size (uint32_t bcr) return size; } -static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) +static void sdram_set_bcr(ppc4xx_sdram_t *sdram, + uint32_t *bcrp, uint32_t bcr, int enabled) { + unsigned n = bcrp - sdram->bcr; + if (*bcrp & 0x00000001) { /* Unmap RAM */ #ifdef DEBUG_SDRAM printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", __func__, sdram_base(*bcrp), sdram_size(*bcrp)); #endif - cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), + &sdram->containers[n]); + memory_region_del_subregion(&sdram->containers[n], + &sdram->ram_memories[n]); + memory_region_destroy(&sdram->containers[n]); } *bcrp = bcr & 0xFFDEE001; if (enabled && (bcr & 0x00000001)) { @@ -412,8 +421,13 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", __func__, sdram_base(bcr), sdram_size(bcr)); #endif - cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), - sdram_base(bcr) | IO_MEM_RAM); + memory_region_init(&sdram->containers[n], "sdram-containers", + sdram_size(bcr)); + memory_region_add_subregion(&sdram->containers[n], 0, + &sdram->ram_memories[n]); + memory_region_add_subregion(get_system_memory(), + sdram_base(bcr), + &sdram->containers[n]); } } @@ -423,11 +437,12 @@ static void sdram_map_bcr (ppc4xx_sdram_t *sdram) for (i = 0; i < sdram->nbanks; i++) { if (sdram->ram_sizes[i] != 0) { - sdram_set_bcr(&sdram->bcr[i], + sdram_set_bcr(sdram, + &sdram->bcr[i], sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), 1); } else { - sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); + sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0); } } } @@ -441,9 +456,8 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); #endif - cpu_register_physical_memory(sdram_base(sdram->bcr[i]), - sdram_size(sdram->bcr[i]), - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), + &sdram->ram_memories[i]); } } @@ -568,16 +582,16 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) sdram->pmit = (val & 0xF8000000) | 0x07C00000; break; case 0x40: /* SDRAM_B0CR */ - sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); + sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000); break; case 0x44: /* SDRAM_B1CR */ - sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); + sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000); break; case 0x48: /* SDRAM_B2CR */ - sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); + sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000); break; case 0x4C: /* SDRAM_B3CR */ - sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); + sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000); break; case 0x80: /* SDRAM_TR */ sdram->tr = val & 0x018FC01F; @@ -621,6 +635,7 @@ static void sdram_reset (void *opaque) } void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, + MemoryRegion *ram_memories, target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, int do_init) @@ -630,6 +645,7 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, sdram = g_malloc0(sizeof(ppc4xx_sdram_t)); sdram->irq = irq; sdram->nbanks = nbanks; + sdram->ram_memories = ram_memories; memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t)); @@ -653,11 +669,13 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, * must be one of a small set of sizes. The number of banks and the supported * sizes varies by SoC. */ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, + MemoryRegion ram_memories[], target_phys_addr_t ram_bases[], target_phys_addr_t ram_sizes[], const unsigned int sdram_bank_sizes[]) { ram_addr_t size_left = ram_size; + ram_addr_t base = 0; int i; int j; @@ -668,8 +686,10 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, if (bank_size <= size_left) { char name[32]; snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); - ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size); + memory_region_init_ram(&ram_memories[i], NULL, name, bank_size); + ram_bases[i] = base; ram_sizes[i] = bank_size; + base += ram_size; size_left -= bank_size; break; } diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 4727e0790c..fbd443d90f 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -146,6 +146,7 @@ static void ppc_core99_init (ram_addr_t ram_size, MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem; + MemoryRegion *escc_bar = g_new(MemoryRegion, 1); MemoryRegion *ide_mem[3]; int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; @@ -328,6 +329,8 @@ static void ppc_core99_init (ram_addr_t ram_size, escc_mem = escc_init(0x80013000, pic[0x25], pic[0x24], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); + memory_region_init_alias(escc_bar, "escc-bar", + escc_mem, 0, memory_region_size(escc_mem)); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); @@ -350,7 +353,7 @@ static void ppc_core99_init (ram_addr_t ram_size, adb_mouse_init(&adb_bus); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem, - dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_mem); + dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index 0071fc950e..235d2efc7b 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -83,7 +83,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, MacIONVRAMState *nvr; int bios_size; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem; - MemoryRegion *escc_mem, *ide_mem[2]; + MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2]; uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; @@ -241,6 +241,8 @@ static void ppc_heathrow_init (ram_addr_t ram_size, escc_mem = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); + memory_region_init_alias(escc_bar, "escc-bar", + escc_mem, 0, memory_region_size(escc_mem)); for(i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); @@ -269,7 +271,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, pmac_format_nvram_partition(nvr, 0x2000); macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem, - dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_mem); + dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar); if (usb_enabled) { usb_ohci_init_pci(pci_bus, -1); diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 6a9f97975d..4390aeb559 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -274,6 +274,16 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base) s->reg); } +static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) +{ + cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, + IO_MEM_UNASSIGNED); + cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, + IO_MEM_UNASSIGNED); + cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, + IO_MEM_UNASSIGNED); +} + #include "exec-memory.h" static int e500_pcihost_initfn(SysBusDevice *dev) @@ -304,7 +314,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev) DEVICE_LITTLE_ENDIAN); s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s, DEVICE_BIG_ENDIAN); - sysbus_init_mmio_cb(dev, PCIE500_ALL_SIZE, e500_pci_map); + sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap); return 0; } diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index d00edc6177..2aa876001e 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -1923,7 +1923,7 @@ static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, else ch = ~value; if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); break; case ICSR0: s->status[0] &= ~(value & 0x66); @@ -1598,7 +1598,7 @@ static int qxl_init_primary(PCIDevice *dev) ram_size = 32 * 1024 * 1024; } vga_common_init(vga, ram_size); - vga_init(vga); + vga_init(vga, pci_address_space(dev)); register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga); register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga); register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga); diff --git a/hw/realview_gic.c b/hw/realview_gic.c index 43a2a0d5ed..cd6a44d9d0 100644 --- a/hw/realview_gic.c +++ b/hw/realview_gic.c @@ -23,39 +23,37 @@ gic_get_current_cpu(void) typedef struct { gic_state gic; - int iomemtype; + MemoryRegion iomem; + MemoryRegion container; } RealViewGICState; -static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset) +static uint64_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset, + unsigned size) { gic_state *s = (gic_state *)opaque; return gic_cpu_read(s, gic_get_current_cpu(), offset); } static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { gic_state *s = (gic_state *)opaque; gic_cpu_write(s, gic_get_current_cpu(), offset, value); } -static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = { - realview_gic_cpu_read, - realview_gic_cpu_read, - realview_gic_cpu_read +static const MemoryRegionOps realview_gic_cpu_ops = { + .read = realview_gic_cpu_read, + .write = realview_gic_cpu_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = { - realview_gic_cpu_write, - realview_gic_cpu_write, - realview_gic_cpu_write -}; - -static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base) +static void realview_gic_map_setup(RealViewGICState *s) { - RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); - cpu_register_physical_memory(base, 0x1000, s->iomemtype); - cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype); + memory_region_init(&s->container, "realview-gic-container", 0x2000); + memory_region_init_io(&s->iomem, &realview_gic_cpu_ops, &s->gic, + "realview-gic", 0x1000); + memory_region_add_subregion(&s->container, 0, &s->iomem); + memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem); } static int realview_gic_init(SysBusDevice *dev) @@ -63,10 +61,8 @@ static int realview_gic_init(SysBusDevice *dev) RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev); gic_init(&s->gic); - s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn, - realview_gic_cpu_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map); + realview_gic_map_setup(s); + sysbus_init_mmio_region(dev, &s->container); return 0; } diff --git a/hw/serial.c b/hw/serial.c index 222e356bed..ed7fd0aae0 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -274,7 +274,7 @@ static void serial_update_parameters(SerialState *s) ssp.data_bits = data_bits; ssp.stop_bits = stop_bits; s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; - qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); DPRINTF("speed=%d parity=%c data=%d stop=%d\n", speed, parity, data_bits, stop_bits); @@ -287,7 +287,7 @@ static void serial_update_msl(SerialState *s) qemu_del_timer(s->modem_status_poll); - if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { + if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { s->poll_msl = -1; return; } @@ -334,7 +334,7 @@ static void serial_xmit(void *opaque) if (s->mcr & UART_MCR_LOOP) { /* in loopback mode, say that we just received a char */ serial_receive1(s, &s->tsr, 1); - } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) { + } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { s->tsr_retry++; qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); @@ -467,7 +467,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) break_enable = (val >> 6) & 1; if (break_enable != s->last_break_enable) { s->last_break_enable = break_enable; - qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, &break_enable); } } @@ -482,7 +482,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) if (s->poll_msl >= 0 && old_mcr != s->mcr) { - qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); + qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); @@ -491,7 +491,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) if (val & UART_MCR_DTR) flags |= CHR_TIOCM_DTR; - qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); + qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); /* Update the modem status after a one-character-send wait-time, since there may be a response from the device/computer at the other end of the serial line */ qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); diff --git a/hw/sh_pci.c b/hw/sh_pci.c index cd8650143c..76061bb756 100644 --- a/hw/sh_pci.c +++ b/hw/sh_pci.c @@ -33,13 +33,16 @@ typedef struct SHPCIState { PCIBus *bus; PCIDevice *dev; qemu_irq irq[4]; - int memconfig; + MemoryRegion memconfig_p4; + MemoryRegion memconfig_a7; + MemoryRegion isa; uint32_t par; uint32_t mbr; uint32_t iobr; } SHPCIState; -static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) +static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val, + unsigned size) { SHPCIState *pcic = p; switch(addr) { @@ -54,10 +57,10 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) break; case 0x1c8: if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { - cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000, - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &pcic->isa); pcic->iobr = val & 0xfffc0001; - isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000); + memory_region_add_subregion(get_system_memory(), + pcic->iobr & 0xfffc0000, &pcic->isa); } break; case 0x220: @@ -66,7 +69,8 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) } } -static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) +static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr, + unsigned size) { SHPCIState *pcic = p; switch(addr) { @@ -84,14 +88,14 @@ static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) return 0; } -typedef struct { - CPUReadMemoryFunc * const r[3]; - CPUWriteMemoryFunc * const w[3]; -} MemOp; - -static MemOp sh_pci_reg = { - { NULL, NULL, sh_pci_reg_read }, - { NULL, NULL, sh_pci_reg_write }, +static const MemoryRegionOps sh_pci_reg_ops = { + .read = sh_pci_reg_read, + .write = sh_pci_reg_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static int sh_pci_map_irq(PCIDevice *d, int irq_num) @@ -110,11 +114,23 @@ static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base) { SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); - cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig); - cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig); - + memory_region_add_subregion(get_system_memory(), + P4ADDR(base), + &s->memconfig_p4); + memory_region_add_subregion(get_system_memory(), + A7ADDR(base), + &s->memconfig_a7); s->iobr = 0xfe240000; - isa_mmio_init(s->iobr, 0x40000); + memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa); +} + +static void sh_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) +{ + SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); + + memory_region_del_subregion(get_system_memory(), &s->memconfig_p4); + memory_region_del_subregion(get_system_memory(), &s->memconfig_a7); + memory_region_del_subregion(get_system_memory(), &s->isa); } static int sh_pci_init_device(SysBusDevice *dev) @@ -132,9 +148,14 @@ static int sh_pci_init_device(SysBusDevice *dev) get_system_memory(), get_system_io(), PCI_DEVFN(0, 0), 4); - s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, - s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio_cb(dev, 0x224, sh_pci_map); + memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s, + "sh_pci", 0x224); + memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_a7, + 0, 0x224); + isa_mmio_setup(&s->isa, 0x40000); + sysbus_init_mmio_cb2(dev, sh_pci_map, sh_pci_unmap); + sysbus_init_mmio_region(dev, &s->memconfig_a7); + sysbus_init_mmio_region(dev, &s->isa); s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host"); return 0; } diff --git a/hw/sh_serial.c b/hw/sh_serial.c index 1767c97fcc..a20c59ef77 100644 --- a/hw/sh_serial.c +++ b/hw/sh_serial.c @@ -105,7 +105,7 @@ static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val) case 0x0c: /* FTDR / TDR */ if (s->chr) { ch = val; - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); } s->dr = val; s->flags &= ~SH_SERIAL_FLAG_TDE; diff --git a/hw/spapr_vty.c b/hw/spapr_vty.c index 6fc0105eac..f5046d9183 100644 --- a/hw/spapr_vty.c +++ b/hw/spapr_vty.c @@ -50,8 +50,8 @@ void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len) { VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)sdev; - /* FIXME: should check the qemu_chr_write() return value */ - qemu_chr_write(dev->chardev, buf, len); + /* FIXME: should check the qemu_chr_fe_write() return value */ + qemu_chr_fe_write(dev->chardev, buf, len); } static int spapr_vty_init(VIOsPAPRDevice *sdev) diff --git a/hw/strongarm.c b/hw/strongarm.c index 3a7fd6da8f..6097ea2c18 100644 --- a/hw/strongarm.c +++ b/hw/strongarm.c @@ -980,7 +980,7 @@ static void strongarm_uart_update_parameters(StrongARMUARTState *s) ssp.stop_bits = stop_bits; s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; if (s->chr) { - qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); + qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); } DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, @@ -1067,7 +1067,7 @@ static void strongarm_uart_tx(void *opaque) if (s->utcr3 & UTCR3_LBM) /* loopback */ { strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); } else if (s->chr) { - qemu_chr_write(s->chr, &s->tx_fifo[s->tx_start], 1); + qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1); } s->tx_start = (s->tx_start + 1) % 8; diff --git a/hw/syborg_serial.c b/hw/syborg_serial.c index 4d0ec04e31..c83f82c36e 100644 --- a/hw/syborg_serial.c +++ b/hw/syborg_serial.c @@ -119,7 +119,7 @@ static void do_dma_tx(SyborgSerialState *s, uint32_t count) /* optimize later. Now, 1 byte per iteration */ while (count--) { cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1); - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); s->dma_tx_ptr++; } } else { @@ -203,7 +203,7 @@ static void syborg_serial_write(void *opaque, target_phys_addr_t offset, case SERIAL_DATA: ch = value; if (s->chr) - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); break; case SERIAL_INT_ENABLE: s->int_enable = value; diff --git a/hw/sysbus.c b/hw/sysbus.c index f8f1746658..f39768b6a2 100644 --- a/hw/sysbus.c +++ b/hw/sysbus.c @@ -53,6 +53,8 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr) if (dev->mmio[n].memory) { memory_region_del_subregion(get_system_memory(), dev->mmio[n].memory); + } else if (dev->mmio[n].unmap) { + dev->mmio[n].unmap(dev, dev->mmio[n].addr); } else { cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size, IO_MEM_UNASSIGNED); @@ -105,16 +107,17 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, dev->mmio[n].iofunc = iofunc; } -void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size, - mmio_mapfunc cb) +void sysbus_init_mmio_cb2(SysBusDevice *dev, + mmio_mapfunc cb, mmio_mapfunc unmap) { int n; assert(dev->num_mmio < QDEV_MAX_MMIO); n = dev->num_mmio++; dev->mmio[n].addr = -1; - dev->mmio[n].size = size; + dev->mmio[n].size = 0; dev->mmio[n].cb = cb; + dev->mmio[n].unmap = unmap; } void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory) diff --git a/hw/sysbus.h b/hw/sysbus.h index 5f62e2da31..b87c6c5aab 100644 --- a/hw/sysbus.h +++ b/hw/sysbus.h @@ -23,6 +23,7 @@ struct SysBusDevice { target_phys_addr_t addr; target_phys_addr_t size; mmio_mapfunc cb; + mmio_mapfunc unmap; ram_addr_t iofunc; MemoryRegion *memory; } mmio[QDEV_MAX_MMIO]; @@ -46,8 +47,8 @@ void sysbus_register_withprop(SysBusDeviceInfo *info); void *sysbus_new(void); void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, ram_addr_t iofunc); -void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size, - mmio_mapfunc cb); +void sysbus_init_mmio_cb2(SysBusDevice *dev, + mmio_mapfunc cb, mmio_mapfunc unmap); void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory); void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p); void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target); diff --git a/hw/tusb6010.c b/hw/tusb6010.c index d7ae527a53..b2bf35934d 100644 --- a/hw/tusb6010.c +++ b/hw/tusb6010.c @@ -23,10 +23,10 @@ #include "usb.h" #include "omap.h" #include "irq.h" -#include "devices.h" +#include "tusb6010.h" struct TUSBState { - int iomemtype[2]; + MemoryRegion iomem[2]; qemu_irq irq; MUSBState *musb; QEMUTimer *otg_timer; @@ -234,14 +234,14 @@ struct TUSBState { #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) #define TUSB_PROD_TEST_RESET_VAL 0xa596 -int tusb6010_sync_io(TUSBState *s) +MemoryRegion *tusb6010_sync_io(TUSBState *s) { - return s->iomemtype[0]; + return &s->iomem[0]; } -int tusb6010_async_io(TUSBState *s) +MemoryRegion *tusb6010_async_io(TUSBState *s) { - return s->iomemtype[1]; + return &s->iomem[1]; } static void tusb_intr_update(TUSBState *s) @@ -647,16 +647,12 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const tusb_async_readfn[] = { - tusb_async_readb, - tusb_async_readh, - tusb_async_readw, -}; - -static CPUWriteMemoryFunc * const tusb_async_writefn[] = { - tusb_async_writeb, - tusb_async_writeh, - tusb_async_writew, +static const MemoryRegionOps tusb_async_ops = { + .old_mmio = { + .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, }, + .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void tusb_otg_tick(void *opaque) @@ -739,8 +735,8 @@ TUSBState *tusb6010_init(qemu_irq intr) s->mask = 0xffffffff; s->intr = 0x00000000; s->otg_timer_val = 0; - s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn, - tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async", + UINT32_MAX); s->irq = intr; s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s); s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s); diff --git a/hw/tusb6010.h b/hw/tusb6010.h new file mode 100644 index 0000000000..b85ee86215 --- /dev/null +++ b/hw/tusb6010.h @@ -0,0 +1,28 @@ +/* + * tusb6010 interfaces + * + * Copyright 2011 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Avi Kivity <avi@redhat.com> + * + * Derived from hw/devices.h. + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#ifndef TUSB6010_H +#define TUSB6010_H + +#include "targphys.h" +#include "memory.h" + +typedef struct TUSBState TUSBState; +TUSBState *tusb6010_init(qemu_irq intr); +MemoryRegion *tusb6010_sync_io(TUSBState *s); +MemoryRegion *tusb6010_async_io(TUSBState *s); +void tusb6010_power(TUSBState *s, int on); + +#endif diff --git a/hw/usb-serial.c b/hw/usb-serial.c index bf2b775e83..7dbf6dfc6d 100644 --- a/hw/usb-serial.c +++ b/hw/usb-serial.c @@ -203,7 +203,7 @@ static uint8_t usb_get_modem_lines(USBSerialState *s) int flags; uint8_t ret; - if (qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) + if (qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) return FTDI_CTS|FTDI_DSR|FTDI_RLSD; ret = 0; @@ -263,7 +263,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p, case DeviceOutVendor | FTDI_SET_MDM_CTRL: { static int flags; - qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); + qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); if (value & FTDI_SET_RTS) { if (value & FTDI_RTS) flags |= CHR_TIOCM_RTS; @@ -276,7 +276,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p, else flags &= ~CHR_TIOCM_DTR; } - qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); + qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); break; } case DeviceOutVendor | FTDI_SET_FLOW_CTRL: @@ -295,7 +295,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p, divisor = 1; s->params.speed = (48000000 / 2) / (8 * divisor + subdivisor8); - qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params); + qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params); break; } case DeviceOutVendor | FTDI_SET_DATA: @@ -324,7 +324,7 @@ static int usb_serial_handle_control(USBDevice *dev, USBPacket *p, DPRINTF("unsupported stop bits %d\n", value & FTDI_STOP); goto fail; } - qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params); + qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params); /* TODO: TX ON/OFF */ break; case DeviceInVendor | FTDI_GET_MDM_ST: @@ -371,7 +371,7 @@ static int usb_serial_handle_data(USBDevice *dev, USBPacket *p) goto fail; for (i = 0; i < p->iov.niov; i++) { iov = p->iov.iov + i; - qemu_chr_write(s->cs, iov->iov_base, iov->iov_len); + qemu_chr_fe_write(s->cs, iov->iov_base, iov->iov_len); } break; @@ -428,7 +428,7 @@ static void usb_serial_handle_destroy(USBDevice *dev) { USBSerialState *s = (USBSerialState *)dev; - qemu_chr_close(s->cs); + qemu_chr_delete(s->cs); } static int usb_serial_can_read(void *opaque) @@ -538,7 +538,7 @@ static USBDevice *usb_serial_init(const char *filename) filename++; snprintf(label, sizeof(label), "usbserial%d", index++); - cdrv = qemu_chr_open(label, filename, NULL); + cdrv = qemu_chr_new(label, filename, NULL); if (!cdrv) return NULL; @@ -561,7 +561,7 @@ static USBDevice *usb_braille_init(const char *unused) USBDevice *dev; CharDriverState *cdrv; - cdrv = qemu_chr_open("braille", "braille", NULL); + cdrv = qemu_chr_new("braille", "braille", NULL); if (!cdrv) return NULL; diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index e1d5c0bf5a..98e56f1610 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -16,7 +16,9 @@ typedef struct { SysBusDevice busdev; qemu_irq irq[4]; int realview; - int mem_config; + MemoryRegion mem_config; + MemoryRegion mem_config2; + MemoryRegion isa; } PCIVPBState; static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr) @@ -24,55 +26,24 @@ static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr) return addr & 0xffffff; } -static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr, - uint32_t val) +static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { - pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1); + pci_data_write(opaque, vpb_pci_config_addr(addr), val, size); } -static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2); -} - -static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, - uint32_t val) -{ - pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4); -} - -static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr) -{ - uint32_t val; - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1); - return val; -} - -static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr) -{ - uint32_t val; - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2); - return val; -} - -static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr) +static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr, + unsigned size) { uint32_t val; - val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4); + val = pci_data_read(opaque, vpb_pci_config_addr(addr), size); return val; } -static CPUWriteMemoryFunc * const pci_vpb_config_write[] = { - &pci_vpb_config_writeb, - &pci_vpb_config_writew, - &pci_vpb_config_writel, -}; - -static CPUReadMemoryFunc * const pci_vpb_config_read[] = { - &pci_vpb_config_readb, - &pci_vpb_config_readw, - &pci_vpb_config_readl, +static const MemoryRegionOps pci_vpb_config_ops = { + .read = pci_vpb_config_read, + .write = pci_vpb_config_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int pci_vpb_map_irq(PCIDevice *d, int irq_num) @@ -87,17 +58,35 @@ static void pci_vpb_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num], level); } + static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) { PCIVPBState *s = (PCIVPBState *)dev; /* Selfconfig area. */ - cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config); + memory_region_add_subregion(get_system_memory(), base + 0x01000000, + &s->mem_config); + /* Normal config area. */ + memory_region_add_subregion(get_system_memory(), base + 0x02000000, + &s->mem_config2); + + if (s->realview) { + /* IO memory area. */ + memory_region_add_subregion(get_system_memory(), base + 0x03000000, + &s->isa); + } +} + +static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base) +{ + PCIVPBState *s = (PCIVPBState *)dev; + /* Selfconfig area. */ + memory_region_del_subregion(get_system_memory(), &s->mem_config); /* Normal config area. */ - cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config); + memory_region_del_subregion(get_system_memory(), &s->mem_config2); if (s->realview) { /* IO memory area. */ - isa_mmio_init(base + 0x03000000, 0x00100000); + memory_region_del_subregion(get_system_memory(), &s->isa); } } @@ -117,10 +106,15 @@ static int pci_vpb_init(SysBusDevice *dev) /* ??? Register memory space. */ - s->mem_config = cpu_register_io_memory(pci_vpb_config_read, - pci_vpb_config_write, bus, - DEVICE_LITTLE_ENDIAN); - sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map); + memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus, + "pci-vpb-selfconfig", 0x1000000); + memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus, + "pci-vpb-config", 0x1000000); + if (s->realview) { + isa_mmio_setup(&s->isa, 0x0100000); + } + + sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap); pci_create_simple(bus, -1, "versatile_pci_host"); return 0; diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c index b93497803c..f8984c62cb 100644 --- a/hw/vga-isa-mm.c +++ b/hw/vga-isa-mm.c @@ -27,7 +27,6 @@ #include "vga_int.h" #include "pixel_ops.h" #include "qemu-timer.h" -#include "exec-memory.h" typedef struct ISAVGAMMState { VGACommonState vga; @@ -97,7 +96,8 @@ static const MemoryRegionOps vga_mm_ctrl_ops = { }; static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift) + target_phys_addr_t ctrl_base, int it_shift, + MemoryRegion *address_space) { MemoryRegion *s_ioport_ctrl, *vga_io_memory; @@ -113,26 +113,27 @@ static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base, vmstate_register(NULL, 0, &vmstate_vga_common, s); - memory_region_add_subregion(get_system_memory(), ctrl_base, s_ioport_ctrl); + memory_region_add_subregion(address_space, ctrl_base, s_ioport_ctrl); s->vga.bank_offset = 0; - memory_region_add_subregion(get_system_memory(), + memory_region_add_subregion(address_space, vram_base + 0x000a0000, vga_io_memory); memory_region_set_coalescing(vga_io_memory); } int isa_vga_mm_init(target_phys_addr_t vram_base, - target_phys_addr_t ctrl_base, int it_shift) + target_phys_addr_t ctrl_base, int it_shift, + MemoryRegion *address_space) { ISAVGAMMState *s; s = g_malloc0(sizeof(*s)); vga_common_init(&s->vga, VGA_RAM_SIZE); - vga_mm_init(s, vram_base, ctrl_base, it_shift); + vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space); s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, s->vga.screen_dump, s->vga.text_update, s); - vga_init_vbe(&s->vga); + vga_init_vbe(&s->vga, address_space); return 0; } diff --git a/hw/vga-isa.c b/hw/vga-isa.c index fef7f58f28..0d199015d7 100644 --- a/hw/vga-isa.c +++ b/hw/vga-isa.c @@ -28,7 +28,6 @@ #include "pixel_ops.h" #include "qemu-timer.h" #include "loader.h" -#include "exec-memory.h" typedef struct ISAVGAState { ISADevice dev; @@ -51,7 +50,7 @@ static int vga_initfn(ISADevice *dev) vga_common_init(s, VGA_RAM_SIZE); vga_io_memory = vga_init_io(s); - memory_region_add_subregion_overlap(get_system_memory(), + memory_region_add_subregion_overlap(isa_address_space(dev), isa_mem_base + 0x000a0000, vga_io_memory, 1); memory_region_set_coalescing(vga_io_memory); @@ -68,7 +67,7 @@ static int vga_initfn(ISADevice *dev) s->ds = graphic_console_init(s->update, s->invalidate, s->screen_dump, s->text_update, s); - vga_init_vbe(s); + vga_init_vbe(s, isa_address_space(dev)); /* ROM BIOS */ rom_add_vga(VGABIOS_FILENAME); return 0; diff --git a/hw/vga-pci.c b/hw/vga-pci.c index c67be0abeb..3c8bcb00b7 100644 --- a/hw/vga-pci.c +++ b/hw/vga-pci.c @@ -54,7 +54,7 @@ static int pci_vga_initfn(PCIDevice *dev) // vga + console init vga_common_init(s, VGA_RAM_SIZE); - vga_init(s); + vga_init(s, pci_address_space(dev)); s->ds = graphic_console_init(s->update, s->invalidate, s->screen_dump, s->text_update, s); @@ -64,7 +64,7 @@ static int pci_vga_initfn(PCIDevice *dev) if (!dev->rom_bar) { /* compatibility with pc-0.13 and older */ - vga_init_vbe(s); + vga_init_vbe(s, pci_address_space(dev)); } return 0; @@ -28,7 +28,6 @@ #include "vga_int.h" #include "pixel_ops.h" #include "qemu-timer.h" -#include "exec-memory.h" //#define DEBUG_VGA //#define DEBUG_VGA_MEM @@ -153,6 +152,48 @@ static void vga_screen_dump(void *opaque, const char *filename); static char *screen_dump_filename; static DisplayChangeListener *screen_dump_dcl; +static void vga_update_memory_access(VGACommonState *s) +{ + MemoryRegion *region, *old_region = s->chain4_alias; + target_phys_addr_t base, offset, size; + + s->chain4_alias = NULL; + + if ((s->sr[0x02] & 0xf) == 0xf && s->sr[0x04] & 0x08) { + offset = 0; + switch ((s->gr[6] >> 2) & 3) { + case 0: + base = 0xa0000; + size = 0x20000; + break; + case 1: + base = 0xa0000; + size = 0x10000; + offset = s->bank_offset; + break; + case 2: + base = 0xb0000; + size = 0x8000; + break; + case 3: + base = 0xb8000; + size = 0x8000; + break; + } + region = g_malloc(sizeof(*region)); + memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size); + memory_region_add_subregion_overlap(s->legacy_address_space, base, + region, 2); + s->chain4_alias = region; + } + if (old_region) { + memory_region_del_subregion(s->legacy_address_space, old_region); + memory_region_destroy(old_region); + g_free(old_region); + s->plane_updated = 0xf; + } +} + static void vga_dumb_update_retrace_info(VGACommonState *s) { (void) s; @@ -446,6 +487,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) #endif s->sr[s->sr_index] = val & sr_mask[s->sr_index]; if (s->sr_index == 1) s->update_retrace_info(s); + vga_update_memory_access(s); break; case 0x3c7: s->dac_read_index = val; @@ -473,6 +515,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) printf("vga: write GR%x = 0x%02x\n", s->gr_index, val); #endif s->gr[s->gr_index] = val & gr_mask[s->gr_index]; + vga_update_memory_access(s); break; case 0x3b4: case 0x3d4: @@ -606,6 +649,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val) } s->vbe_regs[s->vbe_index] = val; s->bank_offset = (val << 16); + vga_update_memory_access(s); break; case VBE_DISPI_INDEX_ENABLE: if ((val & VBE_DISPI_ENABLED) && @@ -665,6 +709,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val) } s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0; s->vbe_regs[s->vbe_index] = val; + vga_update_memory_access(s); break; case VBE_DISPI_INDEX_VIRT_WIDTH: { @@ -1239,7 +1284,7 @@ static void vga_draw_text(VGACommonState *s, int full_update) s->font_offsets[1] = offset; full_update = 1; } - if (s->plane_updated & (1 << 2)) { + if (s->plane_updated & (1 << 2) || s->chain4_alias) { /* if the plane 2 was modified since the last display, it indicates the font may have been modified */ s->plane_updated = 0; @@ -1533,12 +1578,6 @@ void vga_dirty_log_stop(VGACommonState *s) memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA); } -void vga_dirty_log_restart(VGACommonState *s) -{ - vga_dirty_log_stop(s); - vga_dirty_log_start(s); -} - /* * graphic modes */ @@ -1892,6 +1931,7 @@ void vga_common_reset(VGACommonState *s) memset(&s->retrace_info, 0, sizeof (s->retrace_info)); break; } + vga_update_memory_access(s); } static void vga_reset(void *opaque) @@ -2241,7 +2281,7 @@ MemoryRegion *vga_init_io(VGACommonState *s) return vga_mem; } -void vga_init(VGACommonState *s) +void vga_init(VGACommonState *s, MemoryRegion *address_space) { MemoryRegion *vga_io_memory; @@ -2249,19 +2289,21 @@ void vga_init(VGACommonState *s) s->bank_offset = 0; + s->legacy_address_space = address_space; + vga_io_memory = vga_init_io(s); - memory_region_add_subregion_overlap(get_system_memory(), + memory_region_add_subregion_overlap(address_space, isa_mem_base + 0x000a0000, vga_io_memory, 1); memory_region_set_coalescing(vga_io_memory); } -void vga_init_vbe(VGACommonState *s) +void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory) { #ifdef CONFIG_BOCHS_VBE /* XXX: use optimized standard vga accesses */ - memory_region_add_subregion(get_system_memory(), + memory_region_add_subregion(system_memory, VBE_DISPI_LFB_PHYSICAL_ADDRESS, &s->vram); s->vbe_mapped = 1; diff --git a/hw/vga_int.h b/hw/vga_int.h index 100d98c8bf..99287dde9b 100644 --- a/hw/vga_int.h +++ b/hw/vga_int.h @@ -105,11 +105,12 @@ typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s); typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s); typedef struct VGACommonState { + MemoryRegion *legacy_address_space; uint8_t *vram_ptr; MemoryRegion vram; uint32_t vram_size; uint32_t latch; - uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */ + MemoryRegion *chain4_alias; uint8_t sr_index; uint8_t sr[256]; uint8_t gr_index; @@ -131,7 +132,6 @@ typedef struct VGACommonState { int dac_8bit; uint8_t palette[768]; int32_t bank_offset; - MemoryRegion *vga_io_memory; int (*get_bpp)(struct VGACommonState *s); void (*get_offsets)(struct VGACommonState *s, uint32_t *pline_offset, @@ -187,13 +187,12 @@ static inline int c6_to_8(int v) } void vga_common_init(VGACommonState *s, int vga_ram_size); -void vga_init(VGACommonState *s); +void vga_init(VGACommonState *s, MemoryRegion *address_space); MemoryRegion *vga_init_io(VGACommonState *s); void vga_common_reset(VGACommonState *s); void vga_dirty_log_start(VGACommonState *s); void vga_dirty_log_stop(VGACommonState *s); -void vga_dirty_log_restart(VGACommonState *s); extern const VMStateDescription vmstate_vga_common; uint32_t vga_ioport_read(void *opaque, uint32_t addr); @@ -217,7 +216,7 @@ void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1, unsigned int color_xor); int vga_ioport_invalid(VGACommonState *s, uint32_t addr); -void vga_init_vbe(VGACommonState *s); +void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space); extern const uint8_t sr_mask[8]; extern const uint8_t gr_mask[16]; diff --git a/hw/virtio-console.c b/hw/virtio-console.c index fe5e188bf4..d3351c83ff 100644 --- a/hw/virtio-console.c +++ b/hw/virtio-console.c @@ -27,7 +27,7 @@ static ssize_t flush_buf(VirtIOSerialPort *port, const uint8_t *buf, size_t len) VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); ssize_t ret; - ret = qemu_chr_write(vcon->chr, buf, len); + ret = qemu_chr_fe_write(vcon->chr, buf, len); trace_virtio_console_flush_buf(port->id, len, ret); if (ret < 0) { @@ -52,7 +52,7 @@ static void guest_open(VirtIOSerialPort *port) { VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); - qemu_chr_guest_open(vcon->chr); + qemu_chr_fe_open(vcon->chr); } /* Callback function that's called when the guest closes the port */ @@ -60,7 +60,7 @@ static void guest_close(VirtIOSerialPort *port) { VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port); - qemu_chr_guest_close(vcon->chr); + qemu_chr_fe_close(vcon->chr); } /* Readiness of the guest to accept data on a port */ diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index a840cbd4b7..52d2d26f1b 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -27,8 +27,7 @@ #include "pci.h" #include "vmware_vga.h" -#define VERBOSE -#undef DIRECT_VRAM +#undef VERBOSE #define HW_RECT_ACCEL #define HW_FILL_ACCEL #define HW_MOUSE_ACCEL @@ -292,7 +291,6 @@ enum { static inline void vmsvga_update_rect(struct vmsvga_state_s *s, int x, int y, int w, int h) { -#ifndef DIRECT_VRAM int line; int bypl; int width; @@ -323,23 +321,17 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s, for (; line > 0; line --, src += bypl, dst += bypl) memcpy(dst, src, width); -#endif dpy_update(s->vga.ds, x, y, w, h); } static inline void vmsvga_update_screen(struct vmsvga_state_s *s) { -#ifndef DIRECT_VRAM - memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height); -#endif - + memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, + s->bypp * s->width * s->height); dpy_update(s->vga.ds, 0, 0, s->width, s->height); } -#ifdef DIRECT_VRAM -# define vmsvga_update_rect_delayed vmsvga_update_rect -#else static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, int x, int y, int w, int h) { @@ -350,7 +342,6 @@ static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, rect->w = w; rect->h = h; } -#endif static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) { @@ -372,32 +363,23 @@ static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, int x0, int y0, int x1, int y1, int w, int h) { -# ifdef DIRECT_VRAM - uint8_t *vram = ds_get_data(s->ds); -# else uint8_t *vram = s->vga.vram_ptr; -# endif int bypl = s->bypp * s->width; int width = s->bypp * w; int line = h; uint8_t *ptr[2]; -# ifdef DIRECT_VRAM - if (s->ds->dpy_copy) - qemu_console_copy(s->ds, x0, y0, x1, y1, w, h); - else -# endif - { - if (y1 > y0) { - ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); - ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); - for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) - memmove(ptr[1], ptr[0], width); - } else { - ptr[0] = vram + s->bypp * x0 + bypl * y0; - ptr[1] = vram + s->bypp * x1 + bypl * y1; - for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) - memmove(ptr[1], ptr[0], width); + if (y1 > y0) { + ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); + ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); + for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { + memmove(ptr[1], ptr[0], width); + } + } else { + ptr[0] = vram + s->bypp * x0 + bypl * y0; + ptr[1] = vram + s->bypp * x1 + bypl * y1; + for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { + memmove(ptr[1], ptr[0], width); } } @@ -409,11 +391,7 @@ static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, uint32_t c, int x, int y, int w, int h) { -# ifdef DIRECT_VRAM - uint8_t *vram = ds_get_data(s->ds); -# else uint8_t *vram = s->vga.vram_ptr; -# endif int bypp = s->bypp; int bypl = bypp * s->width; int width = bypp * w; @@ -424,31 +402,25 @@ static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, uint8_t *src; uint8_t col[4]; -# ifdef DIRECT_VRAM - if (s->ds->dpy_fill) - s->ds->dpy_fill(s->ds, x, y, w, h, c); - else -# endif - { - col[0] = c; - col[1] = c >> 8; - col[2] = c >> 16; - col[3] = c >> 24; - - if (line --) { - dst = fst; - src = col; - for (column = width; column > 0; column --) { - *(dst ++) = *(src ++); - if (src - col == bypp) - src = col; - } - dst = fst; - for (; line > 0; line --) { - dst += bypl; - memcpy(dst, fst, width); + col[0] = c; + col[1] = c >> 8; + col[2] = c >> 16; + col[3] = c >> 24; + + if (line--) { + dst = fst; + src = col; + for (column = width; column > 0; column--) { + *(dst++) = *(src++); + if (src - col == bypp) { + src = col; } } + dst = fst; + for (; line > 0; line--) { + dst += bypl; + memcpy(dst, fst, width); + } } vmsvga_update_rect_delayed(s, x, y, w, h); @@ -998,46 +970,21 @@ static void vmsvga_update_display(void *opaque) } } -static void vmsvga_reset(struct vmsvga_state_s *s) +static void vmsvga_reset(DeviceState *dev) { + struct pci_vmsvga_state_s *pci = + DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev); + struct vmsvga_state_s *s = &pci->chip; + s->index = 0; s->enable = 0; s->config = 0; s->width = -1; s->height = -1; s->svgaid = SVGA_ID; - s->depth = ds_get_bits_per_pixel(s->vga.ds); - s->bypp = ds_get_bytes_per_pixel(s->vga.ds); s->cursor.on = 0; s->redraw_fifo_first = 0; s->redraw_fifo_last = 0; - switch (s->depth) { - case 8: - s->wred = 0x00000007; - s->wgreen = 0x00000038; - s->wblue = 0x000000c0; - break; - case 15: - s->wred = 0x0000001f; - s->wgreen = 0x000003e0; - s->wblue = 0x00007c00; - break; - case 16: - s->wred = 0x0000001f; - s->wgreen = 0x000007e0; - s->wblue = 0x0000f800; - break; - case 24: - s->wred = 0x00ff0000; - s->wgreen = 0x0000ff00; - s->wblue = 0x000000ff; - break; - case 32: - s->wred = 0x00ff0000; - s->wgreen = 0x0000ff00; - s->wblue = 0x000000ff; - break; - } s->syncing = 0; vga_dirty_log_start(&s->vga); @@ -1080,82 +1027,6 @@ static void vmsvga_text_update(void *opaque, console_ch_t *chardata) s->vga.text_update(&s->vga, chardata); } -#ifdef DIRECT_VRAM -static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) -{ - struct vmsvga_state_s *s = opaque; - if (addr < s->fb_size) - return *(uint8_t *) (ds_get_data(s->ds) + addr); - else - return *(uint8_t *) (s->vram_ptr + addr); -} - -static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) -{ - struct vmsvga_state_s *s = opaque; - if (addr < s->fb_size) - return *(uint16_t *) (ds_get_data(s->ds) + addr); - else - return *(uint16_t *) (s->vram_ptr + addr); -} - -static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) -{ - struct vmsvga_state_s *s = opaque; - if (addr < s->fb_size) - return *(uint32_t *) (ds_get_data(s->ds) + addr); - else - return *(uint32_t *) (s->vram_ptr + addr); -} - -static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, - uint32_t value) -{ - struct vmsvga_state_s *s = opaque; - if (addr < s->fb_size) - *(uint8_t *) (ds_get_data(s->ds) + addr) = value; - else - *(uint8_t *) (s->vram_ptr + addr) = value; -} - -static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, - uint32_t value) -{ - struct vmsvga_state_s *s = opaque; - if (addr < s->fb_size) - *(uint16_t *) (ds_get_data(s->ds) + addr) = value; - else - *(uint16_t *) (s->vram_ptr + addr) = value; -} - -static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr, - uint32_t value) -{ - struct vmsvga_state_s *s = opaque; - if (addr < s->fb_size) - *(uint32_t *) (ds_get_data(s->ds) + addr) = value; - else - *(uint32_t *) (s->vram_ptr + addr) = value; -} - -static const MemoryRegionOps vmsvga_vram_io_ops = { - .old_mmio = { - .read = { - vmsvga_vram_readb, - vmsvga_vram_readw, - vmsvga_vram_readl, - }, - .write = { - vmsvga_vram_writeb, - vmsvga_vram_writew, - vmsvga_vram_writel, - }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, -} - -#endif - static int vmsvga_post_load(void *opaque, int version_id) { struct vmsvga_state_s *s = opaque; @@ -1207,7 +1078,8 @@ static const VMStateDescription vmstate_vmware_vga = { } }; -static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size) +static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size, + MemoryRegion *address_space) { s->scratch_size = SVGA_SCRATCH_SIZE; s->scratch = g_malloc(s->scratch_size * 4); @@ -1223,10 +1095,38 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size) s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); vga_common_init(&s->vga, vga_ram_size); - vga_init(&s->vga); + vga_init(&s->vga, address_space); vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); - vmsvga_reset(s); + s->depth = ds_get_bits_per_pixel(s->vga.ds); + s->bypp = ds_get_bytes_per_pixel(s->vga.ds); + switch (s->depth) { + case 8: + s->wred = 0x00000007; + s->wgreen = 0x00000038; + s->wblue = 0x000000c0; + break; + case 15: + s->wred = 0x0000001f; + s->wgreen = 0x000003e0; + s->wblue = 0x00007c00; + break; + case 16: + s->wred = 0x0000001f; + s->wgreen = 0x000007e0; + s->wblue = 0x0000f800; + break; + case 24: + s->wred = 0x00ff0000; + s->wgreen = 0x0000ff00; + s->wblue = 0x000000ff; + break; + case 32: + s->wred = 0x00ff0000; + s->wgreen = 0x0000ff00; + s->wblue = 0x000000ff; + break; + } } static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr, @@ -1273,17 +1173,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev) DO_UPCAST(struct pci_vmsvga_state_s, card, dev); MemoryRegion *iomem; -#ifdef DIRECT_VRAM - DirectMem *directmem = g_malloc(sizeof(*directmem)); - - iomem = &directmem->mr; - memory_region_init_io(iomem, &vmsvga_vram_io_ops, &s->chip, "vmsvga", - memory_region_size(&s->chip.vga.vram)); -#else iomem = &s->chip.vga.vram; -#endif - - vga_dirty_log_restart(&s->chip.vga); s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ @@ -1293,7 +1183,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev) "vmsvga-io", 0x10); pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); - vmsvga_init(&s->chip, VGA_RAM_SIZE); + vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev)); pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem); pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, @@ -1301,7 +1191,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev) if (!dev->rom_bar) { /* compatibility with pc-0.13 and older */ - vga_init_vbe(&s->chip.vga); + vga_init_vbe(&s->chip.vga, pci_address_space(dev)); } return 0; @@ -1311,6 +1201,7 @@ static PCIDeviceInfo vmsvga_info = { .qdev.name = "vmware-svga", .qdev.size = sizeof(struct pci_vmsvga_state_s), .qdev.vmsd = &vmstate_vmware_vga, + .qdev.reset = vmsvga_reset, .no_hotplug = 1, .init = pci_vmsvga_initfn, .romfile = "vgabios-vmware.bin", diff --git a/hw/xen_console.c b/hw/xen_console.c index 99ff442f85..5789bd09a5 100644 --- a/hw/xen_console.c +++ b/hw/xen_console.c @@ -156,7 +156,7 @@ static void xencons_send(struct XenConsole *con) size = con->buffer.size - con->buffer.consumed; if (con->chr) - len = qemu_chr_write(con->chr, con->buffer.data + con->buffer.consumed, + len = qemu_chr_fe_write(con->chr, con->buffer.data + con->buffer.consumed, size); else len = size; @@ -202,7 +202,7 @@ static int con_init(struct XenDevice *xendev) con->chr = serial_hds[con->xendev.dev]; } else { snprintf(label, sizeof(label), "xencons%d", con->xendev.dev); - con->chr = qemu_chr_open(label, output, NULL); + con->chr = qemu_chr_new(label, output, NULL); } xenstore_store_pv_console_info(con->xendev.dev, con->chr); diff --git a/hw/xilinx.h b/hw/xilinx.h index 090e6f7c3d..35f35bd7fc 100644 --- a/hw/xilinx.h +++ b/hw/xilinx.h @@ -1,6 +1,5 @@ - -/* OPB Interrupt Controller. */ -qemu_irq *microblaze_pic_init_cpu(CPUState *env); +#include "qemu-common.h" +#include "net.h" static inline DeviceState * xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr) diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c index 9b94e98fe3..467a26cc9e 100644 --- a/hw/xilinx_uartlite.c +++ b/hw/xilinx_uartlite.c @@ -129,7 +129,7 @@ uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value) case R_TX: if (s->chr) - qemu_chr_write(s->chr, &ch, 1); + qemu_chr_fe_write(s->chr, &ch, 1); s->regs[addr] = value; |