diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/apb_pci.c | 26 | ||||
| -rw-r--r-- | hw/dec_pci.c | 3 | ||||
| -rw-r--r-- | hw/sparc32_dma.c | 36 |
3 files changed, 40 insertions, 25 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c index 46d5b0e8e4..ebfcd4153f 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -359,9 +359,14 @@ static void apb_pci_bridge_init(PCIBus *b) * (which is true) and thus it should be PCI_COMMAND_MEMORY. */ pci_set_word(dev->config + PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - dev->config[PCI_LATENCY_TIMER] = 0x10; - dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; + PCI_COMMAND_MEMORY); + pci_set_word(dev->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | + PCI_STATUS_DEVSEL_MEDIUM); + pci_set_byte(dev->config + PCI_REVISION_ID, 0x11); + pci_set_byte(dev->config + PCI_HEADER_TYPE, + pci_get_byte(dev->config + PCI_HEADER_TYPE) | + PCI_HEADER_TYPE_MULTI_FUNCTION); } PCIBus *pci_apb_init(target_phys_addr_t special_base, @@ -463,15 +468,14 @@ static int pbm_pci_host_init(PCIDevice *d) { pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN); pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE); - d->config[0x04] = 0x06; // command = bus master, pci mem - d->config[0x05] = 0x00; - d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error - d->config[0x07] = 0x03; // status = medium devsel - d->config[0x08] = 0x00; // revision - d->config[0x09] = 0x00; // programming i/f + pci_set_word(d->config + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_set_word(d->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | + PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); - d->config[0x0D] = 0x10; // latency_timer - d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type + pci_set_byte(d->config + PCI_HEADER_TYPE, + PCI_HEADER_TYPE_NORMAL); return 0; } diff --git a/hw/dec_pci.c b/hw/dec_pci.c index 8d059f1315..fb4973bb7c 100644 --- a/hw/dec_pci.c +++ b/hw/dec_pci.c @@ -81,9 +81,8 @@ static int dec_21154_pci_host_init(PCIDevice *d) /* PCI2PCI bridge same values as PearPC - check this */ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC); pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); - d->config[0x08] = 0x02; // revision + pci_set_byte(d->config + PCI_REVISION_ID, 0x02); pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); - d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type return 0; } diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index 6e991e0734..3ceb851e91 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -3,6 +3,9 @@ * * Copyright (c) 2006 Fabrice Bellard * + * Modifications: + * 2010-Feb-14 Artyom Tarasenko : reworked irq generation + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -125,13 +128,19 @@ static void dma_set_irq(void *opaque, int irq, int level) { DMAState *s = opaque; if (level) { - DPRINTF("Raise IRQ\n"); s->dmaregs[0] |= DMA_INTR; - qemu_irq_raise(s->irq); + if (s->dmaregs[0] & DMA_INTREN) { + DPRINTF("Raise IRQ\n"); + qemu_irq_raise(s->irq); + } } else { - s->dmaregs[0] &= ~DMA_INTR; - DPRINTF("Lower IRQ\n"); - qemu_irq_lower(s->irq); + if (s->dmaregs[0] & DMA_INTR) { + s->dmaregs[0] &= ~DMA_INTR; + if (s->dmaregs[0] & DMA_INTREN) { + DPRINTF("Lower IRQ\n"); + qemu_irq_lower(s->irq); + } + } } } @@ -142,8 +151,6 @@ void espdma_memory_read(void *opaque, uint8_t *buf, int len) DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n", s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); - DPRINTF("Raise IRQ\n"); - s->dmaregs[0] |= DMA_INTR; s->dmaregs[1] += len; } @@ -154,8 +161,6 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len) DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n", s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); - DPRINTF("Raise IRQ\n"); - s->dmaregs[0] |= DMA_INTR; s->dmaregs[1] += len; } @@ -181,9 +186,16 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) s->dmaregs[saddr], val); switch (saddr) { case 0: - if (!(val & DMA_INTREN)) { - DPRINTF("Lower IRQ\n"); - qemu_irq_lower(s->irq); + if (val & DMA_INTREN) { + if (val & DMA_INTR) { + DPRINTF("Raise IRQ\n"); + qemu_irq_raise(s->irq); + } + } else { + if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { + DPRINTF("Lower IRQ\n"); + qemu_irq_lower(s->irq); + } } if (val & DMA_RESET) { qemu_irq_raise(s->dev_reset); |