diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/acpi.c | 9 | ||||
| -rw-r--r-- | hw/adlib.c | 2 | ||||
| -rw-r--r-- | hw/baum.c | 3 | ||||
| -rw-r--r-- | hw/bt-hci-csr.c | 4 | ||||
| -rw-r--r-- | hw/bt-hci.c | 4 | ||||
| -rw-r--r-- | hw/cuda.c | 14 | ||||
| -rw-r--r-- | hw/dp8393x.c | 2 | ||||
| -rw-r--r-- | hw/fdc.c | 2 | ||||
| -rw-r--r-- | hw/i8254.c | 14 | ||||
| -rw-r--r-- | hw/i8259.c | 3 | ||||
| -rw-r--r-- | hw/ide/core.c | 2 | ||||
| -rw-r--r-- | hw/mc146818rtc.c | 16 | ||||
| -rw-r--r-- | hw/mips_timer.c | 10 | ||||
| -rw-r--r-- | hw/omap1.c | 16 | ||||
| -rw-r--r-- | hw/omap2.c | 4 | ||||
| -rw-r--r-- | hw/pcnet.c | 2 | ||||
| -rw-r--r-- | hw/pflash_cfi02.c | 4 | ||||
| -rw-r--r-- | hw/pl031.c | 6 | ||||
| -rw-r--r-- | hw/ppc.c | 18 | ||||
| -rw-r--r-- | hw/ppc405_uc.c | 4 | ||||
| -rw-r--r-- | hw/pxa2xx_timer.c | 14 | ||||
| -rw-r--r-- | hw/rc4030.c | 3 | ||||
| -rw-r--r-- | hw/rtl8139.c | 5 | ||||
| -rw-r--r-- | hw/sb16.c | 4 | ||||
| -rw-r--r-- | hw/serial.c | 6 | ||||
| -rw-r--r-- | hw/spitz.c | 3 | ||||
| -rw-r--r-- | hw/stellaris.c | 2 | ||||
| -rw-r--r-- | hw/tsc2005.c | 2 | ||||
| -rw-r--r-- | hw/tsc210x.c | 2 | ||||
| -rw-r--r-- | hw/tusb6010.c | 4 | ||||
| -rw-r--r-- | hw/usb-musb.c | 2 | ||||
| -rw-r--r-- | hw/usb-ohci.c | 10 | ||||
| -rw-r--r-- | hw/usb-uhci.c | 2 | ||||
| -rw-r--r-- | hw/vga.c | 6 | ||||
| -rw-r--r-- | hw/wdt_i6300esb.c | 2 | ||||
| -rw-r--r-- | hw/wdt_ib700.c | 2 |
36 files changed, 110 insertions, 98 deletions
@@ -79,7 +79,7 @@ static PIIX4PMState *pm_state; static uint32_t get_pmtmr(PIIX4PMState *s) { uint32_t d; - d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); + d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); return d & 0xffffff; } @@ -88,7 +88,7 @@ static int get_pmsts(PIIX4PMState *s) int64_t d; int pmsts; pmsts = s->pmsts; - d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); + d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); if (d >= s->tmr_overflow_time) s->pmsts |= TMROF_EN; return s->pmsts; @@ -105,7 +105,7 @@ static void pm_update_sci(PIIX4PMState *s) qemu_set_irq(s->irq, sci_level); /* schedule a timer interruption if needed */ if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) { - expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); + expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ); qemu_mod_timer(s->tmr_timer, expire_time); } else { qemu_del_timer(s->tmr_timer); @@ -130,7 +130,8 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) pmsts = get_pmsts(s); if (pmsts & val & TMROF_EN) { /* if TMRSTS is reset, then compute the new overflow time */ - d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); + d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, + get_ticks_per_sec()); s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; } s->pmsts &= ~val; diff --git a/hw/adlib.c b/hw/adlib.c index e1e40771a6..1d8092baca 100644 --- a/hw/adlib.c +++ b/hw/adlib.c @@ -165,7 +165,7 @@ static void timer_handler (int c, double interval_Sec) s->ticking[n] = 1; #ifdef DEBUG - interval = ticks_per_sec * interval_Sec; + interval = get_ticks_per_sec() * interval_Sec; exp = qemu_get_clock (vm_clock) + interval; s->exp[n] = exp; #endif @@ -335,7 +335,8 @@ static int baum_eat_packet(BaumDriverState *baum, const uint8_t *buf, int len) int i; /* Allow 100ms to complete the DisplayData packet */ - qemu_mod_timer(baum->cellCount_timer, qemu_get_clock(vm_clock) + ticks_per_sec / 10); + qemu_mod_timer(baum->cellCount_timer, qemu_get_clock(vm_clock) + + get_ticks_per_sec() / 10); for (i = 0; i < baum->x * baum->y ; i++) { EAT(c); cells[i] = c; diff --git a/hw/bt-hci-csr.c b/hw/bt-hci-csr.c index 19d23f536d..7300ea6799 100644 --- a/hw/bt-hci-csr.c +++ b/hw/bt-hci-csr.c @@ -363,7 +363,7 @@ static int csrhci_ioctl(struct CharDriverState *chr, int cmd, void *arg) switch (cmd) { case CHR_IOCTL_SERIAL_SET_PARAMS: ssp = (QEMUSerialSetParams *) arg; - s->baud_delay = ticks_per_sec / ssp->speed; + s->baud_delay = get_ticks_per_sec() / ssp->speed; /* Moments later... (but shorter than 100ms) */ s->modem_state |= CHR_TIOCM_CTS; break; @@ -389,7 +389,7 @@ static void csrhci_reset(struct csrhci_s *s) s->out_len = 0; s->out_size = FIFO_LEN; s->in_len = 0; - s->baud_delay = ticks_per_sec; + s->baud_delay = get_ticks_per_sec(); s->enable = 0; s->in_hdr = INT_MAX; s->in_data = INT_MAX; diff --git a/hw/bt-hci.c b/hw/bt-hci.c index d510d81180..669866a5c3 100644 --- a/hw/bt-hci.c +++ b/hw/bt-hci.c @@ -577,7 +577,7 @@ static void bt_hci_inquiry_result(struct bt_hci_s *hci, static void bt_hci_mod_timer_1280ms(QEMUTimer *timer, int period) { qemu_mod_timer(timer, qemu_get_clock(vm_clock) + - muldiv64(period << 7, ticks_per_sec, 100)); + muldiv64(period << 7, get_ticks_per_sec(), 100)); } static void bt_hci_inquiry_start(struct bt_hci_s *hci, int length) @@ -1086,7 +1086,7 @@ static int bt_hci_mode_change(struct bt_hci_s *hci, uint16_t handle, bt_hci_event_status(hci, HCI_SUCCESS); qemu_mod_timer(link->acl_mode_timer, qemu_get_clock(vm_clock) + - muldiv64(interval * 625, ticks_per_sec, 1000000)); + muldiv64(interval * 625, get_ticks_per_sec(), 1000000)); bt_hci_lmp_mode_change_master(hci, link->link, mode, interval); return 0; @@ -171,7 +171,7 @@ static unsigned int get_counter(CUDATimer *s) unsigned int counter; d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, - CUDA_TIMER_FREQ, ticks_per_sec); + CUDA_TIMER_FREQ, get_ticks_per_sec()); if (s->index == 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ if (d <= (s->counter_value + 1)) { @@ -201,7 +201,7 @@ static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) /* current counter value */ d = muldiv64(current_time - s->load_time, - CUDA_TIMER_FREQ, ticks_per_sec); + CUDA_TIMER_FREQ, get_ticks_per_sec()); /* the timer goes down from latch to -1 (period of latch + 2) */ if (d <= (s->counter_value + 1)) { counter = (s->counter_value - d) & 0xffff; @@ -220,7 +220,7 @@ static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) } CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", s->latch, d, next_time - d); - next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + + next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) + s->load_time; if (next_time <= current_time) next_time = current_time + 1; @@ -505,7 +505,7 @@ static void cuda_adb_poll(void *opaque) } qemu_mod_timer(s->adb_poll_timer, qemu_get_clock(vm_clock) + - (ticks_per_sec / CUDA_ADB_POLL_FREQ)); + (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); } static void cuda_receive_packet(CUDAState *s, @@ -523,7 +523,7 @@ static void cuda_receive_packet(CUDAState *s, if (autopoll) { qemu_mod_timer(s->adb_poll_timer, qemu_get_clock(vm_clock) + - (ticks_per_sec / CUDA_ADB_POLL_FREQ)); + (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); } else { qemu_del_timer(s->adb_poll_timer); } @@ -534,14 +534,14 @@ static void cuda_receive_packet(CUDAState *s, break; case CUDA_SET_TIME: ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4]; - s->tick_offset = ti - (qemu_get_clock(vm_clock) / ticks_per_sec); + s->tick_offset = ti - (qemu_get_clock(vm_clock) / get_ticks_per_sec()); obuf[0] = CUDA_PACKET; obuf[1] = 0; obuf[2] = 0; cuda_send_packet_to_host(s, obuf, 3); break; case CUDA_GET_TIME: - ti = s->tick_offset + (qemu_get_clock(vm_clock) / ticks_per_sec); + ti = s->tick_offset + (qemu_get_clock(vm_clock) / get_ticks_per_sec()); obuf[0] = CUDA_PACKET; obuf[1] = 0; obuf[2] = 0; diff --git a/hw/dp8393x.c b/hw/dp8393x.c index fcf0398fca..067831d1dc 100644 --- a/hw/dp8393x.c +++ b/hw/dp8393x.c @@ -290,7 +290,7 @@ static void set_next_tick(dp8393xState *s) ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; s->wt_last_update = qemu_get_clock(vm_clock); - delay = ticks_per_sec * ticks / 5000000; + delay = get_ticks_per_sec() * ticks / 5000000; qemu_mod_timer(s->watchdog, s->wt_last_update + delay); } @@ -1541,7 +1541,7 @@ static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction) /* XXX: should set main status register to busy */ cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; qemu_mod_timer(fdctrl->result_timer, - qemu_get_clock(vm_clock) + (ticks_per_sec / 50)); + qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50)); } static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction) diff --git a/hw/i8254.c b/hw/i8254.c index 6a8cd3ed18..5c49e6e0ae 100644 --- a/hw/i8254.c +++ b/hw/i8254.c @@ -66,7 +66,8 @@ static int pit_get_count(PITChannelState *s) uint64_t d; int counter; - d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec); + d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, + get_ticks_per_sec()); switch(s->mode) { case 0: case 1: @@ -91,7 +92,8 @@ static int pit_get_out1(PITChannelState *s, int64_t current_time) uint64_t d; int out; - d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); + d = muldiv64(current_time - s->count_load_time, PIT_FREQ, + get_ticks_per_sec()); switch(s->mode) { default: case 0: @@ -130,7 +132,8 @@ static int64_t pit_get_next_transition_time(PITChannelState *s, uint64_t d, next_time, base; int period2; - d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); + d = muldiv64(current_time - s->count_load_time, PIT_FREQ, + get_ticks_per_sec()); switch(s->mode) { default: case 0: @@ -166,7 +169,8 @@ static int64_t pit_get_next_transition_time(PITChannelState *s, break; } /* convert to timer units */ - next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ); + next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(), + PIT_FREQ); /* fix potential rounding problems */ /* XXX: better solution: use a clock at PIT_FREQ Hz */ if (next_time <= current_time) @@ -373,7 +377,7 @@ static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) #ifdef DEBUG_PIT printf("irq_level=%d next_delay=%f\n", irq_level, - (double)(expire_time - current_time) / ticks_per_sec); + (double)(expire_time - current_time) / get_ticks_per_sec()); #endif s->next_transition_time = expire_time; if (expire_time != -1) diff --git a/hw/i8259.c b/hw/i8259.c index 74acc396c1..9b2896c3fc 100644 --- a/hw/i8259.c +++ b/hw/i8259.c @@ -247,7 +247,8 @@ int pic_read_irq(PicState2 *s) #ifdef DEBUG_IRQ_LATENCY printf("IRQ%d latency=%0.3fus\n", irq, - (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec); + (double)(qemu_get_clock(vm_clock) - + irq_time[irq]) * 1000000.0 / get_ticks_per_sec()); #endif #if defined(DEBUG_PIC) printf("pic_interrupt: irq=%d\n", irq); diff --git a/hw/ide/core.c b/hw/ide/core.c index 87d5cdf6ef..5f6e2cb5de 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -647,7 +647,7 @@ static void ide_sector_write(IDEState *s) option _only_ to install Windows 2000. You must disable it for normal use. */ qemu_mod_timer(s->sector_write_timer, - qemu_get_clock(vm_clock) + (ticks_per_sec / 1000)); + qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 1000)); } else #endif { diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index a1ff9baa37..9d6a62751f 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -109,7 +109,7 @@ static void rtc_coalesced_timer_update(RTCState *s) /* divide each RTC interval to 2 - 8 smaller intervals */ int c = MIN(s->irq_coalesced, 7) + 1; int64_t next_clock = qemu_get_clock(vm_clock) + - muldiv64(s->period / c, ticks_per_sec, 32768); + muldiv64(s->period / c, get_ticks_per_sec(), 32768); qemu_mod_timer(s->coalesced_timer, next_clock); } } @@ -159,9 +159,9 @@ static void rtc_timer_update(RTCState *s, int64_t current_time) s->period = period; #endif /* compute 32 khz clock */ - cur_clock = muldiv64(current_time, 32768, ticks_per_sec); + cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec()); next_irq_clock = (cur_clock & ~(period - 1)) + period; - s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; + s->next_periodic_time = muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; qemu_mod_timer(s->periodic_timer, s->next_periodic_time); } else { #ifdef TARGET_I386 @@ -380,7 +380,7 @@ static void rtc_update_second(void *opaque) /* if the oscillator is not in normal operation, we do not update */ if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { - s->next_second_time += ticks_per_sec; + s->next_second_time += get_ticks_per_sec(); qemu_mod_timer(s->second_timer, s->next_second_time); } else { rtc_next_second(&s->current_tm); @@ -391,7 +391,7 @@ static void rtc_update_second(void *opaque) } /* should be 244 us = 8 / 32768 seconds, but currently the timers do not have the necessary resolution. */ - delay = (ticks_per_sec * 1) / 100; + delay = (get_ticks_per_sec() * 1) / 100; if (delay < 1) delay = 1; qemu_mod_timer(s->second_timer2, @@ -431,7 +431,7 @@ static void rtc_update_second2(void *opaque) /* clear update in progress bit */ s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; - s->next_second_time += ticks_per_sec; + s->next_second_time += get_ticks_per_sec(); qemu_mod_timer(s->second_timer, s->next_second_time); } @@ -616,7 +616,7 @@ static int rtc_initfn(ISADevice *dev) s->second_timer2 = qemu_new_timer(vm_clock, rtc_update_second2, s); - s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; + s->next_second_time = qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 99) / 100; qemu_mod_timer(s->second_timer2, s->next_second_time); register_ioport_write(base, 2, 1, cmos_ioport_write, s); @@ -754,7 +754,7 @@ RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, s->second_timer2 = qemu_new_timer(vm_clock, rtc_update_second2, s); - s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; + s->next_second_time = qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 99) / 100; qemu_mod_timer(s->second_timer2, s->next_second_time); io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s); diff --git a/hw/mips_timer.c b/hw/mips_timer.c index d341e51657..bb3c3e4ec3 100644 --- a/hw/mips_timer.c +++ b/hw/mips_timer.c @@ -27,7 +27,7 @@ uint32_t cpu_mips_get_count (CPUState *env) else return env->CP0_Count + (uint32_t)muldiv64(qemu_get_clock(vm_clock), - TIMER_FREQ, ticks_per_sec); + TIMER_FREQ, get_ticks_per_sec()); } static void cpu_mips_timer_update(CPUState *env) @@ -37,8 +37,8 @@ static void cpu_mips_timer_update(CPUState *env) now = qemu_get_clock(vm_clock); wait = env->CP0_Compare - env->CP0_Count - - (uint32_t)muldiv64(now, TIMER_FREQ, ticks_per_sec); - next = now + muldiv64(wait, ticks_per_sec, TIMER_FREQ); + (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); + next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); qemu_mod_timer(env->timer, next); } @@ -50,7 +50,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t count) /* Store new count register */ env->CP0_Count = count - (uint32_t)muldiv64(qemu_get_clock(vm_clock), - TIMER_FREQ, ticks_per_sec); + TIMER_FREQ, get_ticks_per_sec()); /* Update timer timer */ cpu_mips_timer_update(env); } @@ -75,7 +75,7 @@ void cpu_mips_stop_count(CPUState *env) { /* Store the current value */ env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock), - TIMER_FREQ, ticks_per_sec); + TIMER_FREQ, get_ticks_per_sec()); } static void mips_timer_cb (void *opaque) diff --git a/hw/omap1.c b/hw/omap1.c index e870d96753..06c71581b0 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -675,7 +675,7 @@ static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) if (timer->st && timer->enable && timer->rate) return timer->val - muldiv64(distance >> (timer->ptv + 1), - timer->rate, ticks_per_sec); + timer->rate, get_ticks_per_sec()); else return timer->val; } @@ -693,7 +693,7 @@ static inline void omap_timer_update(struct omap_mpu_timer_s *timer) if (timer->enable && timer->st && timer->rate) { timer->val = timer->reset_val; /* Should skip this on clk enable */ expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), - ticks_per_sec, timer->rate); + get_ticks_per_sec(), timer->rate); /* If timer expiry would be sooner than in about 1 ms and * auto-reload isn't set, then fire immediately. This is a hack @@ -701,7 +701,7 @@ static inline void omap_timer_update(struct omap_mpu_timer_s *timer) * sets the interval to a very low value and polls the status bit * in a busy loop when it wants to sleep just a couple of CPU * ticks. */ - if (expires > (ticks_per_sec >> 10) || timer->ar) + if (expires > (get_ticks_per_sec() >> 10) || timer->ar) qemu_mod_timer(timer->timer, timer->time + expires); else qemu_bh_schedule(timer->tick); @@ -1158,14 +1158,14 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, now -= s->ulpd_gauge_start; /* 32-kHz ticks */ - ticks = muldiv64(now, 32768, ticks_per_sec); + ticks = muldiv64(now, 32768, get_ticks_per_sec()); s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; if (ticks >> 32) /* OVERFLOW_32K */ s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; /* High frequency ticks */ - ticks = muldiv64(now, 12000000, ticks_per_sec); + ticks = muldiv64(now, 12000000, get_ticks_per_sec()); s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; if (ticks >> 32) /* OVERFLOW_HI_FREQ */ @@ -3831,7 +3831,8 @@ static void omap_mcbsp_source_tick(void *opaque) s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; omap_mcbsp_rx_newdata(s); - qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec); + qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + + get_ticks_per_sec()); } static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) @@ -3876,7 +3877,8 @@ static void omap_mcbsp_sink_tick(void *opaque) s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; omap_mcbsp_tx_newdata(s); - qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec); + qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + + get_ticks_per_sec()); } static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) diff --git a/hw/omap2.c b/hw/omap2.c index 6a681d60f3..ef338a5623 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -412,7 +412,7 @@ static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, if (s->trigger == gpt_trigger_none) omap_gp_timer_out(s, s->scpwm); /* TODO: make sure this doesn't overflow 32-bits */ - s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0); + s->ticks_per_sec = get_ticks_per_sec() << (s->pre ? s->ptv + 1 : 0); omap_gp_timer_update(s); break; @@ -491,7 +491,7 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, /* 32-kHz Sync Timer of the OMAP2 */ static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { - return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec); + return muldiv64(qemu_get_clock(vm_clock), 0x8000, get_ticks_per_sec()); } static void omap_synctimer_reset(struct omap_synctimer_s *s) diff --git a/hw/pcnet.c b/hw/pcnet.c index 8c352d2137..ae98a201dc 100644 --- a/hw/pcnet.c +++ b/hw/pcnet.c @@ -726,7 +726,7 @@ static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_ti { int64_t next_time = current_time + muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)), - ticks_per_sec, 33000000L); + get_ticks_per_sec(), 33000000L); if (next_time <= current_time) next_time = current_time + 1; return next_time; diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 7f5094b3ed..135c850797 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -389,7 +389,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, pflash_update(pfl, 0, pfl->chip_len); /* Let's wait 5 seconds before chip erase is done */ qemu_mod_timer(pfl->timer, - qemu_get_clock(vm_clock) + (ticks_per_sec * 5)); + qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 5)); break; case 0x30: /* Sector erase */ @@ -402,7 +402,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, pfl->status = 0x00; /* Let's wait 1/2 second before sector erase is done */ qemu_mod_timer(pfl->timer, - qemu_get_clock(vm_clock) + (ticks_per_sec / 2)); + qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 2)); break; default: DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); diff --git a/hw/pl031.c b/hw/pl031.c index 19577dde35..45b7032c50 100644 --- a/hw/pl031.c +++ b/hw/pl031.c @@ -67,7 +67,7 @@ static uint32_t pl031_get_count(pl031_state *s) { /* This assumes qemu_get_clock returns the time since the machine was created. */ - return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec; + return s->tick_offset + qemu_get_clock(vm_clock) / get_ticks_per_sec(); } static void pl031_set_alarm(pl031_state *s) @@ -76,7 +76,7 @@ static void pl031_set_alarm(pl031_state *s) uint32_t ticks; now = qemu_get_clock(vm_clock); - ticks = s->tick_offset + now / ticks_per_sec; + ticks = s->tick_offset + now / get_ticks_per_sec(); /* The timer wraps around. This subtraction also wraps in the same way, and gives correct results when alarm < now_ticks. */ @@ -86,7 +86,7 @@ static void pl031_set_alarm(pl031_state *s) qemu_del_timer(s->timer); pl031_interrupt(s); } else { - qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec); + qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec()); } } @@ -397,7 +397,7 @@ static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) { /* TB time in tb periods */ - return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset; + return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset; } uint32_t cpu_ppc_load_tbl (CPUState *env) @@ -430,7 +430,7 @@ uint32_t cpu_ppc_load_tbu (CPUState *env) static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t *tb_offsetp, uint64_t value) { - *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); + *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", __func__, value, *tb_offsetp); } @@ -557,9 +557,9 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) diff = next - qemu_get_clock(vm_clock); if (diff >= 0) - decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); + decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); else - decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); + decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec()); LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); return decr; @@ -586,7 +586,7 @@ uint64_t cpu_ppc_load_purr (CPUState *env) diff = qemu_get_clock(vm_clock) - tb_env->purr_start; - return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec); + return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec()); } /* When decrementer expires, @@ -618,7 +618,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, decr, value); now = qemu_get_clock(vm_clock); - next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); + next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); if (is_excp) next += *nextp - now; if (next == now) @@ -788,7 +788,7 @@ static void cpu_4xx_fit_cb (void *opaque) /* Cannot occur, but makes gcc happy */ return; } - next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); + next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq); if (next == now) next++; qemu_mod_timer(ppcemb_timer->fit_timer, next); @@ -818,7 +818,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) __func__, ppcemb_timer->pit_reload); now = qemu_get_clock(vm_clock); next = now + muldiv64(ppcemb_timer->pit_reload, - ticks_per_sec, tb_env->decr_freq); + get_ticks_per_sec(), tb_env->decr_freq); if (is_excp) next += tb_env->decr_next - now; if (next == now) @@ -878,7 +878,7 @@ static void cpu_4xx_wdt_cb (void *opaque) /* Cannot occur, but makes gcc happy */ return; } - next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); + next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq); if (next == now) next++; LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 65d70d380c..59def4ceb6 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -1379,7 +1379,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) case 0x00: /* Time base counter */ ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, - gpt->tb_freq, ticks_per_sec); + gpt->tb_freq, get_ticks_per_sec()); break; case 0x10: /* Output enable */ @@ -1434,7 +1434,7 @@ static void ppc4xx_gpt_writel (void *opaque, switch (addr) { case 0x00: /* Time base counter */ - gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) + gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq) - qemu_get_clock(vm_clock); ppc4xx_gpt_compute_timer(gpt); break; diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c index 154537baa7..43bad2c9c2 100644 --- a/hw/pxa2xx_timer.c +++ b/hw/pxa2xx_timer.c @@ -98,11 +98,11 @@ static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) uint64_t new_qemu; now_vm = s->clock + - muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec); + muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec()); for (i = 0; i < 4; i ++) { new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), - ticks_per_sec, s->freq); + get_ticks_per_sec(), s->freq); qemu_mod_timer(s->timer[i].qtimer, new_qemu); } } @@ -127,10 +127,10 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) now_vm = s->tm4[counter].clock + muldiv64(now_qemu - s->tm4[counter].lastload, - s->tm4[counter].freq, ticks_per_sec); + s->tm4[counter].freq, get_ticks_per_sec()); new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), - ticks_per_sec, s->tm4[counter].freq); + get_ticks_per_sec(), s->tm4[counter].freq); qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); } @@ -158,7 +158,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) return s->tm4[tm].tm.value; case OSCR: return s->clock + muldiv64(qemu_get_clock(vm_clock) - - s->lastload, s->freq, ticks_per_sec); + s->lastload, s->freq, get_ticks_per_sec()); case OSCR11: tm ++; case OSCR10: tm ++; case OSCR9: tm ++; @@ -175,7 +175,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) s->snapshot = s->tm4[tm - 1].clock + muldiv64( qemu_get_clock(vm_clock) - s->tm4[tm - 1].lastload, - s->tm4[tm - 1].freq, ticks_per_sec); + s->tm4[tm - 1].freq, get_ticks_per_sec()); else s->snapshot = s->tm4[tm - 1].clock; } @@ -183,7 +183,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) if (!s->tm4[tm].freq) return s->tm4[tm].clock; return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) - - s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec); + s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); case OIER: return s->irq_enabled; case OSSR: /* Status register */ diff --git a/hw/rc4030.c b/hw/rc4030.c index f4ac83fff5..c2b2a3eb56 100644 --- a/hw/rc4030.c +++ b/hw/rc4030.c @@ -104,7 +104,8 @@ static void set_next_tick(rc4030State *s) tm_hz = 1000 / (s->itr + 1); - qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / tm_hz); + qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + + get_ticks_per_sec() / tm_hz); } /* called for accesses to rc4030 */ diff --git a/hw/rtl8139.c b/hw/rtl8139.c index 3bd72e5c86..83cb1ff701 100644 --- a/hw/rtl8139.c +++ b/hw/rtl8139.c @@ -3361,7 +3361,7 @@ static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = { static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time) { int64_t next_time = current_time + - muldiv64(1, ticks_per_sec, PCI_FREQUENCY); + muldiv64(1, get_ticks_per_sec(), PCI_FREQUENCY); if (next_time <= current_time) next_time = current_time + 1; return next_time; @@ -3385,7 +3385,8 @@ static void rtl8139_timer(void *opaque) curr_time = qemu_get_clock(vm_clock); - curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec); + curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, + get_ticks_per_sec()); if (s->TimerInt && curr_tick >= s->TimerInt) { @@ -757,8 +757,8 @@ static void complete (SB16State *s) freq = s->freq > 0 ? s->freq : 11025; samples = dsp_get_lohi (s) + 1; bytes = samples << s->fmt_stereo << (s->fmt_bits == 16); - ticks = (bytes * ticks_per_sec) / freq; - if (ticks < ticks_per_sec / 1024) { + ticks = (bytes * get_ticks_per_sec()) / freq; + if (ticks < get_ticks_per_sec() / 1024) { qemu_irq_raise (s->pic); } else { diff --git a/hw/serial.c b/hw/serial.c index f5988a5fc6..f9c7246b60 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -246,7 +246,7 @@ static void serial_update_parameters(SerialState *s) ssp.parity = parity; ssp.data_bits = data_bits; ssp.stop_bits = stop_bits; - s->char_transmit_time = (ticks_per_sec / speed) * frame_size; + s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); #if 0 printf("speed=%d parity=%c data=%d stop=%d\n", @@ -286,7 +286,7 @@ static void serial_update_msl(SerialState *s) We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ if (s->poll_msl) - qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100); + qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100); } static void serial_xmit(void *opaque) @@ -695,7 +695,7 @@ static void serial_reset(void *opaque) s->mcr = UART_MCR_OUT2; s->scr = 0; s->tsr_retry = 0; - s->char_transmit_time = (ticks_per_sec / 9600) * 9; + s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9; s->poll_msl = 0; fifo_clear(s,RECV_FIFO); diff --git a/hw/spitz.c b/hw/spitz.c index e19b8a203d..564519b2c7 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -392,7 +392,8 @@ static void spitz_keyboard_tick(void *opaque) s->fifopos = 0; } - qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32); + qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + + get_ticks_per_sec() / 32); } static void spitz_keyboard_pre_map(SpitzKeyboardState *s) diff --git a/hw/stellaris.c b/hw/stellaris.c index 0ea76527cf..bcde0a2977 100644 --- a/hw/stellaris.c +++ b/hw/stellaris.c @@ -90,7 +90,7 @@ static void gptm_reload(gptm_state *s, int n, int reset) tick += (int64_t)count * system_clock_scale; } else if (s->config == 1) { /* 32-bit RTC. 1Hz tick. */ - tick += ticks_per_sec; + tick += get_ticks_per_sec(); } else if (s->mode[n] == 0xa) { /* PWM mode. Not implemented. */ } else { diff --git a/hw/tsc2005.c b/hw/tsc2005.c index efc63c0454..b75cc862ae 100644 --- a/hw/tsc2005.c +++ b/hw/tsc2005.c @@ -290,7 +290,7 @@ static void tsc2005_pin_update(TSC2005State *s) s->precision = s->nextprecision; s->function = s->nextfunction; s->pdst = !s->pnd0; /* Synchronised on internal clock */ - expires = qemu_get_clock(vm_clock) + (ticks_per_sec >> 7); + expires = qemu_get_clock(vm_clock) + (get_ticks_per_sec() >> 7); qemu_mod_timer(s->timer, expires); } diff --git a/hw/tsc210x.c b/hw/tsc210x.c index 004e607649..6bbe24d2fe 100644 --- a/hw/tsc210x.c +++ b/hw/tsc210x.c @@ -864,7 +864,7 @@ static void tsc210x_pin_update(TSC210xState *s) s->busy = 1; s->precision = s->nextprecision; s->function = s->nextfunction; - expires = qemu_get_clock(vm_clock) + (ticks_per_sec >> 10); + expires = qemu_get_clock(vm_clock) + (get_ticks_per_sec() >> 10); qemu_mod_timer(s->timer, expires); } diff --git a/hw/tusb6010.c b/hw/tusb6010.c index 1ed9d4c08e..3887233339 100644 --- a/hw/tusb6010.c +++ b/hw/tusb6010.c @@ -523,7 +523,7 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr, if (value & TUSB_DEV_OTG_TIMER_ENABLE) qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) + muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), - ticks_per_sec, TUSB_DEVCLOCK)); + get_ticks_per_sec(), TUSB_DEVCLOCK)); else qemu_del_timer(s->otg_timer); break; @@ -763,6 +763,6 @@ void tusb6010_power(TUSBState *s, int on) s->intr_ok = 0; tusb_intr_update(s); qemu_mod_timer(s->pwr_timer, - qemu_get_clock(vm_clock) + ticks_per_sec / 2); + qemu_get_clock(vm_clock) + get_ticks_per_sec() / 2); } } diff --git a/hw/usb-musb.c b/hw/usb-musb.c index 8fba84dadf..9eb0d6361f 100644 --- a/hw/usb-musb.c +++ b/hw/usb-musb.c @@ -511,7 +511,7 @@ static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir) ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque); qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) + - muldiv64(timeout, ticks_per_sec, 8000)); + muldiv64(timeout, get_ticks_per_sec(), 8000)); } static void musb_schedule0_cb(USBPacket *packey, void *opaque) diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 96a955516d..6e428c4fda 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -1669,12 +1669,12 @@ static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, if (usb_frame_time == 0) { #ifdef OHCI_TIME_WARP - usb_frame_time = ticks_per_sec; - usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000); + usb_frame_time = get_ticks_per_sec(); + usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); #else - usb_frame_time = muldiv64(1, ticks_per_sec, 1000); - if (ticks_per_sec >= USB_HZ) { - usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ); + usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); + if (get_ticks_per_sec() >= USB_HZ) { + usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ); } else { usb_bit_time = 1; } diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index 09ffd4b36b..6807413682 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1054,7 +1054,7 @@ static void uhci_frame_timer(void *opaque) /* prepare the timer for the next frame */ expire_time = qemu_get_clock(vm_clock) + - (ticks_per_sec / FRAME_TIMER_FREQ); + (get_ticks_per_sec() / FRAME_TIMER_FREQ); qemu_mod_timer(s->frame_timer, expire_time); } @@ -202,9 +202,9 @@ static void vga_precise_update_retrace_info(VGACommonState *s) r->total_chars = vtotal_lines * htotal_chars; if (r->freq) { - r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq); + r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq); } else { - r->ticks_per_char = ticks_per_sec / chars_per_sec; + r->ticks_per_char = get_ticks_per_sec() / chars_per_sec; } r->vstart = vretr_start_line; @@ -230,7 +230,7 @@ static void vga_precise_update_retrace_info(VGACommonState *s) "dots = %d\n" "ticks/char = %lld\n" "\n", - (double) ticks_per_sec / (r->ticks_per_char * r->total_chars), + (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars), htotal_chars, hretr_start_char, hretr_skew_chars, diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c index fc038c8e31..9126e72524 100644 --- a/hw/wdt_i6300esb.c +++ b/hw/wdt_i6300esb.c @@ -130,7 +130,7 @@ static void i6300esb_restart_timer(I6300State *d, int stage) timeout <<= 5; /* Get the timeout in units of ticks_per_sec. */ - timeout = ticks_per_sec * timeout / 33000000; + timeout = get_ticks_per_sec() * timeout / 33000000; i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout); diff --git a/hw/wdt_ib700.c b/hw/wdt_ib700.c index e0ee65a85b..0ee3a5cc06 100644 --- a/hw/wdt_ib700.c +++ b/hw/wdt_ib700.c @@ -52,7 +52,7 @@ static void ib700_write_enable_reg(void *vp, uint32_t addr, uint32_t data) ib700_debug("addr = %x, data = %x\n", addr, data); - timeout = (int64_t) time_map[data & 0xF] * ticks_per_sec; + timeout = (int64_t) time_map[data & 0xF] * get_ticks_per_sec(); qemu_mod_timer(timer, qemu_get_clock (vm_clock) + timeout); } |