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-rw-r--r--hw/arm/aspeed.c2
-rw-r--r--hw/arm/aspeed_soc.c63
-rw-r--r--hw/core/loader.c2
-rw-r--r--hw/gpio/Makefile.objs1
-rw-r--r--hw/gpio/aspeed_gpio.c884
-rw-r--r--hw/i386/Kconfig1
-rw-r--r--hw/i386/Makefile.objs2
-rw-r--r--hw/i386/e820_memory_layout.c59
-rw-r--r--hw/i386/e820_memory_layout.h42
-rw-r--r--hw/i386/fw_cfg.c137
-rw-r--r--hw/i386/fw_cfg.h7
-rw-r--r--hw/i386/pc.c204
-rw-r--r--hw/misc/aspeed_scu.c102
-rw-r--r--hw/ssi/aspeed_smc.c335
-rw-r--r--hw/timer/aspeed_timer.c3
15 files changed, 1549 insertions, 295 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 13e208c78c..aa72be309d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -190,6 +190,8 @@ static void aspeed_board_init(MachineState *machine,
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus",
&error_abort);
+ object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container),
+ "dram", &error_abort);
if (machine->kernel_filename) {
/*
* When booting with a -kernel command line there is no u-boot
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 9ee8104832..cf1d0cf921 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -112,43 +112,13 @@ static const int aspeed_soc_ast2400_irqmap[] = {
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
-static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
-static const char *aspeed_soc_ast2500_typenames[] = {
- "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
-
static const AspeedSoCInfo aspeed_socs[] = {
{
- .name = "ast2400-a0",
- .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
- .silicon_rev = AST2400_A0_SILICON_REV,
- .sram_size = 0x8000,
- .spis_num = 1,
- .fmc_typename = "aspeed.smc.fmc",
- .spi_typename = aspeed_soc_ast2400_typenames,
- .wdts_num = 2,
- .irqmap = aspeed_soc_ast2400_irqmap,
- .memmap = aspeed_soc_ast2400_memmap,
- .num_cpus = 1,
- }, {
.name = "ast2400-a1",
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
.silicon_rev = AST2400_A1_SILICON_REV,
.sram_size = 0x8000,
.spis_num = 1,
- .fmc_typename = "aspeed.smc.fmc",
- .spi_typename = aspeed_soc_ast2400_typenames,
- .wdts_num = 2,
- .irqmap = aspeed_soc_ast2400_irqmap,
- .memmap = aspeed_soc_ast2400_memmap,
- .num_cpus = 1,
- }, {
- .name = "ast2400",
- .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
- .silicon_rev = AST2400_A0_SILICON_REV,
- .sram_size = 0x8000,
- .spis_num = 1,
- .fmc_typename = "aspeed.smc.fmc",
- .spi_typename = aspeed_soc_ast2400_typenames,
.wdts_num = 2,
.irqmap = aspeed_soc_ast2400_irqmap,
.memmap = aspeed_soc_ast2400_memmap,
@@ -159,8 +129,6 @@ static const AspeedSoCInfo aspeed_socs[] = {
.silicon_rev = AST2500_A1_SILICON_REV,
.sram_size = 0x9000,
.spis_num = 2,
- .fmc_typename = "aspeed.smc.ast2500-fmc",
- .spi_typename = aspeed_soc_ast2500_typenames,
.wdts_num = 3,
.irqmap = aspeed_soc_ast2500_irqmap,
.memmap = aspeed_soc_ast2500_memmap,
@@ -180,6 +148,12 @@ static void aspeed_soc_init(Object *obj)
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i;
+ char socname[8];
+ char typename[64];
+
+ if (sscanf(sc->info->name, "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
for (i = 0; i < sc->info->num_cpus; i++) {
object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
@@ -187,8 +161,9 @@ static void aspeed_soc_init(Object *obj)
&error_abort, NULL);
}
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
- TYPE_ASPEED_SCU);
+ typename);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
sc->info->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
@@ -212,14 +187,18 @@ static void aspeed_soc_init(Object *obj)
sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
TYPE_ASPEED_I2C);
+ snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
- sc->info->fmc_typename);
+ typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
&error_abort);
+ object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
+ &error_abort);
for (i = 0; i < sc->info->spis_num; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
- sizeof(s->spi[i]), sc->info->spi_typename[i]);
+ sizeof(s->spi[i]), typename);
}
sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
@@ -247,6 +226,10 @@ static void aspeed_soc_init(Object *obj)
sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
TYPE_ASPEED_XDMA);
+
+ snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
+ sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
+ typename);
}
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -426,6 +409,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sc->info->memmap[ASPEED_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
aspeed_soc_get_irq(s, ASPEED_XDMA));
+
+ /* GPIO */
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
+ aspeed_soc_get_irq(s, ASPEED_GPIO));
}
static Property aspeed_soc_properties[] = {
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 32f7cc7c33..75eb56ddbb 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -338,6 +338,8 @@ const char *load_elf_strerror(int error)
return "The image is from incompatible architecture";
case ELF_LOAD_WRONG_ENDIAN:
return "The image has incorrect endianness";
+ case ELF_LOAD_TOO_BIG:
+ return "The image segments are too big to load";
default:
return "Unknown error";
}
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
index e5da0cb54f..d305b3b24b 100644
--- a/hw/gpio/Makefile.objs
+++ b/hw/gpio/Makefile.objs
@@ -9,3 +9,4 @@ obj-$(CONFIG_OMAP) += omap_gpio.o
obj-$(CONFIG_IMX) += imx_gpio.o
obj-$(CONFIG_RASPI) += bcm2835_gpio.o
obj-$(CONFIG_NRF51_SOC) += nrf51_gpio.o
+obj-$(CONFIG_ASPEED_SOC) += aspeed_gpio.o
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
new file mode 100644
index 0000000000..25fbfec3b8
--- /dev/null
+++ b/hw/gpio/aspeed_gpio.c
@@ -0,0 +1,884 @@
+/*
+ * ASPEED GPIO Controller
+ *
+ * Copyright (C) 2017-2019 IBM Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <assert.h>
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "qemu/log.h"
+#include "hw/gpio/aspeed_gpio.h"
+#include "include/hw/misc/aspeed_scu.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+
+#define GPIOS_PER_REG 32
+#define GPIOS_PER_SET GPIOS_PER_REG
+#define GPIO_PIN_GAP_SIZE 4
+#define GPIOS_PER_GROUP 8
+#define GPIO_GROUP_SHIFT 3
+
+/* GPIO Source Types */
+#define ASPEED_CMD_SRC_MASK 0x01010101
+#define ASPEED_SOURCE_ARM 0
+#define ASPEED_SOURCE_LPC 1
+#define ASPEED_SOURCE_COPROCESSOR 2
+#define ASPEED_SOURCE_RESERVED 3
+
+/* GPIO Interrupt Triggers */
+/*
+ * For each set of gpios there are three sensitivity registers that control
+ * the interrupt trigger mode.
+ *
+ * | 2 | 1 | 0 | trigger mode
+ * -----------------------------
+ * | 0 | 0 | 0 | falling-edge
+ * | 0 | 0 | 1 | rising-edge
+ * | 0 | 1 | 0 | level-low
+ * | 0 | 1 | 1 | level-high
+ * | 1 | X | X | dual-edge
+ */
+#define ASPEED_FALLING_EDGE 0
+#define ASPEED_RISING_EDGE 1
+#define ASPEED_LEVEL_LOW 2
+#define ASPEED_LEVEL_HIGH 3
+#define ASPEED_DUAL_EDGE 4
+
+/* GPIO Register Address Offsets */
+#define GPIO_ABCD_DATA_VALUE (0x000 >> 2)
+#define GPIO_ABCD_DIRECTION (0x004 >> 2)
+#define GPIO_ABCD_INT_ENABLE (0x008 >> 2)
+#define GPIO_ABCD_INT_SENS_0 (0x00C >> 2)
+#define GPIO_ABCD_INT_SENS_1 (0x010 >> 2)
+#define GPIO_ABCD_INT_SENS_2 (0x014 >> 2)
+#define GPIO_ABCD_INT_STATUS (0x018 >> 2)
+#define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2)
+#define GPIO_EFGH_DATA_VALUE (0x020 >> 2)
+#define GPIO_EFGH_DIRECTION (0x024 >> 2)
+#define GPIO_EFGH_INT_ENABLE (0x028 >> 2)
+#define GPIO_EFGH_INT_SENS_0 (0x02C >> 2)
+#define GPIO_EFGH_INT_SENS_1 (0x030 >> 2)
+#define GPIO_EFGH_INT_SENS_2 (0x034 >> 2)
+#define GPIO_EFGH_INT_STATUS (0x038 >> 2)
+#define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2)
+#define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2)
+#define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2)
+#define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2)
+#define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2)
+#define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2)
+#define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2)
+#define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2)
+#define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2)
+#define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2)
+#define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2)
+#define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2)
+#define GPIO_IJKL_DATA_VALUE (0x070 >> 2)
+#define GPIO_IJKL_DIRECTION (0x074 >> 2)
+#define GPIO_MNOP_DATA_VALUE (0x078 >> 2)
+#define GPIO_MNOP_DIRECTION (0x07C >> 2)
+#define GPIO_QRST_DATA_VALUE (0x080 >> 2)
+#define GPIO_QRST_DIRECTION (0x084 >> 2)
+#define GPIO_UVWX_DATA_VALUE (0x088 >> 2)
+#define GPIO_UVWX_DIRECTION (0x08C >> 2)
+#define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2)
+#define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2)
+#define GPIO_IJKL_INT_ENABLE (0x098 >> 2)
+#define GPIO_IJKL_INT_SENS_0 (0x09C >> 2)
+#define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2)
+#define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2)
+#define GPIO_IJKL_INT_STATUS (0x0A8 >> 2)
+#define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2)
+#define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2)
+#define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2)
+#define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2)
+#define GPIO_ABCD_DATA_READ (0x0C0 >> 2)
+#define GPIO_EFGH_DATA_READ (0x0C4 >> 2)
+#define GPIO_IJKL_DATA_READ (0x0C8 >> 2)
+#define GPIO_MNOP_DATA_READ (0x0CC >> 2)
+#define GPIO_QRST_DATA_READ (0x0D0 >> 2)
+#define GPIO_UVWX_DATA_READ (0x0D4 >> 2)
+#define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2)
+#define GPIO_AC_DATA_READ (0x0DC >> 2)
+#define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2)
+#define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2)
+#define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2)
+#define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2)
+#define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2)
+#define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2)
+#define GPIO_MNOP_INT_STATUS (0x0F8 >> 2)
+#define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2)
+#define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2)
+#define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2)
+#define GPIO_MNOP_INPUT_MASK (0x108 >> 2)
+#define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2)
+#define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2)
+#define GPIO_QRST_INT_ENABLE (0x118 >> 2)
+#define GPIO_QRST_INT_SENS_0 (0x11C >> 2)
+#define GPIO_QRST_INT_SENS_1 (0x120 >> 2)
+#define GPIO_QRST_INT_SENS_2 (0x124 >> 2)
+#define GPIO_QRST_INT_STATUS (0x128 >> 2)
+#define GPIO_QRST_RESET_TOLERANT (0x12C >> 2)
+#define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2)
+#define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2)
+#define GPIO_QRST_INPUT_MASK (0x138 >> 2)
+#define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2)
+#define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2)
+#define GPIO_UVWX_INT_ENABLE (0x148 >> 2)
+#define GPIO_UVWX_INT_SENS_0 (0x14C >> 2)
+#define GPIO_UVWX_INT_SENS_1 (0x150 >> 2)
+#define GPIO_UVWX_INT_SENS_2 (0x154 >> 2)
+#define GPIO_UVWX_INT_STATUS (0x158 >> 2)
+#define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2)
+#define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2)
+#define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2)
+#define GPIO_UVWX_INPUT_MASK (0x168 >> 2)
+#define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2)
+#define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2)
+#define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2)
+#define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2)
+#define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2)
+#define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2)
+#define GPIO_YZAAAB_INT_STATUS (0x188 >> 2)
+#define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2)
+#define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2)
+#define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2)
+#define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2)
+#define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2)
+#define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2)
+#define GPIO_AC_INT_ENABLE (0x1A8 >> 2)
+#define GPIO_AC_INT_SENS_0 (0x1AC >> 2)
+#define GPIO_AC_INT_SENS_1 (0x1B0 >> 2)
+#define GPIO_AC_INT_SENS_2 (0x1B4 >> 2)
+#define GPIO_AC_INT_STATUS (0x1B8 >> 2)
+#define GPIO_AC_RESET_TOLERANT (0x1BC >> 2)
+#define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2)
+#define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2)
+#define GPIO_AC_INPUT_MASK (0x1C8 >> 2)
+#define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2)
+#define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2)
+#define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2)
+#define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2)
+#define GPIO_AC_DATA_VALUE (0x1E8 >> 2)
+#define GPIO_AC_DIRECTION (0x1EC >> 2)
+#define GPIO_3_6V_MEM_SIZE 0x1F0
+#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2)
+
+static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
+{
+ uint32_t falling_edge = 0, rising_edge = 0;
+ uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1)
+ | extract32(regs->int_sens_1, gpio, 1) << 1
+ | extract32(regs->int_sens_2, gpio, 1) << 2;
+ uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1);
+ uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1);
+
+ if (!gpio_int_enabled) {
+ return 0;
+ }
+
+ /* Detect edges */
+ if (gpio_curr_high && !gpio_prev_high) {
+ rising_edge = 1;
+ } else if (!gpio_curr_high && gpio_prev_high) {
+ falling_edge = 1;
+ }
+
+ if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) ||
+ ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) ||
+ ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) ||
+ ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) ||
+ ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge)))
+ {
+ regs->int_status = deposit32(regs->int_status, gpio, 1, 1);
+ return 1;
+ }
+ return 0;
+}
+
+#define nested_struct_index(ta, pa, m, tb, pb) \
+ (pb - ((tb *)(((char *)pa) + offsetof(ta, m))))
+
+static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs)
+{
+ return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs);
+}
+
+static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs,
+ uint32_t value)
+{
+ uint32_t input_mask = regs->input_mask;
+ uint32_t direction = regs->direction;
+ uint32_t old = regs->data_value;
+ uint32_t new = value;
+ uint32_t diff;
+ int gpio;
+
+ diff = old ^ new;
+ if (diff) {
+ for (gpio = 0; gpio < GPIOS_PER_REG; gpio++) {
+ uint32_t mask = 1 << gpio;
+
+ /* If the gpio needs to be updated... */
+ if (!(diff & mask)) {
+ continue;
+ }
+
+ /* ...and we're output or not input-masked... */
+ if (!(direction & mask) && (input_mask & mask)) {
+ continue;
+ }
+
+ /* ...then update the state. */
+ if (mask & new) {
+ regs->data_value |= mask;
+ } else {
+ regs->data_value &= ~mask;
+ }
+
+ /* If the gpio is set to output... */
+ if (direction & mask) {
+ /* ...trigger the line-state IRQ */
+ ptrdiff_t set = aspeed_gpio_set_idx(s, regs);
+ size_t offset = set * GPIOS_PER_SET + gpio;
+ qemu_set_irq(s->gpios[offset], !!(new & mask));
+ } else {
+ /* ...otherwise if we meet the line's current IRQ policy... */
+ if (aspeed_evaluate_irq(regs, old & mask, gpio)) {
+ /* ...trigger the VIC IRQ */
+ s->pending++;
+ }
+ }
+ }
+ }
+ qemu_set_irq(s->irq, !!(s->pending));
+}
+
+static uint32_t aspeed_adjust_pin(AspeedGPIOState *s, uint32_t pin)
+{
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ /*
+ * The 2500 has a 4 pin gap in group AB and the 2400 has a 4 pin
+ * gap in group Y (and only four pins in AB but this is the last group so
+ * it doesn't matter).
+ */
+ if (agc->gap && pin >= agc->gap) {
+ pin += GPIO_PIN_GAP_SIZE;
+ }
+
+ return pin;
+}
+
+static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx,
+ uint32_t pin)
+{
+ uint32_t reg_val;
+ uint32_t pin_mask = 1 << pin;
+
+ reg_val = s->sets[set_idx].data_value;
+
+ return !!(reg_val & pin_mask);
+}
+
+static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx,
+ uint32_t pin, bool level)
+{
+ uint32_t value = s->sets[set_idx].data_value;
+ uint32_t pin_mask = 1 << pin;
+
+ if (level) {
+ value |= pin_mask;
+ } else {
+ value &= !pin_mask;
+ }
+
+ aspeed_gpio_update(s, &s->sets[set_idx], value);
+}
+
+/*
+ * | src_1 | src_2 | source |
+ * |-----------------------------|
+ * | 0 | 0 | ARM |
+ * | 0 | 1 | LPC |
+ * | 1 | 0 | Coprocessor|
+ * | 1 | 1 | Reserved |
+ *
+ * Once the source of a set is programmed, corresponding bits in the
+ * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and
+ * debounce registers can only be written by the source.
+ *
+ * Source is ARM by default
+ * only bits 24, 16, 8, and 0 can be set
+ *
+ * we don't currently have a model for the LPC or Coprocessor
+ */
+static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value,
+ uint32_t value)
+{
+ int i;
+ int cmd_source;
+
+ /* assume the source is always ARM for now */
+ int source = ASPEED_SOURCE_ARM;
+
+ uint32_t new_value = 0;
+
+ /* for each group in set */
+ for (i = 0; i < GPIOS_PER_REG; i += GPIOS_PER_GROUP) {
+ cmd_source = extract32(regs->cmd_source_0, i, 1)
+ | (extract32(regs->cmd_source_1, i, 1) << 1);
+
+ if (source == cmd_source) {
+ new_value |= (0xff << i) & value;
+ } else {
+ new_value |= (0xff << i) & old_value;
+ }
+ }
+ return new_value;
+}
+
+static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = {
+ /* Set ABCD */
+ [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value },
+ [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction },
+ [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable },
+ [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 },
+ [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 },
+ [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 },
+ [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status },
+ [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant },
+ [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 },
+ [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 },
+ [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 },
+ [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 },
+ [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read },
+ [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask },
+ /* Set EFGH */
+ [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value },
+ [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction },
+ [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable },
+ [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 },
+ [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 },
+ [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 },
+ [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status },
+ [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant },
+ [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 },
+ [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 },
+ [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 },
+ [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 },
+ [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read },
+ [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask },
+ /* Set IJKL */
+ [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value },
+ [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction },
+ [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable },
+ [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 },
+ [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 },
+ [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 },
+ [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status },
+ [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant },
+ [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 },
+ [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 },
+ [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 },
+ [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 },
+ [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read },
+ [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask },
+ /* Set MNOP */
+ [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value },
+ [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction },
+ [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable },
+ [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 },
+ [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 },
+ [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 },
+ [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status },
+ [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant },
+ [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 },
+ [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 },
+ [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 },
+ [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 },
+ [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read },
+ [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask },
+ /* Set QRST */
+ [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value },
+ [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction },
+ [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable },
+ [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 },
+ [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 },
+ [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 },
+ [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status },
+ [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant },
+ [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 },
+ [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 },
+ [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 },
+ [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 },
+ [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read },
+ [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask },
+ /* Set UVWX */
+ [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value },
+ [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction },
+ [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable },
+ [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 },
+ [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 },
+ [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 },
+ [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status },
+ [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant },
+ [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 },
+ [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 },
+ [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 },
+ [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 },
+ [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read },
+ [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask },
+ /* Set YZAAAB */
+ [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value },
+ [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction },
+ [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable },
+ [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 },
+ [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 },
+ [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 },
+ [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status },
+ [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant },
+ [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 },
+ [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 },
+ [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 },
+ [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 },
+ [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read },
+ [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask },
+ /* Set AC (ast2500 only) */
+ [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value },
+ [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction },
+ [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable },
+ [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 },
+ [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 },
+ [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 },
+ [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status },
+ [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant },
+ [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 },
+ [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 },
+ [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 },
+ [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 },
+ [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read },
+ [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask },
+};
+
+static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)
+{
+ AspeedGPIOState *s = ASPEED_GPIO(opaque);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ uint64_t idx = -1;
+ const AspeedGPIOReg *reg;
+ GPIOSets *set;
+
+ idx = offset >> 2;
+ if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {
+ idx -= GPIO_DEBOUNCE_TIME_1;
+ return (uint64_t) s->debounce_regs[idx];
+ }
+
+ reg = &agc->reg_table[idx];
+ if (reg->set_idx >= agc->nr_gpio_sets) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
+ HWADDR_PRIx"\n", __func__, offset);
+ return 0;
+ }
+
+ set = &s->sets[reg->set_idx];
+ switch (reg->type) {
+ case gpio_reg_data_value:
+ return set->data_value;
+ case gpio_reg_direction:
+ return set->direction;
+ case gpio_reg_int_enable:
+ return set->int_enable;
+ case gpio_reg_int_sens_0:
+ return set->int_sens_0;
+ case gpio_reg_int_sens_1:
+ return set->int_sens_1;
+ case gpio_reg_int_sens_2:
+ return set->int_sens_2;
+ case gpio_reg_int_status:
+ return set->int_status;
+ case gpio_reg_reset_tolerant:
+ return set->reset_tol;
+ case gpio_reg_debounce_1:
+ return set->debounce_1;
+ case gpio_reg_debounce_2:
+ return set->debounce_2;
+ case gpio_reg_cmd_source_0:
+ return set->cmd_source_0;
+ case gpio_reg_cmd_source_1:
+ return set->cmd_source_1;
+ case gpio_reg_data_read:
+ return set->data_read;
+ case gpio_reg_input_mask:
+ return set->input_mask;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
+ HWADDR_PRIx"\n", __func__, offset);
+ return 0;
+ };
+}
+
+static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,
+ uint32_t size)
+{
+ AspeedGPIOState *s = ASPEED_GPIO(opaque);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ const GPIOSetProperties *props;
+ uint64_t idx = -1;
+ const AspeedGPIOReg *reg;
+ GPIOSets *set;
+ uint32_t cleared;
+
+ idx = offset >> 2;
+ if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {
+ idx -= GPIO_DEBOUNCE_TIME_1;
+ s->debounce_regs[idx] = (uint32_t) data;
+ return;
+ }
+
+ reg = &agc->reg_table[idx];
+ if (reg->set_idx >= agc->nr_gpio_sets) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
+ HWADDR_PRIx"\n", __func__, offset);
+ return;
+ }
+
+ set = &s->sets[reg->set_idx];
+ props = &agc->props[reg->set_idx];
+
+ switch (reg->type) {
+ case gpio_reg_data_value:
+ data &= props->output;
+ data = update_value_control_source(set, set->data_value, data);
+ set->data_read = data;
+ aspeed_gpio_update(s, set, data);
+ return;
+ case gpio_reg_direction:
+ /*
+ * where data is the value attempted to be written to the pin:
+ * pin type | input mask | output mask | expected value
+ * ------------------------------------------------------------
+ * bidirectional | 1 | 1 | data
+ * input only | 1 | 0 | 0
+ * output only | 0 | 1 | 1
+ * no pin / gap | 0 | 0 | 0
+ *
+ * which is captured by:
+ * data = ( data | ~input) & output;
+ */
+ data = (data | ~props->input) & props->output;
+ set->direction = update_value_control_source(set, set->direction, data);
+ break;
+ case gpio_reg_int_enable:
+ set->int_enable = update_value_control_source(set, set->int_enable,
+ data);
+ break;
+ case gpio_reg_int_sens_0:
+ set->int_sens_0 = update_value_control_source(set, set->int_sens_0,
+ data);
+ break;
+ case gpio_reg_int_sens_1:
+ set->int_sens_1 = update_value_control_source(set, set->int_sens_1,
+ data);
+ break;
+ case gpio_reg_int_sens_2:
+ set->int_sens_2 = update_value_control_source(set, set->int_sens_2,
+ data);
+ break;
+ case gpio_reg_int_status:
+ cleared = ctpop32(data & set->int_status);
+ if (s->pending && cleared) {
+ assert(s->pending >= cleared);
+ s->pending -= cleared;
+ }
+ set->int_status &= ~data;
+ break;
+ case gpio_reg_reset_tolerant:
+ set->reset_tol = update_value_control_source(set, set->reset_tol,
+ data);
+ return;
+ case gpio_reg_debounce_1:
+ set->debounce_1 = update_value_control_source(set, set->debounce_1,
+ data);
+ return;
+ case gpio_reg_debounce_2:
+ set->debounce_2 = update_value_control_source(set, set->debounce_2,
+ data);
+ return;
+ case gpio_reg_cmd_source_0:
+ set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK;
+ return;
+ case gpio_reg_cmd_source_1:
+ set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK;
+ return;
+ case gpio_reg_data_read:
+ /* Read only register */
+ return;
+ case gpio_reg_input_mask:
+ /*
+ * feeds into interrupt generation
+ * 0: read from data value reg will be updated
+ * 1: read from data value reg will not be updated
+ */
+ set->input_mask = data & props->input;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
+ HWADDR_PRIx"\n", __func__, offset);
+ return;
+ }
+ aspeed_gpio_update(s, set, set->data_value);
+ return;
+}
+
+static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx)
+{
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ int set_idx, g_idx = *group_idx;
+
+ for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) {
+ const GPIOSetProperties *set_props = &agc->props[set_idx];
+ for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) {
+ if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) {
+ *group_idx = g_idx;
+ return set_idx;
+ }
+ }
+ }
+ return -1;
+}
+
+static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ int pin = 0xfff;
+ bool level = true;
+ char group[3];
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
+ int set_idx, group_idx = 0;
+
+ if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+ set_idx = get_set_idx(s, group, &group_idx);
+ if (set_idx == -1) {
+ error_setg(errp, "%s: invalid group %s", __func__, group);
+ return;
+ }
+ pin = pin + group_idx * GPIOS_PER_GROUP;
+ level = aspeed_gpio_get_pin_level(s, set_idx, pin);
+ visit_type_bool(v, name, &level, errp);
+}
+
+static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ Error *local_err = NULL;
+ bool level;
+ int pin = 0xfff;
+ char group[3];
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
+ int set_idx, group_idx = 0;
+
+ visit_type_bool(v, name, &level, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+ set_idx = get_set_idx(s, group, &group_idx);
+ if (set_idx == -1) {
+ error_setg(errp, "%s: invalid group %s", __func__, group);
+ return;
+ }
+ pin = pin + group_idx * GPIOS_PER_GROUP;
+ aspeed_gpio_set_pin_level(s, set_idx, pin, level);
+}
+
+/****************** Setup functions ******************/
+static const GPIOSetProperties ast2400_set_props[] = {
+ [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
+ [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
+ [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
+ [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
+ [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
+ [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} },
+ [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} },
+};
+
+static const GPIOSetProperties ast2500_set_props[] = {
+ [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
+ [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
+ [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
+ [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
+ [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
+ [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} },
+ [6] = {0xffffff0f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} },
+ [7] = {0x000000ff, 0x000000ff, {"AC"} },
+};
+
+static const MemoryRegionOps aspeed_gpio_ops = {
+ .read = aspeed_gpio_read,
+ .write = aspeed_gpio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+};
+
+static void aspeed_gpio_reset(DeviceState *dev)
+{
+ AspeedGPIOState *s = ASPEED_GPIO(dev);
+
+ /* TODO: respect the reset tolerance registers */
+ memset(s->sets, 0, sizeof(s->sets));
+}
+
+static void aspeed_gpio_realize(DeviceState *dev, Error **errp)
+{
+ AspeedGPIOState *s = ASPEED_GPIO(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ int pin;
+
+ /* Interrupt parent line */
+ sysbus_init_irq(sbd, &s->irq);
+
+ /* Individual GPIOs */
+ for (pin = 0; pin < agc->nr_gpio_pins; pin++) {
+ sysbus_init_irq(sbd, &s->gpios[pin]);
+ }
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,
+ TYPE_ASPEED_GPIO, GPIO_3_6V_MEM_SIZE);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_gpio_init(Object *obj)
+{
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ int pin;
+
+ for (pin = 0; pin < agc->nr_gpio_pins; pin++) {
+ char *name;
+ int set_idx = pin / GPIOS_PER_SET;
+ int pin_idx = aspeed_adjust_pin(s, pin) - (set_idx * GPIOS_PER_SET);
+ int group_idx = pin_idx >> GPIO_GROUP_SHIFT;
+ const GPIOSetProperties *props = &agc->props[set_idx];
+
+ name = g_strdup_printf("gpio%s%d", props->group_label[group_idx],
+ pin_idx % GPIOS_PER_GROUP);
+ object_property_add(obj, name, "bool", aspeed_gpio_get_pin,
+ aspeed_gpio_set_pin, NULL, NULL, NULL);
+ }
+}
+
+static const VMStateDescription vmstate_gpio_regs = {
+ .name = TYPE_ASPEED_GPIO"/regs",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(data_value, GPIOSets),
+ VMSTATE_UINT32(data_read, GPIOSets),
+ VMSTATE_UINT32(direction, GPIOSets),
+ VMSTATE_UINT32(int_enable, GPIOSets),
+ VMSTATE_UINT32(int_sens_0, GPIOSets),
+ VMSTATE_UINT32(int_sens_1, GPIOSets),
+ VMSTATE_UINT32(int_sens_2, GPIOSets),
+ VMSTATE_UINT32(int_status, GPIOSets),
+ VMSTATE_UINT32(reset_tol, GPIOSets),
+ VMSTATE_UINT32(cmd_source_0, GPIOSets),
+ VMSTATE_UINT32(cmd_source_1, GPIOSets),
+ VMSTATE_UINT32(debounce_1, GPIOSets),
+ VMSTATE_UINT32(debounce_2, GPIOSets),
+ VMSTATE_UINT32(input_mask, GPIOSets),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static const VMStateDescription vmstate_aspeed_gpio = {
+ .name = TYPE_ASPEED_GPIO,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS,
+ 1, vmstate_gpio_regs, GPIOSets),
+ VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState,
+ ASPEED_GPIO_NR_DEBOUNCE_REGS),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void aspeed_gpio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_gpio_realize;
+ dc->reset = aspeed_gpio_reset;
+ dc->desc = "Aspeed GPIO Controller";
+ dc->vmsd = &vmstate_aspeed_gpio;
+}
+
+static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data)
+{
+ AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
+
+ agc->props = ast2400_set_props;
+ agc->nr_gpio_pins = 216;
+ agc->nr_gpio_sets = 7;
+ agc->gap = 196;
+ agc->reg_table = aspeed_3_6v_gpios;
+}
+
+static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)
+{
+ AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
+
+ agc->props = ast2500_set_props;
+ agc->nr_gpio_pins = 228;
+ agc->nr_gpio_sets = 8;
+ agc->gap = 220;
+ agc->reg_table = aspeed_3_6v_gpios;
+}
+
+static const TypeInfo aspeed_gpio_info = {
+ .name = TYPE_ASPEED_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedGPIOState),
+ .class_size = sizeof(AspeedGPIOClass),
+ .class_init = aspeed_gpio_class_init,
+ .abstract = true,
+};
+
+static const TypeInfo aspeed_gpio_ast2400_info = {
+ .name = TYPE_ASPEED_GPIO "-ast2400",
+ .parent = TYPE_ASPEED_GPIO,
+ .class_init = aspeed_gpio_ast2400_class_init,
+ .instance_init = aspeed_gpio_init,
+};
+
+static const TypeInfo aspeed_gpio_ast2500_info = {
+ .name = TYPE_ASPEED_GPIO "-ast2500",
+ .parent = TYPE_ASPEED_GPIO,
+ .class_init = aspeed_gpio_2500_class_init,
+ .instance_init = aspeed_gpio_init,
+};
+
+static void aspeed_gpio_register_types(void)
+{
+ type_register_static(&aspeed_gpio_info);
+ type_register_static(&aspeed_gpio_ast2400_info);
+ type_register_static(&aspeed_gpio_ast2500_info);
+}
+
+type_init(aspeed_gpio_register_types);
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 6350438036..c7a9d6315c 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -29,6 +29,7 @@ config PC
select MC146818RTC
# For ACPI builder:
select SERIAL_ISA
+ select ACPI_PCI
select ACPI_VMGENID
select VIRTIO_PMEM_SUPPORTED
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 5d9c9efd5f..d3374e0831 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -1,5 +1,5 @@
obj-$(CONFIG_KVM) += kvm/
-obj-y += multiboot.o
+obj-y += e820_memory_layout.o multiboot.o
obj-y += pc.o
obj-$(CONFIG_I440FX) += pc_piix.o
obj-$(CONFIG_Q35) += pc_q35.o
diff --git a/hw/i386/e820_memory_layout.c b/hw/i386/e820_memory_layout.c
new file mode 100644
index 0000000000..bcf9eaf837
--- /dev/null
+++ b/hw/i386/e820_memory_layout.c
@@ -0,0 +1,59 @@
+/*
+ * QEMU BIOS e820 routines
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "e820_memory_layout.h"
+
+static size_t e820_entries;
+struct e820_table e820_reserve;
+struct e820_entry *e820_table;
+
+int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
+{
+ int index = le32_to_cpu(e820_reserve.count);
+ struct e820_entry *entry;
+
+ if (type != E820_RAM) {
+ /* old FW_CFG_E820_TABLE entry -- reservations only */
+ if (index >= E820_NR_ENTRIES) {
+ return -EBUSY;
+ }
+ entry = &e820_reserve.entry[index++];
+
+ entry->address = cpu_to_le64(address);
+ entry->length = cpu_to_le64(length);
+ entry->type = cpu_to_le32(type);
+
+ e820_reserve.count = cpu_to_le32(index);
+ }
+
+ /* new "etc/e820" file -- include ram too */
+ e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
+ e820_table[e820_entries].address = cpu_to_le64(address);
+ e820_table[e820_entries].length = cpu_to_le64(length);
+ e820_table[e820_entries].type = cpu_to_le32(type);
+ e820_entries++;
+
+ return e820_entries;
+}
+
+int e820_get_num_entries(void)
+{
+ return e820_entries;
+}
+
+bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
+{
+ if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
+ *address = le64_to_cpu(e820_table[idx].address);
+ *length = le64_to_cpu(e820_table[idx].length);
+ return true;
+ }
+ return false;
+}
diff --git a/hw/i386/e820_memory_layout.h b/hw/i386/e820_memory_layout.h
new file mode 100644
index 0000000000..2a0ceb8b9c
--- /dev/null
+++ b/hw/i386/e820_memory_layout.h
@@ -0,0 +1,42 @@
+/*
+ * QEMU BIOS e820 routines
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef HW_I386_E820_H
+#define HW_I386_E820_H
+
+/* e820 types */
+#define E820_RAM 1
+#define E820_RESERVED 2
+#define E820_ACPI 3
+#define E820_NVS 4
+#define E820_UNUSABLE 5
+
+#define E820_NR_ENTRIES 16
+
+struct e820_entry {
+ uint64_t address;
+ uint64_t length;
+ uint32_t type;
+} QEMU_PACKED __attribute((__aligned__(4)));
+
+struct e820_table {
+ uint32_t count;
+ struct e820_entry entry[E820_NR_ENTRIES];
+} QEMU_PACKED __attribute((__aligned__(4)));
+
+extern struct e820_table e820_reserve;
+extern struct e820_entry *e820_table;
+
+int e820_add_entry(uint64_t address, uint64_t length, uint32_t type);
+int e820_get_num_entries(void);
+bool e820_get_entry(int index, uint32_t type,
+ uint64_t *address, uint64_t *length);
+
+
+
+#endif
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c
index 380a819230..39b6bc6052 100644
--- a/hw/i386/fw_cfg.c
+++ b/hw/i386/fw_cfg.c
@@ -13,8 +13,15 @@
*/
#include "qemu/osdep.h"
+#include "sysemu/numa.h"
+#include "hw/acpi/acpi.h"
+#include "hw/firmware/smbios.h"
+#include "hw/i386/pc.h"
#include "hw/i386/fw_cfg.h"
+#include "hw/timer/hpet.h"
#include "hw/nvram/fw_cfg.h"
+#include "e820_memory_layout.h"
+#include "kvm_i386.h"
const char *fw_cfg_arch_key_name(uint16_t key)
{
@@ -36,3 +43,133 @@ const char *fw_cfg_arch_key_name(uint16_t key)
}
return NULL;
}
+
+void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
+{
+ uint8_t *smbios_tables, *smbios_anchor;
+ size_t smbios_tables_len, smbios_anchor_len;
+ struct smbios_phys_mem_area *mem_array;
+ unsigned i, array_count;
+ X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
+
+ /* tell smbios about cpuid version and features */
+ smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
+
+ smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
+ if (smbios_tables) {
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
+ smbios_tables, smbios_tables_len);
+ }
+
+ /* build the array of physical mem area from e820 table */
+ mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
+ for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
+ uint64_t addr, len;
+
+ if (e820_get_entry(i, E820_RAM, &addr, &len)) {
+ mem_array[array_count].address = addr;
+ mem_array[array_count].length = len;
+ array_count++;
+ }
+ }
+ smbios_get_tables(ms, mem_array, array_count,
+ &smbios_tables, &smbios_tables_len,
+ &smbios_anchor, &smbios_anchor_len);
+ g_free(mem_array);
+
+ if (smbios_anchor) {
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
+ smbios_tables, smbios_tables_len);
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
+ smbios_anchor, smbios_anchor_len);
+ }
+}
+
+FWCfgState *fw_cfg_arch_create(MachineState *ms,
+ uint16_t boot_cpus,
+ uint16_t apic_id_limit)
+{
+ FWCfgState *fw_cfg;
+ uint64_t *numa_fw_cfg;
+ int i;
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+ const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
+ int nb_numa_nodes = ms->numa_state->num_nodes;
+
+ fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
+ &address_space_memory);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
+
+ /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
+ *
+ * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
+ * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
+ * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
+ * for CPU hotplug also uses APIC ID and not "CPU index".
+ * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
+ * but the "limit to the APIC ID values SeaBIOS may see".
+ *
+ * So for compatibility reasons with old BIOSes we are stuck with
+ * "etc/max-cpus" actually being apic_id_limit
+ */
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
+ acpi_tables, acpi_tables_len);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
+
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
+ &e820_reserve, sizeof(e820_reserve));
+ fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
+ sizeof(struct e820_entry) * e820_get_num_entries());
+
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
+ /* allocate memory for the NUMA channel: one (64bit) word for the number
+ * of nodes, one word for each VCPU->node and one word for each node to
+ * hold the amount of memory.
+ */
+ numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
+ numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
+ for (i = 0; i < cpus->len; i++) {
+ unsigned int apic_id = cpus->cpus[i].arch_id;
+ assert(apic_id < apic_id_limit);
+ numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
+ }
+ for (i = 0; i < nb_numa_nodes; i++) {
+ numa_fw_cfg[apic_id_limit + 1 + i] =
+ cpu_to_le64(ms->numa_state->nodes[i].node_mem);
+ }
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
+ (1 + apic_id_limit + nb_numa_nodes) *
+ sizeof(*numa_fw_cfg));
+
+ return fw_cfg;
+}
+
+void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
+{
+ X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
+ CPUX86State *env = &cpu->env;
+ uint32_t unused, ecx, edx;
+ uint64_t feature_control_bits = 0;
+ uint64_t *val;
+
+ cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
+ if (ecx & CPUID_EXT_VMX) {
+ feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
+ }
+
+ if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
+ (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
+ (env->mcg_cap & MCG_LMCE_P)) {
+ feature_control_bits |= FEATURE_CONTROL_LMCE;
+ }
+
+ if (!feature_control_bits) {
+ return;
+ }
+
+ val = g_malloc(sizeof(*val));
+ *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
+ fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
+}
diff --git a/hw/i386/fw_cfg.h b/hw/i386/fw_cfg.h
index 17a4bc32f2..e0856a3769 100644
--- a/hw/i386/fw_cfg.h
+++ b/hw/i386/fw_cfg.h
@@ -9,6 +9,7 @@
#ifndef HW_I386_FW_CFG_H
#define HW_I386_FW_CFG_H
+#include "hw/boards.h"
#include "hw/nvram/fw_cfg.h"
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
@@ -17,4 +18,10 @@
#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
+FWCfgState *fw_cfg_arch_create(MachineState *ms,
+ uint16_t boot_cpus,
+ uint16_t apic_id_limit);
+void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg);
+void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg);
+
#endif
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0a6fa6e549..bcda50efcc 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -87,6 +87,8 @@
#include "sysemu/replay.h"
#include "qapi/qmp/qerror.h"
#include "config-devices.h"
+#include "e820_memory_layout.h"
+#include "fw_cfg.h"
/* debug PC/ISA interrupts */
//#define DEBUG_IRQ
@@ -98,22 +100,6 @@
#define DPRINTF(fmt, ...)
#endif
-#define E820_NR_ENTRIES 16
-
-struct e820_entry {
- uint64_t address;
- uint64_t length;
- uint32_t type;
-} QEMU_PACKED __attribute((__aligned__(4)));
-
-struct e820_table {
- uint32_t count;
- struct e820_entry entry[E820_NR_ENTRIES];
-} QEMU_PACKED __attribute((__aligned__(4)));
-
-static struct e820_table e820_reserve;
-static struct e820_entry *e820_table;
-static unsigned e820_entries;
struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
/* Physical Address of PVH entry point read from kernel ELF NOTE */
@@ -880,50 +866,6 @@ static void handle_a20_line_change(void *opaque, int irq, int level)
x86_cpu_set_a20(cpu, level);
}
-int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
-{
- int index = le32_to_cpu(e820_reserve.count);
- struct e820_entry *entry;
-
- if (type != E820_RAM) {
- /* old FW_CFG_E820_TABLE entry -- reservations only */
- if (index >= E820_NR_ENTRIES) {
- return -EBUSY;
- }
- entry = &e820_reserve.entry[index++];
-
- entry->address = cpu_to_le64(address);
- entry->length = cpu_to_le64(length);
- entry->type = cpu_to_le32(type);
-
- e820_reserve.count = cpu_to_le32(index);
- }
-
- /* new "etc/e820" file -- include ram too */
- e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
- e820_table[e820_entries].address = cpu_to_le64(address);
- e820_table[e820_entries].length = cpu_to_le64(length);
- e820_table[e820_entries].type = cpu_to_le32(type);
- e820_entries++;
-
- return e820_entries;
-}
-
-int e820_get_num_entries(void)
-{
- return e820_entries;
-}
-
-bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
-{
- if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
- *address = le64_to_cpu(e820_table[idx].address);
- *length = le64_to_cpu(e820_table[idx].length);
- return true;
- }
- return false;
-}
-
/* Calculates initial APIC ID for a specific CPU index
*
* Currently we need to be able to calculate the APIC ID from the CPU index
@@ -953,108 +895,6 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
}
}
-static void pc_build_smbios(PCMachineState *pcms)
-{
- uint8_t *smbios_tables, *smbios_anchor;
- size_t smbios_tables_len, smbios_anchor_len;
- struct smbios_phys_mem_area *mem_array;
- unsigned i, array_count;
- MachineState *ms = MACHINE(pcms);
- X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
-
- /* tell smbios about cpuid version and features */
- smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
-
- smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
- if (smbios_tables) {
- fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
- smbios_tables, smbios_tables_len);
- }
-
- /* build the array of physical mem area from e820 table */
- mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
- for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
- uint64_t addr, len;
-
- if (e820_get_entry(i, E820_RAM, &addr, &len)) {
- mem_array[array_count].address = addr;
- mem_array[array_count].length = len;
- array_count++;
- }
- }
- smbios_get_tables(ms, mem_array, array_count,
- &smbios_tables, &smbios_tables_len,
- &smbios_anchor, &smbios_anchor_len);
- g_free(mem_array);
-
- if (smbios_anchor) {
- fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
- smbios_tables, smbios_tables_len);
- fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
- smbios_anchor, smbios_anchor_len);
- }
-}
-
-static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
-{
- FWCfgState *fw_cfg;
- uint64_t *numa_fw_cfg;
- int i;
- const CPUArchIdList *cpus;
- MachineClass *mc = MACHINE_GET_CLASS(pcms);
- MachineState *ms = MACHINE(pcms);
- int nb_numa_nodes = ms->numa_state->num_nodes;
-
- fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
-
- /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
- *
- * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
- * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
- * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
- * for CPU hotplug also uses APIC ID and not "CPU index".
- * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
- * but the "limit to the APIC ID values SeaBIOS may see".
- *
- * So for compatibility reasons with old BIOSes we are stuck with
- * "etc/max-cpus" actually being apic_id_limit
- */
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
- fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
- acpi_tables, acpi_tables_len);
- fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
-
- fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
- &e820_reserve, sizeof(e820_reserve));
- fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
- sizeof(struct e820_entry) * e820_entries);
-
- fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
- /* allocate memory for the NUMA channel: one (64bit) word for the number
- * of nodes, one word for each VCPU->node and one word for each node to
- * hold the amount of memory.
- */
- numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
- numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
- cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
- for (i = 0; i < cpus->len; i++) {
- unsigned int apic_id = cpus->cpus[i].arch_id;
- assert(apic_id < pcms->apic_id_limit);
- numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
- }
- for (i = 0; i < nb_numa_nodes; i++) {
- numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
- cpu_to_le64(ms->numa_state->nodes[i].node_mem);
- }
- fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
- (1 + pcms->apic_id_limit + nb_numa_nodes) *
- sizeof(*numa_fw_cfg));
-
- return fw_cfg;
-}
-
static long get_file_size(FILE *f)
{
long where, size;
@@ -1672,7 +1512,7 @@ void pc_cpus_init(PCMachineState *pcms)
* Limit for the APIC ID value, so that all
* CPU APIC IDs are < pcms->apic_id_limit.
*
- * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
+ * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
*/
pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
ms->smp.max_cpus - 1) + 1;
@@ -1682,35 +1522,6 @@ void pc_cpus_init(PCMachineState *pcms)
}
}
-static void pc_build_feature_control_file(PCMachineState *pcms)
-{
- MachineState *ms = MACHINE(pcms);
- X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
- CPUX86State *env = &cpu->env;
- uint32_t unused, ecx, edx;
- uint64_t feature_control_bits = 0;
- uint64_t *val;
-
- cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
- if (ecx & CPUID_EXT_VMX) {
- feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
- }
-
- if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
- (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
- (env->mcg_cap & MCG_LMCE_P)) {
- feature_control_bits |= FEATURE_CONTROL_LMCE;
- }
-
- if (!feature_control_bits) {
- return;
- }
-
- val = g_malloc(sizeof(*val));
- *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
- fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
-}
-
static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
{
if (cpus_count > 0xff) {
@@ -1753,8 +1564,8 @@ void pc_machine_done(Notifier *notifier, void *data)
acpi_setup();
if (pcms->fw_cfg) {
- pc_build_smbios(pcms);
- pc_build_feature_control_file(pcms);
+ fw_cfg_build_smbios(MACHINE(pcms), pcms->fw_cfg);
+ fw_cfg_build_feature_control(MACHINE(pcms), pcms->fw_cfg);
/* update FW_CFG_NB_CPUS to account for -device added CPUs */
fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
}
@@ -1831,6 +1642,7 @@ void pc_memory_init(PCMachineState *pcms,
MemoryRegion *ram_below_4g, *ram_above_4g;
FWCfgState *fw_cfg;
MachineState *machine = MACHINE(pcms);
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
assert(machine->ram_size == pcms->below_4g_mem_size +
@@ -1864,7 +1676,6 @@ void pc_memory_init(PCMachineState *pcms,
if (!pcmc->has_reserved_memory &&
(machine->ram_slots ||
(machine->maxram_size > machine->ram_size))) {
- MachineClass *mc = MACHINE_GET_CLASS(machine);
error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
mc->name);
@@ -1927,7 +1738,8 @@ void pc_memory_init(PCMachineState *pcms,
option_rom_mr,
1);
- fw_cfg = bochs_bios_init(&address_space_memory, pcms);
+ fw_cfg = fw_cfg_arch_create(machine,
+ pcms->boot_cpus, pcms->apic_id_limit);
rom_set_fw(fw_cfg);
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 268cb24e56..620b25c204 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -164,25 +164,13 @@ static uint32_t aspeed_scu_get_random(void)
return num;
}
-static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
+uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
{
- uint32_t apb_divider;
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
+ uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
- switch (s->silicon_rev) {
- case AST2400_A0_SILICON_REV:
- case AST2400_A1_SILICON_REV:
- apb_divider = 2;
- break;
- case AST2500_A0_SILICON_REV:
- case AST2500_A1_SILICON_REV:
- apb_divider = 4;
- break;
- default:
- g_assert_not_reached();
- }
-
- s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
- / apb_divider;
+ return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
+ / asc->apb_divider;
}
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
@@ -241,7 +229,6 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
return;
case CLK_SEL:
s->regs[reg] = data;
- aspeed_scu_set_apb_freq(s);
break;
case HW_STRAP1:
if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
@@ -303,11 +290,11 @@ static const uint32_t hpll_ast2400_freqs[][4] = {
{ 400, 375, 350, 425 }, /* 25MHz */
};
-static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
+static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
{
- uint32_t hpll_reg = s->regs[HPLL_PARAM];
uint8_t freq_select;
bool clk_25m_in;
+ uint32_t clkin = aspeed_scu_get_clkin(s);
if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
return 0;
@@ -324,7 +311,7 @@ static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
multiplier = (2 - od) * ((n + 2) / (d + 1));
}
- return s->clkin * multiplier;
+ return clkin * multiplier;
}
/* HW strapping */
@@ -334,10 +321,10 @@ static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
}
-static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
+static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
{
- uint32_t hpll_reg = s->regs[HPLL_PARAM];
uint32_t multiplier = 1;
+ uint32_t clkin = aspeed_scu_get_clkin(s);
if (hpll_reg & SCU_H_PLL_OFF) {
return 0;
@@ -351,42 +338,19 @@ static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
multiplier = ((m + 1) / (n + 1)) / (p + 1);
}
- return s->clkin * multiplier;
+ return clkin * multiplier;
}
static void aspeed_scu_reset(DeviceState *dev)
{
AspeedSCUState *s = ASPEED_SCU(dev);
- const uint32_t *reset;
- uint32_t (*calc_hpll)(AspeedSCUState *s);
-
- switch (s->silicon_rev) {
- case AST2400_A0_SILICON_REV:
- case AST2400_A1_SILICON_REV:
- reset = ast2400_a0_resets;
- calc_hpll = aspeed_scu_calc_hpll_ast2400;
- break;
- case AST2500_A0_SILICON_REV:
- case AST2500_A1_SILICON_REV:
- reset = ast2500_a1_resets;
- calc_hpll = aspeed_scu_calc_hpll_ast2500;
- break;
- default:
- g_assert_not_reached();
- }
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
- memcpy(s->regs, reset, sizeof(s->regs));
+ memcpy(s->regs, asc->resets, sizeof(s->regs));
s->regs[SILICON_REV] = s->silicon_rev;
s->regs[HW_STRAP1] = s->hw_strap1;
s->regs[HW_STRAP2] = s->hw_strap2;
s->regs[PROT_KEY] = s->hw_prot_key;
-
- /*
- * All registers are set. Now compute the frequencies of the main clocks
- */
- s->clkin = aspeed_scu_get_clkin(s);
- s->hpll = calc_hpll(s);
- aspeed_scu_set_apb_freq(s);
}
static uint32_t aspeed_silicon_revs[] = {
@@ -459,11 +423,51 @@ static const TypeInfo aspeed_scu_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedSCUState),
.class_init = aspeed_scu_class_init,
+ .class_size = sizeof(AspeedSCUClass),
+ .abstract = true,
+};
+
+static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
+
+ dc->desc = "ASPEED 2400 System Control Unit";
+ asc->resets = ast2400_a0_resets;
+ asc->calc_hpll = aspeed_2400_scu_calc_hpll;
+ asc->apb_divider = 2;
+}
+
+static const TypeInfo aspeed_2400_scu_info = {
+ .name = TYPE_ASPEED_2400_SCU,
+ .parent = TYPE_ASPEED_SCU,
+ .instance_size = sizeof(AspeedSCUState),
+ .class_init = aspeed_2400_scu_class_init,
+};
+
+static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
+
+ dc->desc = "ASPEED 2500 System Control Unit";
+ asc->resets = ast2500_a1_resets;
+ asc->calc_hpll = aspeed_2500_scu_calc_hpll;
+ asc->apb_divider = 4;
+}
+
+static const TypeInfo aspeed_2500_scu_info = {
+ .name = TYPE_ASPEED_2500_SCU,
+ .parent = TYPE_ASPEED_SCU,
+ .instance_size = sizeof(AspeedSCUState),
+ .class_init = aspeed_2500_scu_class_init,
};
static void aspeed_scu_register_types(void)
{
type_register_static(&aspeed_scu_info);
+ type_register_static(&aspeed_2400_scu_info);
+ type_register_static(&aspeed_2500_scu_info);
}
type_init(aspeed_scu_register_types);
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 9f3cff5fb6..9ffc7e0117 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -28,6 +28,8 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "exec/address-spaces.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
@@ -75,6 +77,10 @@
#define CTRL_CMD_MASK 0xff
#define CTRL_DUMMY_HIGH_SHIFT 14
#define CTRL_AST2400_SPI_4BYTE (1 << 13)
+#define CE_CTRL_CLOCK_FREQ_SHIFT 8
+#define CE_CTRL_CLOCK_FREQ_MASK 0xf
+#define CE_CTRL_CLOCK_FREQ(div) \
+ (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
#define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
#define CTRL_CE_STOP_ACTIVE (1 << 2)
#define CTRL_CMD_MODE_MASK 0x3
@@ -110,10 +116,10 @@
#define DMA_CTRL_DELAY_SHIFT 8
#define DMA_CTRL_FREQ_MASK 0xf
#define DMA_CTRL_FREQ_SHIFT 4
-#define DMA_CTRL_MODE (1 << 3)
+#define DMA_CTRL_CALIB (1 << 3)
#define DMA_CTRL_CKSUM (1 << 2)
-#define DMA_CTRL_DIR (1 << 1)
-#define DMA_CTRL_EN (1 << 0)
+#define DMA_CTRL_WRITE (1 << 1)
+#define DMA_CTRL_ENABLE (1 << 0)
/* DMA Flash Side Address */
#define R_DMA_FLASH_ADDR (0x84 / 4)
@@ -145,6 +151,24 @@
#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
#define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
+/*
+ * DMA DRAM addresses should be 4 bytes aligned and the valid address
+ * range is 0x40000000 - 0x5FFFFFFF (AST2400)
+ * 0x80000000 - 0xBFFFFFFF (AST2500)
+ *
+ * DMA flash addresses should be 4 bytes aligned and the valid address
+ * range is 0x20000000 - 0x2FFFFFFF.
+ *
+ * DMA length is from 4 bytes to 32MB
+ * 0: 4 bytes
+ * 0x7FFFFF: 32M bytes
+ */
+#define DMA_DRAM_ADDR(s, val) ((s)->sdram_base | \
+ ((val) & (s)->ctrl->dma_dram_mask))
+#define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \
+ ((val) & (s)->ctrl->dma_flash_mask))
+#define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
+
/* Flash opcodes. */
#define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
@@ -190,7 +214,7 @@ static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
static const AspeedSMCController controllers[] = {
{
- .name = "aspeed.smc.smc",
+ .name = "aspeed.smc-ast2400",
.r_conf = R_CONF,
.r_ce_ctrl = R_CE_CTRL,
.r_ctrl0 = R_CTRL0,
@@ -203,7 +227,7 @@ static const AspeedSMCController controllers[] = {
.has_dma = false,
.nregs = ASPEED_SMC_R_SMC_MAX,
}, {
- .name = "aspeed.smc.fmc",
+ .name = "aspeed.fmc-ast2400",
.r_conf = R_CONF,
.r_ce_ctrl = R_CE_CTRL,
.r_ctrl0 = R_CTRL0,
@@ -214,9 +238,11 @@ static const AspeedSMCController controllers[] = {
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
.has_dma = true,
+ .dma_flash_mask = 0x0FFFFFFC,
+ .dma_dram_mask = 0x1FFFFFFC,
.nregs = ASPEED_SMC_R_MAX,
}, {
- .name = "aspeed.smc.spi",
+ .name = "aspeed.spi1-ast2400",
.r_conf = R_SPI_CONF,
.r_ce_ctrl = 0xff,
.r_ctrl0 = R_SPI_CTRL0,
@@ -229,7 +255,7 @@ static const AspeedSMCController controllers[] = {
.has_dma = false,
.nregs = ASPEED_SMC_R_SPI_MAX,
}, {
- .name = "aspeed.smc.ast2500-fmc",
+ .name = "aspeed.fmc-ast2500",
.r_conf = R_CONF,
.r_ce_ctrl = R_CE_CTRL,
.r_ctrl0 = R_CTRL0,
@@ -240,9 +266,11 @@ static const AspeedSMCController controllers[] = {
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
.has_dma = true,
+ .dma_flash_mask = 0x0FFFFFFC,
+ .dma_dram_mask = 0x3FFFFFFC,
.nregs = ASPEED_SMC_R_MAX,
}, {
- .name = "aspeed.smc.ast2500-spi1",
+ .name = "aspeed.spi1-ast2500",
.r_conf = R_CONF,
.r_ce_ctrl = R_CE_CTRL,
.r_ctrl0 = R_CTRL0,
@@ -255,7 +283,7 @@ static const AspeedSMCController controllers[] = {
.has_dma = false,
.nregs = ASPEED_SMC_R_MAX,
}, {
- .name = "aspeed.smc.ast2500-spi2",
+ .name = "aspeed.spi2-ast2500",
.r_conf = R_CONF,
.r_ce_ctrl = R_CE_CTRL,
.r_ctrl0 = R_CTRL0,
@@ -732,9 +760,6 @@ static void aspeed_smc_reset(DeviceState *d)
memset(s->regs, 0, sizeof s->regs);
- /* Pretend DMA is done (u-boot initialization) */
- s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS;
-
/* Unselect all slaves */
for (i = 0; i < s->num_cs; ++i) {
s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
@@ -775,6 +800,11 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
addr == s->r_ce_ctrl ||
addr == R_INTR_CTRL ||
addr == R_DUMMY_DATA ||
+ (s->ctrl->has_dma && addr == R_DMA_CTRL) ||
+ (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) ||
+ (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
+ (s->ctrl->has_dma && addr == R_DMA_LEN) ||
+ (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
return s->regs[addr];
@@ -785,6 +815,243 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
}
}
+static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
+{
+ /* HCLK/1 .. HCLK/16 */
+ const uint8_t hclk_divisors[] = {
+ 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
+ if (hclk_mask == hclk_divisors[i]) {
+ return i + 1;
+ }
+ }
+
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask);
+ return 0;
+}
+
+/*
+ * When doing calibration, the SPI clock rate in the CE0 Control
+ * Register and the read delay cycles in the Read Timing Compensation
+ * Register are set using bit[11:4] of the DMA Control Register.
+ */
+static void aspeed_smc_dma_calibration(AspeedSMCState *s)
+{
+ uint8_t delay =
+ (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
+ uint8_t hclk_mask =
+ (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
+ uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
+ uint32_t hclk_shift = (hclk_div - 1) << 2;
+ uint8_t cs;
+
+ /*
+ * The Read Timing Compensation Register values apply to all CS on
+ * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays
+ */
+ if (hclk_div && hclk_div < 6) {
+ s->regs[s->r_timings] &= ~(0xf << hclk_shift);
+ s->regs[s->r_timings] |= delay << hclk_shift;
+ }
+
+ /*
+ * TODO: compute the CS from the DMA address and the segment
+ * registers. This is not really a problem for now because the
+ * Timing Register values apply to all CS and software uses CS0 to
+ * do calibration.
+ */
+ cs = 0;
+ s->regs[s->r_ctrl0 + cs] &=
+ ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
+ s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
+}
+
+/*
+ * Emulate read errors in the DMA Checksum Register for high
+ * frequencies and optimistic settings of the Read Timing Compensation
+ * Register. This will help in tuning the SPI timing calibration
+ * algorithm.
+ */
+static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
+{
+ uint8_t delay =
+ (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
+ uint8_t hclk_mask =
+ (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
+
+ /*
+ * Typical values of a palmetto-bmc machine.
+ */
+ switch (aspeed_smc_hclk_divisor(hclk_mask)) {
+ case 4 ... 16:
+ return false;
+ case 3: /* at least one HCLK cycle delay */
+ return (delay & 0x7) < 1;
+ case 2: /* at least two HCLK cycle delay */
+ return (delay & 0x7) < 2;
+ case 1: /* (> 100MHz) is above the max freq of the controller */
+ return true;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+/*
+ * Accumulate the result of the reads to provide a checksum that will
+ * be used to validate the read timing settings.
+ */
+static void aspeed_smc_dma_checksum(AspeedSMCState *s)
+{
+ MemTxResult result;
+ uint32_t data;
+
+ if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid direction for DMA checksum\n", __func__);
+ return;
+ }
+
+ if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
+ aspeed_smc_dma_calibration(s);
+ }
+
+ while (s->regs[R_DMA_LEN]) {
+ data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
+ __func__, s->regs[R_DMA_FLASH_ADDR]);
+ return;
+ }
+
+ /*
+ * When the DMA is on-going, the DMA registers are updated
+ * with the current working addresses and length.
+ */
+ s->regs[R_DMA_CHECKSUM] += data;
+ s->regs[R_DMA_FLASH_ADDR] += 4;
+ s->regs[R_DMA_LEN] -= 4;
+ }
+
+ if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
+ s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
+ }
+
+}
+
+static void aspeed_smc_dma_rw(AspeedSMCState *s)
+{
+ MemTxResult result;
+ uint32_t data;
+
+ while (s->regs[R_DMA_LEN]) {
+ if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
+ data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n",
+ __func__, s->regs[R_DMA_DRAM_ADDR]);
+ return;
+ }
+
+ address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
+ data, MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash write failed @%08x\n",
+ __func__, s->regs[R_DMA_FLASH_ADDR]);
+ return;
+ }
+ } else {
+ data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
+ __func__, s->regs[R_DMA_FLASH_ADDR]);
+ return;
+ }
+
+ address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
+ data, MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n",
+ __func__, s->regs[R_DMA_DRAM_ADDR]);
+ return;
+ }
+ }
+
+ /*
+ * When the DMA is on-going, the DMA registers are updated
+ * with the current working addresses and length.
+ */
+ s->regs[R_DMA_FLASH_ADDR] += 4;
+ s->regs[R_DMA_DRAM_ADDR] += 4;
+ s->regs[R_DMA_LEN] -= 4;
+ s->regs[R_DMA_CHECKSUM] += data;
+ }
+}
+
+static void aspeed_smc_dma_stop(AspeedSMCState *s)
+{
+ /*
+ * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
+ * engine is idle
+ */
+ s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
+ s->regs[R_DMA_CHECKSUM] = 0;
+
+ /*
+ * Lower the DMA irq in any case. The IRQ control register could
+ * have been cleared before disabling the DMA.
+ */
+ qemu_irq_lower(s->irq);
+}
+
+/*
+ * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
+ * can start even if the result of the previous was not collected.
+ */
+static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
+{
+ return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
+ !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
+}
+
+static void aspeed_smc_dma_done(AspeedSMCState *s)
+{
+ s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
+ if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
+ qemu_irq_raise(s->irq);
+ }
+}
+
+static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
+{
+ if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
+ s->regs[R_DMA_CTRL] = dma_ctrl;
+
+ aspeed_smc_dma_stop(s);
+ return;
+ }
+
+ if (aspeed_smc_dma_in_progress(s)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA in progress\n", __func__);
+ return;
+ }
+
+ s->regs[R_DMA_CTRL] = dma_ctrl;
+
+ if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
+ aspeed_smc_dma_checksum(s);
+ } else {
+ aspeed_smc_dma_rw(s);
+ }
+
+ aspeed_smc_dma_done(s);
+}
+
static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
unsigned int size)
{
@@ -810,6 +1077,16 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
}
} else if (addr == R_DUMMY_DATA) {
s->regs[addr] = value & 0xff;
+ } else if (addr == R_INTR_CTRL) {
+ s->regs[addr] = value;
+ } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) {
+ aspeed_smc_dma_ctrl(s, value);
+ } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) {
+ s->regs[addr] = DMA_DRAM_ADDR(s, value);
+ } else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) {
+ s->regs[addr] = DMA_FLASH_ADDR(s, value);
+ } else if (s->ctrl->has_dma && addr == R_DMA_LEN) {
+ s->regs[addr] = DMA_LENGTH(value);
} else {
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
__func__, addr);
@@ -824,6 +1101,28 @@ static const MemoryRegionOps aspeed_smc_ops = {
.valid.unaligned = true,
};
+
+/*
+ * Initialize the custom address spaces for DMAs
+ */
+static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
+{
+ char *name;
+
+ if (!s->dram_mr) {
+ error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
+ return;
+ }
+
+ name = g_strdup_printf("%s-dma-flash", s->ctrl->name);
+ address_space_init(&s->flash_as, &s->mmio_flash, name);
+ g_free(name);
+
+ name = g_strdup_printf("%s-dma-dram", s->ctrl->name);
+ address_space_init(&s->dram_as, s->dram_mr, name);
+ g_free(name);
+}
+
static void aspeed_smc_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
@@ -849,10 +1148,12 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
s->num_cs = s->ctrl->max_slaves;
}
+ /* DMA irq. Keep it first for the initialization in the SoC */
+ sysbus_init_irq(sbd, &s->irq);
+
s->spi = ssi_create_bus(dev, "spi");
/* Setup cs_lines for slaves */
- sysbus_init_irq(sbd, &s->irq);
s->cs_lines = g_new0(qemu_irq, s->num_cs);
ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
@@ -899,6 +1200,11 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
offset += fl->size;
}
+
+ /* DMA support */
+ if (s->ctrl->has_dma) {
+ aspeed_smc_dma_setup(s, errp);
+ }
}
static const VMStateDescription vmstate_aspeed_smc = {
@@ -915,7 +1221,10 @@ static const VMStateDescription vmstate_aspeed_smc = {
static Property aspeed_smc_properties[] = {
DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
+ DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
+ DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
+ TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 59c2bbeee6..2bda826882 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -93,7 +93,8 @@ static inline uint32_t calculate_rate(struct AspeedTimer *t)
{
AspeedTimerCtrlState *s = timer_to_ctrl(t);
- return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : s->scu->apb_freq;
+ return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ :
+ aspeed_scu_get_apb_freq(s->scu);
}
static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns)
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-12 10:24:37 +0000