aboutsummaryrefslogtreecommitdiff
path: root/hw
diff options
context:
space:
mode:
Diffstat (limited to 'hw')
-rw-r--r--hw/core/machine.c2
-rw-r--r--hw/ide/ahci.c10
-rw-r--r--hw/nvme/ctrl.c6
-rw-r--r--hw/nvram/meson.build6
-rw-r--r--hw/pci-host/pnv_phb4.c299
-rw-r--r--hw/pci-host/pnv_phb4_pec.c121
-rw-r--r--hw/rdma/rdma_utils.c14
-rw-r--r--hw/rdma/rdma_utils.h2
-rw-r--r--hw/rdma/trace-events2
-rw-r--r--hw/scsi/megasas.c102
-rw-r--r--hw/scsi/scsi-bus.c12
-rw-r--r--hw/scsi/scsi-disk.c4
-rw-r--r--hw/timer/etraxfs_timer.c34
13 files changed, 307 insertions, 307 deletions
diff --git a/hw/core/machine.c b/hw/core/machine.c
index debcdc0e70..d856485cb4 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1091,7 +1091,7 @@ MemoryRegion *machine_consume_memdev(MachineState *machine,
{
MemoryRegion *ret = host_memory_backend_get_memory(backend);
- if (memory_region_is_mapped(ret)) {
+ if (host_memory_backend_is_mapped(backend)) {
error_report("memory backend %s can't be used multiple times.",
object_get_canonical_path_component(OBJECT(backend)));
exit(EXIT_FAILURE);
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 205dfdc662..7ce001cacd 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1159,7 +1159,7 @@ static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis,
ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0);
if (ncq_tfs->sglist.size < size) {
- error_report("ahci: PRDT length for NCQ command (0x%zx) "
+ error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") "
"is smaller than the requested size (0x%zx)",
ncq_tfs->sglist.size, size);
ncq_err(ncq_tfs);
@@ -1384,9 +1384,9 @@ static void ahci_pio_transfer(const IDEDMA *dma)
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
if (is_write) {
- dma_buf_write(s->data_ptr, size, &s->sg, attrs);
+ dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs);
} else {
- dma_buf_read(s->data_ptr, size, &s->sg, attrs);
+ dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs);
}
}
@@ -1479,9 +1479,9 @@ static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write)
}
if (is_write) {
- dma_buf_read(p, l, &s->sg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
} else {
- dma_buf_write(p, l, &s->sg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
}
/* free sglist, update byte count */
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 462f79a1f6..1f62116af9 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -1147,12 +1147,12 @@ static uint16_t nvme_tx(NvmeCtrl *n, NvmeSg *sg, uint8_t *ptr, uint32_t len,
if (sg->flags & NVME_SG_DMA) {
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- uint64_t residual;
+ dma_addr_t residual;
if (dir == NVME_TX_DIRECTION_TO_DEVICE) {
- residual = dma_buf_write(ptr, len, &sg->qsg, attrs);
+ dma_buf_write(ptr, len, &residual, &sg->qsg, attrs);
} else {
- residual = dma_buf_read(ptr, len, &sg->qsg, attrs);
+ dma_buf_read(ptr, len, &residual, &sg->qsg, attrs);
}
if (unlikely(residual)) {
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 202a5466e6..f5ee9f6b88 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -1,5 +1,7 @@
-# QOM interfaces must be available anytime QOM is used.
-qom_ss.add(files('fw_cfg-interface.c'))
+if have_system or have_tools
+ # QOM interfaces must be available anytime QOM is used.
+ qom_ss.add(files('fw_cfg-interface.c'))
+endif
softmmu_ss.add(files('fw_cfg.c'))
softmmu_ss.add(when: 'CONFIG_CHRP_NVRAM', if_true: files('chrp_nvram.c'))
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index a7b638831e..a78add75b0 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -22,7 +22,6 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
-#include "sysemu/sysemu.h"
#include "trace.h"
#define phb_error(phb, fmt, ...) \
@@ -228,16 +227,16 @@ static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index)
/* TODO: Figure out how to implemet/decode AOMASK */
/* Check if it matches an enabled MMIO region in the PEC stack */
- if (memory_region_is_mapped(&phb->stack->mmbar0) &&
- base >= phb->stack->mmio0_base &&
- (base + size) <= (phb->stack->mmio0_base + phb->stack->mmio0_size)) {
- parent = &phb->stack->mmbar0;
- base -= phb->stack->mmio0_base;
- } else if (memory_region_is_mapped(&phb->stack->mmbar1) &&
- base >= phb->stack->mmio1_base &&
- (base + size) <= (phb->stack->mmio1_base + phb->stack->mmio1_size)) {
- parent = &phb->stack->mmbar1;
- base -= phb->stack->mmio1_base;
+ if (memory_region_is_mapped(&phb->mmbar0) &&
+ base >= phb->mmio0_base &&
+ (base + size) <= (phb->mmio0_base + phb->mmio0_size)) {
+ parent = &phb->mmbar0;
+ base -= phb->mmio0_base;
+ } else if (memory_region_is_mapped(&phb->mmbar1) &&
+ base >= phb->mmio1_base &&
+ (base + size) <= (phb->mmio1_base + phb->mmio1_size)) {
+ parent = &phb->mmbar1;
+ base -= phb->mmio1_base;
} else {
phb_error(phb, "PHB MBAR %d out of parent bounds", index);
return;
@@ -673,7 +672,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size)
switch (off) {
case PHB_VERSION:
- return phb->version;
+ return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version;
/* Read-only */
case PHB_PHB4_GEN_CAP:
@@ -861,44 +860,65 @@ const MemoryRegionOps pnv_phb4_xscom_ops = {
static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr,
unsigned size)
{
- PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
+ PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
/* TODO: add list of allowed registers and error out if not */
- return stack->nest_regs[reg];
+ return phb->nest_regs[reg];
}
-static void pnv_phb4_update_regions(PnvPhb4PecStack *stack)
+/*
+ * Return the 'stack_no' of a PHB4. 'stack_no' is the order
+ * the PHB4 occupies in the PEC. This is the reverse of what
+ * pnv_phb4_pec_get_phb_id() does.
+ *
+ * E.g. a phb with phb_id = 4 and pec->index = 1 (PEC1) will
+ * be the second phb (stack_no = 1) of the PEC.
+ */
+static int pnv_phb4_get_phb_stack_no(PnvPHB4 *phb)
{
- PnvPHB4 *phb = stack->phb;
+ PnvPhb4PecState *pec = phb->pec;
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
+ int index = pec->index;
+ int stack_no = phb->phb_id;
+
+ while (index--) {
+ stack_no -= pecc->num_phbs[index];
+ }
+
+ return stack_no;
+}
+static void pnv_phb4_update_regions(PnvPHB4 *phb)
+{
/* Unmap first always */
if (memory_region_is_mapped(&phb->mr_regs)) {
- memory_region_del_subregion(&stack->phbbar, &phb->mr_regs);
+ memory_region_del_subregion(&phb->phbbar, &phb->mr_regs);
}
if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) {
- memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio);
+ memory_region_del_subregion(&phb->intbar, &phb->xsrc.esb_mmio);
}
/* Map registers if enabled */
- if (memory_region_is_mapped(&stack->phbbar)) {
- memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs);
+ if (memory_region_is_mapped(&phb->phbbar)) {
+ memory_region_add_subregion(&phb->phbbar, 0, &phb->mr_regs);
}
/* Map ESB if enabled */
- if (memory_region_is_mapped(&stack->intbar)) {
- memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio);
+ if (memory_region_is_mapped(&phb->intbar)) {
+ memory_region_add_subregion(&phb->intbar, 0, &phb->xsrc.esb_mmio);
}
/* Check/update m32 */
pnv_phb4_check_all_mbt(phb);
}
-static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack)
+static void pnv_pec_phb_update_map(PnvPHB4 *phb)
{
- PnvPhb4PecState *pec = stack->pec;
+ PnvPhb4PecState *pec = phb->pec;
MemoryRegion *sysmem = get_system_memory();
- uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN];
+ uint64_t bar_en = phb->nest_regs[PEC_NEST_STK_BAR_EN];
+ int stack_no = pnv_phb4_get_phb_stack_no(phb);
uint64_t bar, mask, size;
char name[64];
@@ -911,106 +931,106 @@ static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack)
*/
/* Handle unmaps */
- if (memory_region_is_mapped(&stack->mmbar0) &&
+ if (memory_region_is_mapped(&phb->mmbar0) &&
!(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
- memory_region_del_subregion(sysmem, &stack->mmbar0);
+ memory_region_del_subregion(sysmem, &phb->mmbar0);
}
- if (memory_region_is_mapped(&stack->mmbar1) &&
+ if (memory_region_is_mapped(&phb->mmbar1) &&
!(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
- memory_region_del_subregion(sysmem, &stack->mmbar1);
+ memory_region_del_subregion(sysmem, &phb->mmbar1);
}
- if (memory_region_is_mapped(&stack->phbbar) &&
+ if (memory_region_is_mapped(&phb->phbbar) &&
!(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
- memory_region_del_subregion(sysmem, &stack->phbbar);
+ memory_region_del_subregion(sysmem, &phb->phbbar);
}
- if (memory_region_is_mapped(&stack->intbar) &&
+ if (memory_region_is_mapped(&phb->intbar) &&
!(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
- memory_region_del_subregion(sysmem, &stack->intbar);
+ memory_region_del_subregion(sysmem, &phb->intbar);
}
/* Update PHB */
- pnv_phb4_update_regions(stack);
+ pnv_phb4_update_regions(phb);
/* Handle maps */
- if (!memory_region_is_mapped(&stack->mmbar0) &&
+ if (!memory_region_is_mapped(&phb->mmbar0) &&
(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
- bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8;
- mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK];
+ bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8;
+ mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK];
size = ((~mask) >> 8) + 1;
- snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0",
- pec->chip_id, pec->index, stack->stack_no);
- memory_region_init(&stack->mmbar0, OBJECT(stack), name, size);
- memory_region_add_subregion(sysmem, bar, &stack->mmbar0);
- stack->mmio0_base = bar;
- stack->mmio0_size = size;
- }
- if (!memory_region_is_mapped(&stack->mmbar1) &&
+ snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio0",
+ pec->chip_id, pec->index, stack_no);
+ memory_region_init(&phb->mmbar0, OBJECT(phb), name, size);
+ memory_region_add_subregion(sysmem, bar, &phb->mmbar0);
+ phb->mmio0_base = bar;
+ phb->mmio0_size = size;
+ }
+ if (!memory_region_is_mapped(&phb->mmbar1) &&
(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
- bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8;
- mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK];
+ bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8;
+ mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK];
size = ((~mask) >> 8) + 1;
- snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1",
- pec->chip_id, pec->index, stack->stack_no);
- memory_region_init(&stack->mmbar1, OBJECT(stack), name, size);
- memory_region_add_subregion(sysmem, bar, &stack->mmbar1);
- stack->mmio1_base = bar;
- stack->mmio1_size = size;
- }
- if (!memory_region_is_mapped(&stack->phbbar) &&
+ snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio1",
+ pec->chip_id, pec->index, stack_no);
+ memory_region_init(&phb->mmbar1, OBJECT(phb), name, size);
+ memory_region_add_subregion(sysmem, bar, &phb->mmbar1);
+ phb->mmio1_base = bar;
+ phb->mmio1_size = size;
+ }
+ if (!memory_region_is_mapped(&phb->phbbar) &&
(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
- bar = stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8;
+ bar = phb->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8;
size = PNV_PHB4_NUM_REGS << 3;
- snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb",
- pec->chip_id, pec->index, stack->stack_no);
- memory_region_init(&stack->phbbar, OBJECT(stack), name, size);
- memory_region_add_subregion(sysmem, bar, &stack->phbbar);
+ snprintf(name, sizeof(name), "pec-%d.%d-phb-%d",
+ pec->chip_id, pec->index, stack_no);
+ memory_region_init(&phb->phbbar, OBJECT(phb), name, size);
+ memory_region_add_subregion(sysmem, bar, &phb->phbbar);
}
- if (!memory_region_is_mapped(&stack->intbar) &&
+ if (!memory_region_is_mapped(&phb->intbar) &&
(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
- bar = stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8;
+ bar = phb->nest_regs[PEC_NEST_STK_INT_BAR] >> 8;
size = PNV_PHB4_MAX_INTs << 16;
- snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int",
- stack->pec->chip_id, stack->pec->index, stack->stack_no);
- memory_region_init(&stack->intbar, OBJECT(stack), name, size);
- memory_region_add_subregion(sysmem, bar, &stack->intbar);
+ snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-int",
+ phb->pec->chip_id, phb->pec->index, stack_no);
+ memory_region_init(&phb->intbar, OBJECT(phb), name, size);
+ memory_region_add_subregion(sysmem, bar, &phb->intbar);
}
/* Update PHB */
- pnv_phb4_update_regions(stack);
+ pnv_phb4_update_regions(phb);
}
static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
- PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
- PnvPhb4PecState *pec = stack->pec;
+ PnvPHB4 *phb = PNV_PHB4(opaque);
+ PnvPhb4PecState *pec = phb->pec;
uint32_t reg = addr >> 3;
switch (reg) {
case PEC_NEST_STK_PCI_NEST_FIR:
- stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
+ phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_CLR:
- stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
+ phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_SET:
- stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
+ phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSK:
- stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
+ phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
- stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
+ phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSKS:
- stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val;
+ phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
- stack->nest_regs[reg] = val;
+ phb->nest_regs[reg] = val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_WOF:
- stack->nest_regs[reg] = 0;
+ phb->nest_regs[reg] = 0;
break;
case PEC_NEST_STK_ERR_REPORT_0:
case PEC_NEST_STK_ERR_REPORT_1:
@@ -1018,39 +1038,39 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
/* Flag error ? */
break;
case PEC_NEST_STK_PBCQ_MODE:
- stack->nest_regs[reg] = val & 0xff00000000000000ull;
+ phb->nest_regs[reg] = val & 0xff00000000000000ull;
break;
case PEC_NEST_STK_MMIO_BAR0:
case PEC_NEST_STK_MMIO_BAR0_MASK:
case PEC_NEST_STK_MMIO_BAR1:
case PEC_NEST_STK_MMIO_BAR1_MASK:
- if (stack->nest_regs[PEC_NEST_STK_BAR_EN] &
+ if (phb->nest_regs[PEC_NEST_STK_BAR_EN] &
(PEC_NEST_STK_BAR_EN_MMIO0 |
PEC_NEST_STK_BAR_EN_MMIO1)) {
phb_pec_error(pec, "Changing enabled BAR unsupported\n");
}
- stack->nest_regs[reg] = val & 0xffffffffff000000ull;
+ phb->nest_regs[reg] = val & 0xffffffffff000000ull;
break;
case PEC_NEST_STK_PHB_REGS_BAR:
- if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
+ if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
phb_pec_error(pec, "Changing enabled BAR unsupported\n");
}
- stack->nest_regs[reg] = val & 0xffffffffffc00000ull;
+ phb->nest_regs[reg] = val & 0xffffffffffc00000ull;
break;
case PEC_NEST_STK_INT_BAR:
- if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
+ if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
phb_pec_error(pec, "Changing enabled BAR unsupported\n");
}
- stack->nest_regs[reg] = val & 0xfffffff000000000ull;
+ phb->nest_regs[reg] = val & 0xfffffff000000000ull;
break;
case PEC_NEST_STK_BAR_EN:
- stack->nest_regs[reg] = val & 0xf000000000000000ull;
- pnv_pec_stk_update_map(stack);
+ phb->nest_regs[reg] = val & 0xf000000000000000ull;
+ pnv_pec_phb_update_map(phb);
break;
case PEC_NEST_STK_DATA_FRZ_TYPE:
case PEC_NEST_STK_PBCQ_TUN_BAR:
/* Not used for now */
- stack->nest_regs[reg] = val;
+ phb->nest_regs[reg] = val;
break;
default:
qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
@@ -1071,54 +1091,54 @@ static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = {
static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr,
unsigned size)
{
- PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
+ PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
/* TODO: add list of allowed registers and error out if not */
- return stack->pci_regs[reg];
+ return phb->pci_regs[reg];
}
static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
- PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
+ PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
switch (reg) {
case PEC_PCI_STK_PCI_FIR:
- stack->pci_regs[reg] = val;
+ phb->pci_regs[reg] = val;
break;
case PEC_PCI_STK_PCI_FIR_CLR:
- stack->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
+ phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
break;
case PEC_PCI_STK_PCI_FIR_SET:
- stack->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
+ phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
break;
case PEC_PCI_STK_PCI_FIR_MSK:
- stack->pci_regs[reg] = val;
+ phb->pci_regs[reg] = val;
break;
case PEC_PCI_STK_PCI_FIR_MSKC:
- stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
+ phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
break;
case PEC_PCI_STK_PCI_FIR_MSKS:
- stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
+ phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
break;
case PEC_PCI_STK_PCI_FIR_ACT0:
case PEC_PCI_STK_PCI_FIR_ACT1:
- stack->pci_regs[reg] = val;
+ phb->pci_regs[reg] = val;
break;
case PEC_PCI_STK_PCI_FIR_WOF:
- stack->pci_regs[reg] = 0;
+ phb->pci_regs[reg] = 0;
break;
case PEC_PCI_STK_ETU_RESET:
- stack->pci_regs[reg] = val & 0x8000000000000000ull;
+ phb->pci_regs[reg] = val & 0x8000000000000000ull;
/* TODO: Implement reset */
break;
case PEC_PCI_STK_PBAIB_ERR_REPORT:
break;
case PEC_PCI_STK_PBAIB_TX_CMD_CRED:
case PEC_PCI_STK_PBAIB_TX_DAT_CRED:
- stack->pci_regs[reg] = val;
+ phb->pci_regs[reg] = val;
break;
default:
qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx
@@ -1362,7 +1382,7 @@ int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index)
int offset = 0;
while (index--) {
- offset += pecc->num_stacks[index];
+ offset += pecc->num_phbs[index];
}
return offset + stack_index;
@@ -1459,9 +1479,9 @@ static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn)
static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
{
- PnvPhb4PecStack *stack = phb->stack;
- PnvPhb4PecState *pec = stack->pec;
+ PnvPhb4PecState *pec = phb->pec;
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
+ int stack_no = pnv_phb4_get_phb_stack_no(phb);
uint32_t pec_nest_base;
uint32_t pec_pci_base;
char name[64];
@@ -1469,22 +1489,22 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
assert(pec);
/* Initialize the XSCOM regions for the stack registers */
- snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d",
- pec->chip_id, pec->index, stack->stack_no);
- pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack),
- &pnv_pec_stk_nest_xscom_ops, stack, name,
+ snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-phb-%d",
+ pec->chip_id, pec->index, stack_no);
+ pnv_xscom_region_init(&phb->nest_regs_mr, OBJECT(phb),
+ &pnv_pec_stk_nest_xscom_ops, phb, name,
PHB4_PEC_NEST_STK_REGS_COUNT);
- snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d",
- pec->chip_id, pec->index, stack->stack_no);
- pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack),
- &pnv_pec_stk_pci_xscom_ops, stack, name,
+ snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
+ pec->chip_id, pec->index, stack_no);
+ pnv_xscom_region_init(&phb->pci_regs_mr, OBJECT(phb),
+ &pnv_pec_stk_pci_xscom_ops, phb, name,
PHB4_PEC_PCI_STK_REGS_COUNT);
/* PHB pass-through */
- snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb",
- pec->chip_id, pec->index, stack->stack_no);
- pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(phb),
+ snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
+ pec->chip_id, pec->index, stack_no);
+ pnv_xscom_region_init(&phb->phb_regs_mr, OBJECT(phb),
&pnv_phb4_xscom_ops, phb, name, 0x40);
pec_nest_base = pecc->xscom_nest_base(pec);
@@ -1492,15 +1512,15 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
/* Populate the XSCOM address space. */
pnv_xscom_add_subregion(pec->chip,
- pec_nest_base + 0x40 * (stack->stack_no + 1),
- &stack->nest_regs_mr);
+ pec_nest_base + 0x40 * (stack_no + 1),
+ &phb->nest_regs_mr);
pnv_xscom_add_subregion(pec->chip,
- pec_pci_base + 0x40 * (stack->stack_no + 1),
- &stack->pci_regs_mr);
+ pec_pci_base + 0x40 * (stack_no + 1),
+ &phb->pci_regs_mr);
pnv_xscom_add_subregion(pec->chip,
pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
- 0x40 * stack->stack_no,
- &stack->phb_regs_mr);
+ 0x40 * stack_no,
+ &phb->phb_regs_mr);
}
static void pnv_phb4_instance_init(Object *obj)
@@ -1513,8 +1533,8 @@ static void pnv_phb4_instance_init(Object *obj)
object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
}
-static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb,
- Error **errp)
+static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
+ Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
int chip_id = phb->chip_id;
@@ -1523,14 +1543,14 @@ static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb,
for (i = 0; i < chip->num_pecs; i++) {
/*
- * For each PEC, check the amount of stacks it supports
- * and see if the given phb4 index matches a stack.
+ * For each PEC, check the amount of phbs it supports
+ * and see if the given phb4 index matches an index.
*/
PnvPhb4PecState *pec = &chip9->pecs[i];
- for (j = 0; j < pec->num_stacks; j++) {
+ for (j = 0; j < pec->num_phbs; j++) {
if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
- return &pec->stacks[j];
+ return pec;
}
}
}
@@ -1552,10 +1572,9 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
char name[32];
/* User created PHB */
- if (!phb->stack) {
+ if (!phb->pec) {
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
- PnvPhb4PecClass *pecc;
BusState *s;
if (!chip) {
@@ -1563,23 +1582,12 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
return;
}
- phb->stack = pnv_phb4_get_stack(chip, phb, &local_err);
+ phb->pec = pnv_phb4_get_pec(chip, phb, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- /* All other phb properties but 'version' are already set */
- pecc = PNV_PHB4_PEC_GET_CLASS(phb->stack->pec);
- object_property_set_int(OBJECT(phb), "version", pecc->version,
- &error_fatal);
-
- /*
- * Assign stack->phb since pnv_phb4_update_regions() uses it
- * to access the phb.
- */
- phb->stack->phb = phb;
-
/*
* Reparent user created devices to the chip to build
* correctly the device tree.
@@ -1624,12 +1632,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
- /* Add a single Root port if running with defaults */
- if (defaults_enabled()) {
- pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb),
- TYPE_PNV_PHB4_ROOT_PORT);
- }
-
/* Setup XIVE Source */
if (phb->big_phb) {
nr_irqs = PNV_PHB4_MAX_INTs;
@@ -1680,9 +1682,8 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno)
static Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
- DEFINE_PROP_UINT64("version", PnvPHB4, version, 0),
- DEFINE_PROP_LINK("stack", PnvPHB4, stack, TYPE_PNV_PHB4_PEC_STACK,
- PnvPhb4PecStack *),
+ DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
+ PnvPhb4PecState *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 7fe7f1f007..40d89fda56 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -112,15 +112,28 @@ static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_pec_instance_init(Object *obj)
+static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
+ int stack_no,
+ Error **errp)
{
- PnvPhb4PecState *pec = PNV_PHB4_PEC(obj);
- int i;
+ PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4));
+ int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
+
+ object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
+ &error_abort);
+ object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id,
+ &error_fatal);
+ object_property_set_int(OBJECT(phb), "index", phb_id,
+ &error_fatal);
- for (i = 0; i < PHB4_PEC_MAX_STACKS; i++) {
- object_initialize_child(obj, "stack[*]", &pec->stacks[i],
- TYPE_PNV_PHB4_PEC_STACK);
+ if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
+ return;
}
+
+ /* Add a single Root port if running with defaults */
+ pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb),
+ PNV_PHB4_PEC_GET_CLASS(pec)->rp_model);
+
}
static void pnv_pec_realize(DeviceState *dev, Error **errp)
@@ -135,22 +148,14 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
return;
}
- pec->num_stacks = pecc->num_stacks[pec->index];
-
- /* Create stacks */
- for (i = 0; i < pec->num_stacks; i++) {
- PnvPhb4PecStack *stack = &pec->stacks[i];
- Object *stk_obj = OBJECT(stack);
+ pec->num_phbs = pecc->num_phbs[pec->index];
- object_property_set_int(stk_obj, "stack-no", i, &error_abort);
- object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort);
- if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) {
- return;
+ /* Create PHBs if running with defaults */
+ if (defaults_enabled()) {
+ for (i = 0; i < pec->num_phbs; i++) {
+ pnv_pec_default_phb_realize(pec, i, errp);
}
}
- for (; i < PHB4_PEC_MAX_STACKS; i++) {
- object_unparent(OBJECT(&pec->stacks[i]));
- }
/* Initialize the XSCOM regions for the PEC registers */
snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
@@ -195,7 +200,7 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
_FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
pecc->compat_size)));
- for (i = 0; i < pec->num_stacks; i++) {
+ for (i = 0; i < pec->num_phbs; i++) {
int phb_id = pnv_phb4_pec_get_phb_id(pec, i);
int stk_offset;
@@ -231,11 +236,11 @@ static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
}
/*
- * PEC0 -> 1 stack
- * PEC1 -> 2 stacks
- * PEC2 -> 3 stacks
+ * PEC0 -> 1 phb
+ * PEC1 -> 2 phb
+ * PEC2 -> 3 phbs
*/
-static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 };
+static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 };
static void pnv_pec_class_init(ObjectClass *klass, void *data)
{
@@ -260,14 +265,14 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
pecc->stk_compat = stk_compat;
pecc->stk_compat_size = sizeof(stk_compat);
pecc->version = PNV_PHB4_VERSION;
- pecc->num_stacks = pnv_pec_num_stacks;
+ pecc->num_phbs = pnv_pec_num_phbs;
+ pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
}
static const TypeInfo pnv_pec_type_info = {
.name = TYPE_PNV_PHB4_PEC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(PnvPhb4PecState),
- .instance_init = pnv_pec_instance_init,
.class_init = pnv_pec_class_init,
.class_size = sizeof(PnvPhb4PecClass),
.interfaces = (InterfaceInfo[]) {
@@ -276,73 +281,9 @@ static const TypeInfo pnv_pec_type_info = {
}
};
-static void pnv_pec_stk_default_phb_realize(PnvPhb4PecStack *stack,
- Error **errp)
-{
- PnvPhb4PecState *pec = stack->pec;
- PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
- int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no);
-
- stack->phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4));
-
- object_property_set_int(OBJECT(stack->phb), "chip-id", pec->chip_id,
- &error_fatal);
- object_property_set_int(OBJECT(stack->phb), "index", phb_id,
- &error_fatal);
- object_property_set_int(OBJECT(stack->phb), "version", pecc->version,
- &error_fatal);
- object_property_set_link(OBJECT(stack->phb), "stack", OBJECT(stack),
- &error_abort);
-
- if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) {
- return;
- }
-}
-
-static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
-{
- PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev);
-
- if (!defaults_enabled()) {
- return;
- }
-
- pnv_pec_stk_default_phb_realize(stack, errp);
-}
-
-static Property pnv_pec_stk_properties[] = {
- DEFINE_PROP_UINT32("stack-no", PnvPhb4PecStack, stack_no, 0),
- DEFINE_PROP_LINK("pec", PnvPhb4PecStack, pec, TYPE_PNV_PHB4_PEC,
- PnvPhb4PecState *),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void pnv_pec_stk_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- device_class_set_props(dc, pnv_pec_stk_properties);
- dc->realize = pnv_pec_stk_realize;
- dc->user_creatable = false;
-
- /* TODO: reset regs ? */
-}
-
-static const TypeInfo pnv_pec_stk_type_info = {
- .name = TYPE_PNV_PHB4_PEC_STACK,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(PnvPhb4PecStack),
- .class_init = pnv_pec_stk_class_init,
- .interfaces = (InterfaceInfo[]) {
- { TYPE_PNV_XSCOM_INTERFACE },
- { }
- }
-};
-
static void pnv_pec_register_types(void)
{
type_register_static(&pnv_pec_type_info);
- type_register_static(&pnv_pec_stk_type_info);
}
type_init(pnv_pec_register_types);
diff --git a/hw/rdma/rdma_utils.c b/hw/rdma/rdma_utils.c
index 98df58f689..5a7ef63ad2 100644
--- a/hw/rdma/rdma_utils.c
+++ b/hw/rdma/rdma_utils.c
@@ -17,29 +17,29 @@
#include "trace.h"
#include "rdma_utils.h"
-void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t plen)
+void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t len)
{
void *p;
- hwaddr len = plen;
+ dma_addr_t pci_len = len;
if (!addr) {
rdma_error_report("addr is NULL");
return NULL;
}
- p = pci_dma_map(dev, addr, &len, DMA_DIRECTION_TO_DEVICE);
+ p = pci_dma_map(dev, addr, &pci_len, DMA_DIRECTION_TO_DEVICE);
if (!p) {
rdma_error_report("pci_dma_map fail, addr=0x%"PRIx64", len=%"PRId64,
- addr, len);
+ addr, pci_len);
return NULL;
}
- if (len != plen) {
- rdma_pci_dma_unmap(dev, p, len);
+ if (pci_len != len) {
+ rdma_pci_dma_unmap(dev, p, pci_len);
return NULL;
}
- trace_rdma_pci_dma_map(addr, p, len);
+ trace_rdma_pci_dma_map(addr, p, pci_len);
return p;
}
diff --git a/hw/rdma/rdma_utils.h b/hw/rdma/rdma_utils.h
index 9fd0efd940..0c6414e7e0 100644
--- a/hw/rdma/rdma_utils.h
+++ b/hw/rdma/rdma_utils.h
@@ -38,7 +38,7 @@ typedef struct RdmaProtectedGSList {
GSList *list;
} RdmaProtectedGSList;
-void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t plen);
+void *rdma_pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t len);
void rdma_pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len);
void rdma_protected_gqueue_init(RdmaProtectedGQueue *list);
void rdma_protected_gqueue_destroy(RdmaProtectedGQueue *list);
diff --git a/hw/rdma/trace-events b/hw/rdma/trace-events
index 9accb14973..c23175120e 100644
--- a/hw/rdma/trace-events
+++ b/hw/rdma/trace-events
@@ -27,5 +27,5 @@ rdma_rm_alloc_qp(uint32_t rm_qpn, uint32_t backend_qpn, uint8_t qp_type) "rm_qpn
rdma_rm_modify_qp(uint32_t qpn, uint32_t attr_mask, int qp_state, uint8_t sgid_idx) "qpn=0x%x, attr_mask=0x%x, qp_state=%d, sgid_idx=%d"
# rdma_utils.c
-rdma_pci_dma_map(uint64_t addr, void *vaddr, uint64_t len) "0x%"PRIx64" -> %p (len=%" PRId64")"
+rdma_pci_dma_map(uint64_t addr, void *vaddr, uint64_t len) "0x%"PRIx64" -> %p (len=%" PRIu64")"
rdma_pci_dma_unmap(void *vaddr) "%p"
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index dc9bbdb740..c9da5ce0b5 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -383,8 +383,7 @@ static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
cdb[1] = 0x1;
cdb[2] = pg;
}
- cdb[3] = (len >> 8) & 0xff;
- cdb[4] = (len & 0xff);
+ stw_be_p(&cdb[3], len);
return len;
}
@@ -400,18 +399,8 @@ static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
} else {
cdb[0] = READ_16;
}
- cdb[2] = (lba >> 56) & 0xff;
- cdb[3] = (lba >> 48) & 0xff;
- cdb[4] = (lba >> 40) & 0xff;
- cdb[5] = (lba >> 32) & 0xff;
- cdb[6] = (lba >> 24) & 0xff;
- cdb[7] = (lba >> 16) & 0xff;
- cdb[8] = (lba >> 8) & 0xff;
- cdb[9] = (lba) & 0xff;
- cdb[10] = (len >> 24) & 0xff;
- cdb[11] = (len >> 16) & 0xff;
- cdb[12] = (len >> 8) & 0xff;
- cdb[13] = (len) & 0xff;
+ stq_be_p(&cdb[2], lba);
+ stl_be_p(&cdb[2 + 8], len);
}
/*
@@ -750,6 +739,7 @@ static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
size_t dcmd_size = sizeof(info);
BusChild *kid;
int num_pd_disks = 0;
+ dma_addr_t residual;
memset(&info, 0x0, dcmd_size);
if (cmd->iov_size < dcmd_size) {
@@ -860,7 +850,9 @@ static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
MFI_INFO_PDMIX_SATA |
MFI_INFO_PDMIX_LD);
- cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -868,6 +860,7 @@ static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
{
struct mfi_defaults info;
size_t dcmd_size = sizeof(struct mfi_defaults);
+ dma_addr_t residual;
memset(&info, 0x0, dcmd_size);
if (cmd->iov_size < dcmd_size) {
@@ -890,7 +883,9 @@ static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
info.disable_preboot_cli = 1;
info.cluster_disable = 1;
- cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -898,6 +893,7 @@ static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
{
struct mfi_bios_data info;
size_t dcmd_size = sizeof(info);
+ dma_addr_t residual;
memset(&info, 0x0, dcmd_size);
if (cmd->iov_size < dcmd_size) {
@@ -911,7 +907,9 @@ static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
info.expose_all_drives = 1;
}
- cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -919,10 +917,13 @@ static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
{
uint64_t fw_time;
size_t dcmd_size = sizeof(fw_time);
+ dma_addr_t residual;
fw_time = cpu_to_le64(megasas_fw_time());
- cmd->iov_size -= dma_buf_read(&fw_time, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(&fw_time, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -942,6 +943,7 @@ static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
{
struct mfi_evt_log_state info;
size_t dcmd_size = sizeof(info);
+ dma_addr_t residual;
memset(&info, 0, dcmd_size);
@@ -949,7 +951,9 @@ static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
info.boot_seq_num = cpu_to_le32(s->boot_event);
- cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -979,6 +983,7 @@ static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
size_t dcmd_size = sizeof(info);
BusChild *kid;
uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
+ dma_addr_t residual;
memset(&info, 0, dcmd_size);
offset = 8;
@@ -1018,7 +1023,9 @@ static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
info.size = cpu_to_le32(offset);
info.count = cpu_to_le32(num_pd_disks);
- cmd->iov_size -= dma_buf_read(&info, offset, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(&info, offset, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -1045,7 +1052,8 @@ static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
uint64_t pd_size;
uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
uint8_t cmdbuf[6];
- size_t len, resid;
+ size_t len;
+ dma_addr_t residual;
if (!cmd->iov_buf) {
cmd->iov_buf = g_malloc0(dcmd_size);
@@ -1112,9 +1120,11 @@ static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
info->connected_port_bitmap = 0x1;
info->device_speed = 1;
info->link_speed = 1;
- resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
g_free(cmd->iov_buf);
- cmd->iov_size = dcmd_size - resid;
+ cmd->iov_size = dcmd_size - residual;
cmd->iov_buf = NULL;
return MFI_STAT_OK;
}
@@ -1149,7 +1159,8 @@ static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
{
struct mfi_ld_list info;
- size_t dcmd_size = sizeof(info), resid;
+ size_t dcmd_size = sizeof(info);
+ dma_addr_t residual;
uint32_t num_ld_disks = 0, max_ld_disks;
uint64_t ld_size;
BusChild *kid;
@@ -1184,8 +1195,9 @@ static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
info.ld_count = cpu_to_le32(num_ld_disks);
trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
- resid = dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
- cmd->iov_size = dcmd_size - resid;
+ dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size = dcmd_size - residual;
return MFI_STAT_OK;
}
@@ -1193,7 +1205,8 @@ static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
{
uint16_t flags;
struct mfi_ld_targetid_list info;
- size_t dcmd_size = sizeof(info), resid;
+ size_t dcmd_size = sizeof(info);
+ dma_addr_t residual;
uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
BusChild *kid;
@@ -1233,8 +1246,9 @@ static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
info.size = dcmd_size;
trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
- resid = dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
- cmd->iov_size = dcmd_size - resid;
+ dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size = dcmd_size - residual;
return MFI_STAT_OK;
}
@@ -1244,7 +1258,8 @@ static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
struct mfi_ld_info *info = cmd->iov_buf;
size_t dcmd_size = sizeof(struct mfi_ld_info);
uint8_t cdb[6];
- ssize_t len, resid;
+ ssize_t len;
+ dma_addr_t residual;
uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
uint64_t ld_size;
@@ -1283,9 +1298,10 @@ static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
info->ld_config.span[0].num_blocks = info->size;
info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
- resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
g_free(cmd->iov_buf);
- cmd->iov_size = dcmd_size - resid;
+ cmd->iov_size = dcmd_size - residual;
cmd->iov_buf = NULL;
return MFI_STAT_OK;
}
@@ -1328,6 +1344,7 @@ static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
struct mfi_config_data *info;
int num_pd_disks = 0, array_offset, ld_offset;
BusChild *kid;
+ dma_addr_t residual;
if (cmd->iov_size > 4096) {
return MFI_STAT_INVALID_PARAMETER;
@@ -1402,7 +1419,9 @@ static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
ld_offset += sizeof(struct mfi_ld_config);
}
- cmd->iov_size -= dma_buf_read(data, info->size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(data, info->size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -1410,6 +1429,7 @@ static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
{
struct mfi_ctrl_props info;
size_t dcmd_size = sizeof(info);
+ dma_addr_t residual;
memset(&info, 0x0, dcmd_size);
if (cmd->iov_size < dcmd_size) {
@@ -1432,7 +1452,9 @@ static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
info.ecc_bucket_leak_rate = cpu_to_le16(1440);
info.expose_encl_devices = 1;
- cmd->iov_size -= dma_buf_read(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
+ MEMTXATTRS_UNSPECIFIED);
+ cmd->iov_size -= residual;
return MFI_STAT_OK;
}
@@ -1477,7 +1499,7 @@ static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
dcmd_size);
return MFI_STAT_INVALID_PARAMETER;
}
- dma_buf_write(&info, dcmd_size, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_write(&info, dcmd_size, NULL, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
return MFI_STAT_OK;
}
@@ -1617,13 +1639,13 @@ static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
}
static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
- SCSIRequest *req, size_t resid)
+ SCSIRequest *req, dma_addr_t residual)
{
int retval = MFI_STAT_OK;
int lun = req->lun;
trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
- cmd->iov_size -= resid;
+ cmd->iov_size -= residual;
switch (cmd->dcmd_opcode) {
case MFI_DCMD_PD_GET_INFO:
retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
@@ -1865,12 +1887,12 @@ static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
}
}
-static void megasas_command_complete(SCSIRequest *req, size_t resid)
+static void megasas_command_complete(SCSIRequest *req, size_t residual)
{
MegasasCmd *cmd = req->hba_private;
uint8_t cmd_status = MFI_STAT_OK;
- trace_megasas_command_complete(cmd->index, req->status, resid);
+ trace_megasas_command_complete(cmd->index, req->status, residual);
if (req->io_canceled) {
return;
@@ -1880,7 +1902,7 @@ static void megasas_command_complete(SCSIRequest *req, size_t resid)
/*
* Internal command complete
*/
- cmd_status = megasas_finish_internal_dcmd(cmd, req, resid);
+ cmd_status = megasas_finish_internal_dcmd(cmd, req, residual);
if (cmd_status == MFI_STAT_INVALID_STATUS) {
return;
}
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
index 2b5e9dca31..4057e04ce8 100644
--- a/hw/scsi/scsi-bus.c
+++ b/hw/scsi/scsi-bus.c
@@ -760,7 +760,7 @@ SCSIRequest *scsi_req_new(SCSIDevice *d, uint32_t tag, uint32_t lun,
}
req->cmd = cmd;
- req->resid = req->cmd.xfer;
+ req->residual = req->cmd.xfer;
switch (buf[0]) {
case INQUIRY:
@@ -1408,7 +1408,7 @@ void scsi_req_data(SCSIRequest *req, int len)
trace_scsi_req_data(req->dev->id, req->lun, req->tag, len);
assert(req->cmd.mode != SCSI_XFER_NONE);
if (!req->sg) {
- req->resid -= len;
+ req->residual -= len;
req->bus->info->transfer_data(req, len);
return;
}
@@ -1421,9 +1421,11 @@ void scsi_req_data(SCSIRequest *req, int len)
buf = scsi_req_get_buf(req);
if (req->cmd.mode == SCSI_XFER_FROM_DEV) {
- req->resid = dma_buf_read(buf, len, req->sg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_read(buf, len, &req->residual, req->sg,
+ MEMTXATTRS_UNSPECIFIED);
} else {
- req->resid = dma_buf_write(buf, len, req->sg, MEMTXATTRS_UNSPECIFIED);
+ dma_buf_write(buf, len, &req->residual, req->sg,
+ MEMTXATTRS_UNSPECIFIED);
}
scsi_req_continue(req);
}
@@ -1512,7 +1514,7 @@ void scsi_req_complete(SCSIRequest *req, int status)
scsi_req_ref(req);
scsi_req_dequeue(req);
- req->bus->info->complete(req, req->resid);
+ req->bus->info->complete(req, req->residual);
/* Cancelled requests might end up being completed instead of cancelled */
notifier_list_notify(&req->cancel_notifiers, req);
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index d4914178ea..9c0dc7b946 100644
--- a/hw/scsi/scsi-disk.c
+++ b/hw/scsi/scsi-disk.c
@@ -420,7 +420,7 @@ static void scsi_do_read(SCSIDiskReq *r, int ret)
if (r->req.sg) {
dma_acct_start(s->qdev.conf.blk, &r->acct, r->req.sg, BLOCK_ACCT_READ);
- r->req.resid -= r->req.sg->size;
+ r->req.residual -= r->req.sg->size;
r->req.aiocb = dma_blk_io(blk_get_aio_context(s->qdev.conf.blk),
r->req.sg, r->sector << BDRV_SECTOR_BITS,
BDRV_SECTOR_SIZE,
@@ -580,7 +580,7 @@ static void scsi_write_data(SCSIRequest *req)
if (r->req.sg) {
dma_acct_start(s->qdev.conf.blk, &r->acct, r->req.sg, BLOCK_ACCT_WRITE);
- r->req.resid -= r->req.sg->size;
+ r->req.residual -= r->req.sg->size;
r->req.aiocb = dma_blk_io(blk_get_aio_context(s->qdev.conf.blk),
r->req.sg, r->sector << BDRV_SECTOR_BITS,
BDRV_SECTOR_SIZE,
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
index 4ba662190d..139e5b86a4 100644
--- a/hw/timer/etraxfs_timer.c
+++ b/hw/timer/etraxfs_timer.c
@@ -26,6 +26,7 @@
#include "hw/sysbus.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
+#include "migration/vmstate.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "hw/irq.h"
@@ -64,7 +65,7 @@ struct ETRAXTimerState {
ptimer_state *ptimer_t1;
ptimer_state *ptimer_wd;
- int wd_hits;
+ uint32_t wd_hits;
/* Control registers. */
uint32_t rw_tmr0_div;
@@ -83,6 +84,36 @@ struct ETRAXTimerState {
uint32_t r_masked_intr;
};
+static const VMStateDescription vmstate_etraxfs = {
+ .name = "etraxfs",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_PTIMER(ptimer_t0, ETRAXTimerState),
+ VMSTATE_PTIMER(ptimer_t1, ETRAXTimerState),
+ VMSTATE_PTIMER(ptimer_wd, ETRAXTimerState),
+
+ VMSTATE_UINT32(wd_hits, ETRAXTimerState),
+
+ VMSTATE_UINT32(rw_tmr0_div, ETRAXTimerState),
+ VMSTATE_UINT32(r_tmr0_data, ETRAXTimerState),
+ VMSTATE_UINT32(rw_tmr0_ctrl, ETRAXTimerState),
+
+ VMSTATE_UINT32(rw_tmr1_div, ETRAXTimerState),
+ VMSTATE_UINT32(r_tmr1_data, ETRAXTimerState),
+ VMSTATE_UINT32(rw_tmr1_ctrl, ETRAXTimerState),
+
+ VMSTATE_UINT32(rw_wd_ctrl, ETRAXTimerState),
+
+ VMSTATE_UINT32(rw_intr_mask, ETRAXTimerState),
+ VMSTATE_UINT32(rw_ack_intr, ETRAXTimerState),
+ VMSTATE_UINT32(r_intr, ETRAXTimerState),
+ VMSTATE_UINT32(r_masked_intr, ETRAXTimerState),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
@@ -357,6 +388,7 @@ static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = etraxfs_timer_realize;
+ dc->vmsd = &vmstate_etraxfs;
rc->phases.enter = etraxfs_timer_reset_enter;
rc->phases.hold = etraxfs_timer_reset_hold;
}
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-01 04:39:15 +0000