diff options
Diffstat (limited to 'hw')
33 files changed, 773 insertions, 734 deletions
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index d2247fa1b9..31586c652e 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -601,6 +601,11 @@ static const MemoryRegionOps musicpal_lcd_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static const GraphicHwOps musicpal_gfx_ops = { + .invalidate = lcd_invalidate, + .gfx_update = lcd_refresh, +}; + static int musicpal_lcd_init(SysBusDevice *dev) { musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); @@ -611,8 +616,7 @@ static int musicpal_lcd_init(SysBusDevice *dev) "musicpal-lcd", MP_LCD_SIZE); sysbus_init_mmio(dev, &s->iomem); - s->con = graphic_console_init(lcd_refresh, lcd_invalidate, - NULL, NULL, s); + s->con = graphic_console_init(&musicpal_gfx_ops, s); qemu_console_resize(s->con, 128*3, 64*3); qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3); diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 55e9d0d37a..efcc7f4c83 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -26,15 +26,17 @@ #include "hw/ssi.h" #include "hw/devices.h" -#ifdef M25P80_ERR_DEBUG -#define DB_PRINT(...) do { \ - fprintf(stderr, ": %s: ", __func__); \ - fprintf(stderr, ## __VA_ARGS__); \ - } while (0); -#else - #define DB_PRINT(...) +#ifndef M25P80_ERR_DEBUG +#define M25P80_ERR_DEBUG 0 #endif +#define DB_PRINT_L(level, ...) do { \ + if (M25P80_ERR_DEBUG > (level)) { \ + fprintf(stderr, ": %s: ", __func__); \ + fprintf(stderr, ## __VA_ARGS__); \ + } \ +} while (0); + /* Fields for FlashPartInfo->flags */ /* erase capabilities */ @@ -317,13 +319,14 @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd) abort(); } - DB_PRINT("offset = %#x, len = %d\n", offset, len); + DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); if ((s->pi->flags & capa_to_assert) != capa_to_assert) { - hw_error("m25p80: %dk erase size not supported by device\n", len); + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" + " device\n", len); } if (!s->write_enable) { - DB_PRINT("erase with write protect!\n"); + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); return; } memset(s->storage + offset, 0xff, len); @@ -345,12 +348,12 @@ void flash_write8(Flash *s, uint64_t addr, uint8_t data) uint8_t prev = s->storage[s->cur_addr]; if (!s->write_enable) { - DB_PRINT("write with write protect!\n"); + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); } if ((prev ^ data) & data) { - DB_PRINT("programming zero to one! addr=%lx %x -> %x\n", - addr, prev, data); + DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8 + " -> %" PRIx8 "\n", addr, prev, data); } if (s->pi->flags & WR_1) { @@ -403,7 +406,7 @@ static void complete_collecting_data(Flash *s) static void decode_new_cmd(Flash *s, uint32_t value) { s->cmd_in_progress = value; - DB_PRINT("decoded new command:%x\n", value); + DB_PRINT_L(0, "decoded new command:%x\n", value); switch (value) { @@ -483,7 +486,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) break; case JEDEC_READ: - DB_PRINT("populated jedec code\n"); + DB_PRINT_L(0, "populated jedec code\n"); s->data[0] = (s->pi->jedec >> 16) & 0xff; s->data[1] = (s->pi->jedec >> 8) & 0xff; s->data[2] = s->pi->jedec & 0xff; @@ -500,16 +503,17 @@ static void decode_new_cmd(Flash *s, uint32_t value) case BULK_ERASE: if (s->write_enable) { - DB_PRINT("chip erase\n"); + DB_PRINT_L(0, "chip erase\n"); flash_erase(s, 0, BULK_ERASE); } else { - DB_PRINT("chip erase with write protect!\n"); + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " + "protect!\n"); } break; case NOP: break; default: - DB_PRINT("Unknown cmd %x\n", value); + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); break; } } @@ -525,7 +529,7 @@ static int m25p80_cs(SSISlave *ss, bool select) flash_sync_dirty(s, -1); } - DB_PRINT("%sselect\n", select ? "de" : ""); + DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); return 0; } @@ -538,15 +542,16 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) switch (s->state) { case STATE_PAGE_PROGRAM: - DB_PRINT("page program cur_addr=%lx data=%x\n", s->cur_addr, - (uint8_t)tx); + DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n", + s->cur_addr, (uint8_t)tx); flash_write8(s, s->cur_addr, (uint8_t)tx); s->cur_addr++; break; case STATE_READ: r = s->storage[s->cur_addr]; - DB_PRINT("READ 0x%lx=%x\n", s->cur_addr, r); + DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr, + (uint8_t)r); s->cur_addr = (s->cur_addr + 1) % s->size; break; @@ -592,7 +597,7 @@ static int m25p80_init(SSISlave *ss) dinfo = drive_get_next(IF_MTD); if (dinfo && dinfo->bdrv) { - DB_PRINT("Binding to IF_MTD drive\n"); + DB_PRINT_L(0, "Binding to IF_MTD drive\n"); s->bdrv = dinfo->bdrv; /* FIXME: Move to late init */ if (bdrv_read(s->bdrv, 0, s->storage, DIV_ROUND_UP(s->size, @@ -601,6 +606,7 @@ static int m25p80_init(SSISlave *ss) return 1; } } else { + DB_PRINT_L(0, "No BDRV - binding to RAM\n"); memset(s->storage, 0xFF, s->size); } diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index ddde18e6b4..ca1739ec84 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -120,6 +120,39 @@ PropertyInfo qdev_prop_bit = { .set = set_bit, }; +/* --- bool --- */ + +static void get_bool(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + bool *ptr = qdev_get_prop_ptr(dev, prop); + + visit_type_bool(v, ptr, name, errp); +} + +static void set_bool(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + bool *ptr = qdev_get_prop_ptr(dev, prop); + + if (dev->realized) { + qdev_prop_set_after_realize(dev, name, errp); + return; + } + + visit_type_bool(v, ptr, name, errp); +} + +PropertyInfo qdev_prop_bool = { + .name = "boolean", + .get = get_bool, + .set = set_bool, +}; + /* --- 8bit integer --- */ static void get_uint8(Object *obj, Visitor *v, void *opaque, diff --git a/hw/core/qdev.c b/hw/core/qdev.c index bab4ed7bf7..4eb01345df 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -684,10 +684,6 @@ static void device_set_realized(Object *obj, bool value, Error **err) Error *local_err = NULL; if (value && !dev->realized) { - if (dc->realize) { - dc->realize(dev, &local_err); - } - if (!obj->parent && local_err == NULL) { static int unattached_count; gchar *name = g_strdup_printf("device[%d]", unattached_count++); @@ -698,6 +694,10 @@ static void device_set_realized(Object *obj, bool value, Error **err) g_free(name); } + if (dc->realize) { + dc->realize(dev, &local_err); + } + if (qdev_get_vmsd(dev) && local_err == NULL) { vmstate_register_with_alias_id(dev, -1, qdev_get_vmsd(dev), dev, dev->instance_id_alias, diff --git a/hw/core/stream.c b/hw/core/stream.c index a07d6a56d3..e6a05a543e 100644 --- a/hw/core/stream.c +++ b/hw/core/stream.c @@ -1,11 +1,20 @@ #include "hw/stream.h" -void -stream_push(StreamSlave *sink, uint8_t *buf, size_t len, uint32_t *app) +size_t +stream_push(StreamSlave *sink, uint8_t *buf, size_t len) { StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink); - k->push(sink, buf, len, app); + return k->push(sink, buf, len); +} + +bool +stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify, + void *notify_opaque) +{ + StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink); + + return k->can_push ? k->can_push(sink, notify, notify_opaque) : true; } static const TypeInfo stream_slave_info = { diff --git a/hw/display/blizzard.c b/hw/display/blizzard.c index de7ccf87dc..1ca3355e5d 100644 --- a/hw/display/blizzard.c +++ b/hw/display/blizzard.c @@ -933,18 +933,6 @@ static void blizzard_update_display(void *opaque) s->my[1] = 0; } -static void blizzard_screen_dump(void *opaque, const char *filename, - bool cswitch, Error **errp) -{ - BlizzardState *s = (BlizzardState *) opaque; - DisplaySurface *surface = qemu_console_surface(s->con); - - blizzard_update_display(opaque); - if (s && surface_data(surface)) { - ppm_save(filename, surface, errp); - } -} - #define DEPTH 8 #include "blizzard_template.h" #define DEPTH 15 @@ -956,6 +944,11 @@ static void blizzard_screen_dump(void *opaque, const char *filename, #define DEPTH 32 #include "blizzard_template.h" +static const GraphicHwOps blizzard_ops = { + .invalidate = blizzard_invalidate_display, + .gfx_update = blizzard_update_display, +}; + void *s1d13745_init(qemu_irq gpio_int) { BlizzardState *s = (BlizzardState *) g_malloc0(sizeof(*s)); @@ -963,9 +956,7 @@ void *s1d13745_init(qemu_irq gpio_int) s->fb = g_malloc(0x180000); - s->con = graphic_console_init(blizzard_update_display, - blizzard_invalidate_display, - blizzard_screen_dump, NULL, s); + s->con = graphic_console_init(&blizzard_ops, s); surface = qemu_console_surface(s->con); switch (surface_bits_per_pixel(surface)) { diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index bf2181afd8..db232af258 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -720,7 +720,7 @@ static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) /* we have to flush all pending changes so that the copy is generated at the appropriate moment in time */ if (notify) - vga_hw_update(); + graphic_hw_update(s->vga.con); (*s->cirrus_rop) (s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), @@ -2910,9 +2910,7 @@ static int vga_initfn(ISADevice *dev) vga_common_init(s); cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0, isa_address_space(dev), isa_address_space_io(dev)); - s->con = graphic_console_init(s->update, s->invalidate, - s->screen_dump, s->text_update, - s); + s->con = graphic_console_init(s->hw_ops, s); rom_add_vga(VGABIOS_CIRRUS_FILENAME); /* XXX ISA-LFB support */ /* FIXME not qdev yet */ @@ -2959,9 +2957,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev) vga_common_init(&s->vga); cirrus_init_common(s, device_id, 1, pci_address_space(dev), pci_address_space_io(dev)); - s->vga.con = graphic_console_init(s->vga.update, s->vga.invalidate, - s->vga.screen_dump, s->vga.text_update, - &s->vga); + s->vga.con = graphic_console_init(s->vga.hw_ops, &s->vga); /* setup PCI */ diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index 49cca4bf94..e6e7b27d13 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1242,7 +1242,7 @@ static void exynos4210_update_resolution(Exynos4210fimdState *s) static void exynos4210_fimd_update(void *opaque) { Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; - DisplaySurface *surface = qemu_console_surface(s->console); + DisplaySurface *surface; Exynos4210fimdWindow *w; int i, line; hwaddr fb_line_addr, inc_size; @@ -1255,11 +1255,12 @@ static void exynos4210_fimd_update(void *opaque) const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) & FIMD_VIDTCON2_SIZE_MASK) + 1; - if (!s || !s->console || !surface_bits_per_pixel(surface) || - !s->enabled) { + if (!s || !s->console || !s->enabled || + surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { return; } exynos4210_update_resolution(s); + surface = qemu_console_surface(s->console); for (i = 0; i < NUM_OF_WINDOWS; i++) { w = &s->window[i]; @@ -1886,6 +1887,11 @@ static const VMStateDescription exynos4210_fimd_vmstate = { } }; +static const GraphicHwOps exynos4210_fimd_ops = { + .invalidate = exynos4210_fimd_invalidate, + .gfx_update = exynos4210_fimd_update, +}; + static int exynos4210_fimd_init(SysBusDevice *dev) { Exynos4210fimdState *s = FROM_SYSBUS(Exynos4210fimdState, dev); @@ -1899,8 +1905,7 @@ static int exynos4210_fimd_init(SysBusDevice *dev) memory_region_init_io(&s->iomem, &exynos4210_fimd_mmio_ops, s, "exynos4210.fimd", FIMD_REGS_SIZE); sysbus_init_mmio(dev, &s->iomem); - s->console = graphic_console_init(exynos4210_fimd_update, - exynos4210_fimd_invalidate, NULL, NULL, s); + s->console = graphic_console_init(&exynos4210_fimd_ops, s); return 0; } diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index f7014e9dd8..03810e9717 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -294,77 +294,6 @@ static void g364fb_reset(G364State *s) g364fb_invalidate_display(s); } -static void g364fb_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp) -{ - G364State *s = opaque; - int ret, y, x; - uint8_t index; - uint8_t *data_buffer; - FILE *f; - - qemu_flush_coalesced_mmio_buffer(); - - if (s->depth != 8) { - error_setg(errp, "g364: unknown guest depth %d", s->depth); - return; - } - - f = fopen(filename, "wb"); - if (!f) { - error_setg(errp, "failed to open file '%s': %s", filename, - strerror(errno)); - return; - } - - if (s->ctla & CTLA_FORCE_BLANK) { - /* blank screen */ - ret = fprintf(f, "P4\n%d %d\n", s->width, s->height); - if (ret < 0) { - goto write_err; - } - for (y = 0; y < s->height; y++) - for (x = 0; x < s->width; x++) { - ret = fputc(0, f); - if (ret == EOF) { - goto write_err; - } - } - } else { - data_buffer = s->vram + s->top_of_screen; - ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); - if (ret < 0) { - goto write_err; - } - for (y = 0; y < s->height; y++) - for (x = 0; x < s->width; x++, data_buffer++) { - index = *data_buffer; - ret = fputc(s->color_palette[index][0], f); - if (ret == EOF) { - goto write_err; - } - ret = fputc(s->color_palette[index][1], f); - if (ret == EOF) { - goto write_err; - } - ret = fputc(s->color_palette[index][2], f); - if (ret == EOF) { - goto write_err; - } - } - } - -out: - fclose(f); - return; - -write_err: - error_setg(errp, "failed to write to file '%s': %s", filename, - strerror(errno)); - unlink(filename); - goto out; -} - /* called for accesses to io ports */ static uint64_t g364fb_ctrl_read(void *opaque, hwaddr addr, @@ -546,13 +475,16 @@ static const VMStateDescription vmstate_g364fb = { } }; +static const GraphicHwOps g364fb_ops = { + .invalidate = g364fb_invalidate_display, + .gfx_update = g364fb_update_display, +}; + static void g364fb_init(DeviceState *dev, G364State *s) { s->vram = g_malloc0(s->vram_size); - s->con = graphic_console_init(g364fb_update_display, - g364fb_invalidate_display, - g364fb_screen_dump, NULL, s); + s->con = graphic_console_init(&g364fb_ops, s); memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000); memory_region_init_ram_ptr(&s->mem_vram, "vram", diff --git a/hw/display/jazz_led.c b/hw/display/jazz_led.c index 05528c7c81..6306d8c12c 100644 --- a/hw/display/jazz_led.c +++ b/hw/display/jazz_led.c @@ -254,6 +254,12 @@ static const VMStateDescription vmstate_jazz_led = { } }; +static const GraphicHwOps jazz_led_ops = { + .invalidate = jazz_led_invalidate_display, + .gfx_update = jazz_led_update_display, + .text_update = jazz_led_text_update, +}; + static int jazz_led_init(SysBusDevice *dev) { LedState *s = FROM_SYSBUS(LedState, dev); @@ -261,10 +267,7 @@ static int jazz_led_init(SysBusDevice *dev) memory_region_init_io(&s->iomem, &led_ops, s, "led", 1); sysbus_init_mmio(dev, &s->iomem); - s->con = graphic_console_init(jazz_led_update_display, - jazz_led_invalidate_display, - NULL, - jazz_led_text_update, s); + s->con = graphic_console_init(&jazz_led_ops, s); return 0; } diff --git a/hw/display/milkymist-vgafb.c b/hw/display/milkymist-vgafb.c index 3219041c81..716997caa2 100644 --- a/hw/display/milkymist-vgafb.c +++ b/hw/display/milkymist-vgafb.c @@ -270,6 +270,11 @@ static void milkymist_vgafb_reset(DeviceState *d) s->regs[R_BASEADDRESS] = 0; } +static const GraphicHwOps vgafb_ops = { + .invalidate = vgafb_invalidate_display, + .gfx_update = vgafb_update_display, +}; + static int milkymist_vgafb_init(SysBusDevice *dev) { MilkymistVgafbState *s = FROM_SYSBUS(typeof(*s), dev); @@ -278,9 +283,7 @@ static int milkymist_vgafb_init(SysBusDevice *dev) "milkymist-vgafb", R_MAX * 4); sysbus_init_mmio(dev, &s->regs_region); - s->con = graphic_console_init(vgafb_update_display, - vgafb_invalidate_display, - NULL, NULL, s); + s->con = graphic_console_init(&vgafb_ops, s); return 0; } diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index be7e9c0d74..e4a55958fa 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -227,90 +227,6 @@ static void omap_update_display(void *opaque) omap_lcd->invalidate = 0; } -static void omap_ppm_save(const char *filename, uint8_t *data, - int w, int h, int linesize, Error **errp) -{ - FILE *f; - uint8_t *d, *d1; - unsigned int v; - int ret, y, x, bpp; - - f = fopen(filename, "wb"); - if (!f) { - error_setg(errp, "failed to open file '%s': %s", filename, - strerror(errno)); - return; - } - ret = fprintf(f, "P6\n%d %d\n%d\n", w, h, 255); - if (ret < 0) { - goto write_err; - } - d1 = data; - bpp = linesize / w; - for (y = 0; y < h; y ++) { - d = d1; - for (x = 0; x < w; x ++) { - v = *(uint32_t *) d; - switch (bpp) { - case 2: - ret = fputc((v >> 8) & 0xf8, f); - if (ret == EOF) { - goto write_err; - } - ret = fputc((v >> 3) & 0xfc, f); - if (ret == EOF) { - goto write_err; - } - ret = fputc((v << 3) & 0xf8, f); - if (ret == EOF) { - goto write_err; - } - break; - case 3: - case 4: - default: - ret = fputc((v >> 16) & 0xff, f); - if (ret == EOF) { - goto write_err; - } - ret = fputc((v >> 8) & 0xff, f); - if (ret == EOF) { - goto write_err; - } - ret = fputc((v) & 0xff, f); - if (ret == EOF) { - goto write_err; - } - break; - } - d += bpp; - } - d1 += linesize; - } -out: - fclose(f); - return; - -write_err: - error_setg(errp, "failed to write to file '%s': %s", filename, - strerror(errno)); - unlink(filename); - goto out; -} - -static void omap_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp) -{ - struct omap_lcd_panel_s *omap_lcd = opaque; - DisplaySurface *surface = qemu_console_surface(omap_lcd->con); - - omap_update_display(opaque); - if (omap_lcd && surface_data(surface)) - omap_ppm_save(filename, surface_data(surface), - omap_lcd->width, omap_lcd->height, - surface_stride(surface), errp); -} - static void omap_invalidate_display(void *opaque) { struct omap_lcd_panel_s *omap_lcd = opaque; omap_lcd->invalidate = 1; @@ -468,6 +384,11 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s) s->ctrl = 0; } +static const GraphicHwOps omap_ops = { + .invalidate = omap_invalidate_display, + .gfx_update = omap_update_display, +}; + struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, hwaddr base, qemu_irq irq, @@ -485,9 +406,7 @@ struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100); memory_region_add_subregion(sysmem, base, &s->iomem); - s->con = graphic_console_init(omap_update_display, - omap_invalidate_display, - omap_screen_dump, NULL, s); + s->con = graphic_console_init(&omap_ops, s); return s; } diff --git a/hw/display/pl110.c b/hw/display/pl110.c index 295434eded..d23243199c 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -444,6 +444,11 @@ static int vmstate_pl110_post_load(void *opaque, int version_id) return 0; } +static const GraphicHwOps pl110_gfx_ops = { + .invalidate = pl110_invalidate_display, + .gfx_update = pl110_update_display, +}; + static int pl110_init(SysBusDevice *dev) { pl110_state *s = FROM_SYSBUS(pl110_state, dev); @@ -452,9 +457,7 @@ static int pl110_init(SysBusDevice *dev) sysbus_init_mmio(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1); - s->con = graphic_console_init(pl110_update_display, - pl110_invalidate_display, - NULL, NULL, s); + s->con = graphic_console_init(&pl110_gfx_ops, s); return 0; } diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c index c9bd42e023..12d9cd2808 100644 --- a/hw/display/pxa2xx_lcd.c +++ b/hw/display/pxa2xx_lcd.c @@ -991,6 +991,11 @@ static const VMStateDescription vmstate_pxa2xx_lcdc = { #define BITS 32 #include "pxa2xx_template.h" +static const GraphicHwOps pxa2xx_ops = { + .invalidate = pxa2xx_invalidate_display, + .gfx_update = pxa2xx_update_display, +}; + PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, hwaddr base, qemu_irq irq) { @@ -1008,9 +1013,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, "pxa2xx-lcd-controller", 0x00100000); memory_region_add_subregion(sysmem, base, &s->iomem); - s->con = graphic_console_init(pxa2xx_update_display, - pxa2xx_invalidate_display, - NULL, NULL, s); + s->con = graphic_console_init(&pxa2xx_ops, s); surface = qemu_console_surface(s->con); switch (surface_bits_per_pixel(surface)) { diff --git a/hw/display/qxl.c b/hw/display/qxl.c index cb47995b84..e679830fed 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1080,7 +1080,7 @@ static void qxl_enter_vga_mode(PCIQXLDevice *d) qemu_spice_create_host_primary(&d->ssd); d->mode = QXL_MODE_VGA; vga_dirty_log_start(&d->vga); - vga_hw_update(); + graphic_hw_update(d->vga.con); } static void qxl_exit_vga_mode(PCIQXLDevice *d) @@ -1759,7 +1759,7 @@ static void qxl_hw_update(void *opaque) switch (qxl->mode) { case QXL_MODE_VGA: - vga->update(vga); + vga->hw_ops->gfx_update(vga); break; case QXL_MODE_COMPAT: case QXL_MODE_NATIVE: @@ -1775,26 +1775,9 @@ static void qxl_hw_invalidate(void *opaque) PCIQXLDevice *qxl = opaque; VGACommonState *vga = &qxl->vga; - vga->invalidate(vga); -} - -static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp) -{ - PCIQXLDevice *qxl = opaque; - VGACommonState *vga = &qxl->vga; - - switch (qxl->mode) { - case QXL_MODE_COMPAT: - case QXL_MODE_NATIVE: - qxl_render_update(qxl); - ppm_save(filename, qxl->ssd.ds, errp); - break; - case QXL_MODE_VGA: - vga->screen_dump(vga, filename, cswitch, errp); - break; - default: - break; + if (qxl->mode == QXL_MODE_VGA) { + vga->hw_ops->invalidate(vga); + return; } } @@ -1804,7 +1787,7 @@ static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) VGACommonState *vga = &qxl->vga; if (qxl->mode == QXL_MODE_VGA) { - vga->text_update(vga, chardata); + vga->hw_ops->text_update(vga, chardata); return; } } @@ -2064,6 +2047,12 @@ static int qxl_init_common(PCIQXLDevice *qxl) return 0; } +static const GraphicHwOps qxl_ops = { + .invalidate = qxl_hw_invalidate, + .gfx_update = qxl_hw_update, + .text_update = qxl_hw_text_update, +}; + static int qxl_init_primary(PCIDevice *dev) { PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); @@ -2080,10 +2069,7 @@ static int qxl_init_primary(PCIDevice *dev) portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); - vga->con = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, - qxl_hw_screen_dump, qxl_hw_text_update, - qxl); - qxl->ssd.con = vga->con, + vga->con = graphic_console_init(&qxl_ops, qxl); qemu_spice_display_init_common(&qxl->ssd); rc = qxl_init_common(qxl); @@ -2092,6 +2078,7 @@ static int qxl_init_primary(PCIDevice *dev) } qxl->ssd.dcl.ops = &display_listener_ops; + qxl->ssd.dcl.con = vga->con; ds = qemu_console_displaystate(vga->con); register_displaychangelistener(ds, &qxl->ssd.dcl); return rc; @@ -2107,6 +2094,7 @@ static int qxl_init_secondary(PCIDevice *dev) memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); + qxl->vga.con = graphic_console_init(&qxl_ops, qxl); return qxl_init_common(qxl); } diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 9878df4af6..f0e6d7022f 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -1383,6 +1383,10 @@ static void sm501_update_display(void *opaque) sm501_draw_crt(s); } +static const GraphicHwOps sm501_ops = { + .gfx_update = sm501_update_display, +}; + void sm501_init(MemoryRegion *address_space_mem, uint32_t base, uint32_t local_mem_bytes, qemu_irq irq, CharDriverState *chr) { @@ -1445,6 +1449,5 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base, } /* create qemu graphic console */ - s->con = graphic_console_init(sm501_update_display, NULL, - NULL, NULL, s); + s->con = graphic_console_init(&sm501_ops, s); } diff --git a/hw/display/ssd0303.c b/hw/display/ssd0303.c index 183a87835c..3d7ebbe6e2 100644 --- a/hw/display/ssd0303.c +++ b/hw/display/ssd0303.c @@ -284,13 +284,16 @@ static const VMStateDescription vmstate_ssd0303 = { } }; +static const GraphicHwOps ssd0303_ops = { + .invalidate = ssd0303_invalidate_display, + .gfx_update = ssd0303_update_display, +}; + static int ssd0303_init(I2CSlave *i2c) { ssd0303_state *s = FROM_I2C_SLAVE(ssd0303_state, i2c); - s->con = graphic_console_init(ssd0303_update_display, - ssd0303_invalidate_display, - NULL, NULL, s); + s->con = graphic_console_init(&ssd0303_ops, s); qemu_console_resize(s->con, 96 * MAGNIFY, 16 * MAGNIFY); return 0; } diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index 5cf2f7058f..45e8dc1125 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -331,15 +331,18 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id) return 0; } +static const GraphicHwOps ssd0323_ops = { + .invalidate = ssd0323_invalidate_display, + .gfx_update = ssd0323_update_display, +}; + static int ssd0323_init(SSISlave *dev) { ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev); s->col_end = 63; s->row_end = 79; - s->con = graphic_console_init(ssd0323_update_display, - ssd0323_invalidate_display, - NULL, NULL, s); + s->con = graphic_console_init(&ssd0323_ops, s); qemu_console_resize(s->con, 128 * MAGNIFY, 64 * MAGNIFY); qdev_init_gpio_in(&dev->qdev, ssd0323_cd, 1); diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c index 178a21fd8d..b5b255c31a 100644 --- a/hw/display/tc6393xb.c +++ b/hw/display/tc6393xb.c @@ -548,6 +548,10 @@ static void tc6393xb_writeb(void *opaque, hwaddr addr, (uint32_t) addr, (int)value & 0xff); } +static const GraphicHwOps tc6393xb_gfx_ops = { + .gfx_update = tc6393xb_update_display, +}; + TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) { TC6393xbState *s; @@ -583,11 +587,7 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); s->scr_width = 480; s->scr_height = 640; - s->con = graphic_console_init(tc6393xb_update_display, - NULL, /* invalidate */ - NULL, /* screen_dump */ - NULL, /* text_update */ - s); + s->con = graphic_console_init(&tc6393xb_gfx_ops, s); return s; } diff --git a/hw/display/tcx.c b/hw/display/tcx.c index c44068e7c9..77c7191c76 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -56,11 +56,6 @@ typedef struct TCXState { uint8_t dac_index, dac_state; } TCXState; -static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp); -static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp); - static void tcx_set_dirty(TCXState *s) { memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY); @@ -515,6 +510,16 @@ static const MemoryRegionOps dummy_ops = { }, }; +static const GraphicHwOps tcx_ops = { + .invalidate = tcx_invalidate_display, + .gfx_update = tcx_update_display, +}; + +static const GraphicHwOps tcx24_ops = { + .invalidate = tcx24_invalidate_display, + .gfx_update = tcx24_update_display, +}; + static int tcx_init1(SysBusDevice *dev) { TCXState *s = FROM_SYSBUS(TCXState, dev); @@ -567,144 +572,20 @@ static int tcx_init1(SysBusDevice *dev) &s->vram_mem, vram_offset, size); sysbus_init_mmio(dev, &s->vram_cplane); - s->con = graphic_console_init(tcx24_update_display, - tcx24_invalidate_display, - tcx24_screen_dump, NULL, s); + s->con = graphic_console_init(&tcx24_ops, s); } else { /* THC 8 bit (dummy) */ memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8", TCX_THC_NREGS_8); sysbus_init_mmio(dev, &s->thc8); - s->con = graphic_console_init(tcx_update_display, - tcx_invalidate_display, - tcx_screen_dump, NULL, s); + s->con = graphic_console_init(&tcx_ops, s); } qemu_console_resize(s->con, s->width, s->height); return 0; } -static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp) -{ - TCXState *s = opaque; - FILE *f; - uint8_t *d, *d1, v; - int ret, y, x; - - f = fopen(filename, "wb"); - if (!f) { - error_setg(errp, "failed to open file '%s': %s", filename, - strerror(errno)); - return; - } - ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); - if (ret < 0) { - goto write_err; - } - d1 = s->vram; - for(y = 0; y < s->height; y++) { - d = d1; - for(x = 0; x < s->width; x++) { - v = *d; - ret = fputc(s->r[v], f); - if (ret == EOF) { - goto write_err; - } - ret = fputc(s->g[v], f); - if (ret == EOF) { - goto write_err; - } - ret = fputc(s->b[v], f); - if (ret == EOF) { - goto write_err; - } - d++; - } - d1 += MAXX; - } - -out: - fclose(f); - return; - -write_err: - error_setg(errp, "failed to write to file '%s': %s", filename, - strerror(errno)); - unlink(filename); - goto out; -} - -static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp) -{ - TCXState *s = opaque; - FILE *f; - uint8_t *d, *d1, v; - uint32_t *s24, *cptr, dval; - int ret, y, x; - - f = fopen(filename, "wb"); - if (!f) { - error_setg(errp, "failed to open file '%s': %s", filename, - strerror(errno)); - return; - } - ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); - if (ret < 0) { - goto write_err; - } - d1 = s->vram; - s24 = s->vram24; - cptr = s->cplane; - for(y = 0; y < s->height; y++) { - d = d1; - for(x = 0; x < s->width; x++, d++, s24++) { - if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct - dval = *s24 & 0x00ffffff; - ret = fputc((dval >> 16) & 0xff, f); - if (ret == EOF) { - goto write_err; - } - ret = fputc((dval >> 8) & 0xff, f); - if (ret == EOF) { - goto write_err; - } - ret = fputc(dval & 0xff, f); - if (ret == EOF) { - goto write_err; - } - } else { - v = *d; - ret = fputc(s->r[v], f); - if (ret == EOF) { - goto write_err; - } - ret = fputc(s->g[v], f); - if (ret == EOF) { - goto write_err; - } - ret = fputc(s->b[v], f); - if (ret == EOF) { - goto write_err; - } - } - } - d1 += MAXX; - } - -out: - fclose(f); - return; - -write_err: - error_setg(errp, "failed to write to file '%s': %s", filename, - strerror(errno)); - unlink(filename); - goto out; -} - static Property tcx_properties[] = { DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), DEFINE_PROP_UINT16("width", TCXState, width, -1), diff --git a/hw/display/vga-isa-mm.c b/hw/display/vga-isa-mm.c index 1c50070216..2da08a11f7 100644 --- a/hw/display/vga-isa-mm.c +++ b/hw/display/vga-isa-mm.c @@ -135,9 +135,7 @@ int isa_vga_mm_init(hwaddr vram_base, vga_common_init(&s->vga); vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space); - s->vga.con = graphic_console_init(s->vga.update, s->vga.invalidate, - s->vga.screen_dump, s->vga.text_update, - s); + s->vga.con = graphic_console_init(s->vga.hw_ops, s); vga_init_vbe(&s->vga, address_space); return 0; diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c index 90959ebc2c..d2c548e14c 100644 --- a/hw/display/vga-isa.c +++ b/hw/display/vga-isa.c @@ -62,8 +62,7 @@ static int vga_initfn(ISADevice *dev) isa_mem_base + 0x000a0000, vga_io_memory, 1); memory_region_set_coalescing(vga_io_memory); - s->con = graphic_console_init(s->update, s->invalidate, - s->screen_dump, s->text_update, s); + s->con = graphic_console_init(s->hw_ops, s); vga_init_vbe(s, isa_address_space(dev)); /* ROM BIOS */ diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c index a9c69b6ac7..dc73f286da 100644 --- a/hw/display/vga-pci.c +++ b/hw/display/vga-pci.c @@ -150,8 +150,7 @@ static int pci_std_vga_initfn(PCIDevice *dev) vga_common_init(s); vga_init(s, pci_address_space(dev), pci_address_space_io(dev), true); - s->con = graphic_console_init(s->update, s->invalidate, - s->screen_dump, s->text_update, s); + s->con = graphic_console_init(s->hw_ops, s); /* XXX: VGA_RAM_SIZE must be a power of two */ pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram); diff --git a/hw/display/vga.c b/hw/display/vga.c index c1b67bbbf8..21a108d8c0 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -166,9 +166,6 @@ static uint32_t expand4[256]; static uint16_t expand2[256]; static uint8_t expand4to8[16]; -static void vga_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp); - static void vga_update_memory_access(VGACommonState *s) { MemoryRegion *region, *old_region = s->chain4_alias; @@ -2253,6 +2250,12 @@ const VMStateDescription vmstate_vga_common = { } }; +static const GraphicHwOps vga_ops = { + .invalidate = vga_invalidate_display, + .gfx_update = vga_update_display, + .text_update = vga_update_text, +}; + void vga_common_init(VGACommonState *s) { int i, j, v, b; @@ -2296,10 +2299,7 @@ void vga_common_init(VGACommonState *s) s->get_bpp = vga_get_bpp; s->get_offsets = vga_get_offsets; s->get_resolution = vga_get_resolution; - s->update = vga_update_display; - s->invalidate = vga_invalidate_display; - s->screen_dump = vga_screen_dump; - s->text_update = vga_update_text; + s->hw_ops = &vga_ops; switch (vga_retrace_method) { case VGA_RETRACE_DUMB: s->retrace = vga_dumb_retrace; @@ -2393,65 +2393,3 @@ void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory) &s->vram_vbe); s->vbe_mapped = 1; } -/********************************************************/ -/* vga screen dump */ - -void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp) -{ - int width = pixman_image_get_width(ds->image); - int height = pixman_image_get_height(ds->image); - FILE *f; - int y; - int ret; - pixman_image_t *linebuf; - - trace_ppm_save(filename, ds); - f = fopen(filename, "wb"); - if (!f) { - error_setg(errp, "failed to open file '%s': %s", filename, - strerror(errno)); - return; - } - ret = fprintf(f, "P6\n%d %d\n%d\n", width, height, 255); - if (ret < 0) { - linebuf = NULL; - goto write_err; - } - linebuf = qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); - for (y = 0; y < height; y++) { - qemu_pixman_linebuf_fill(linebuf, ds->image, width, 0, y); - clearerr(f); - ret = fwrite(pixman_image_get_data(linebuf), 1, - pixman_image_get_stride(linebuf), f); - (void)ret; - if (ferror(f)) { - goto write_err; - } - } - -out: - qemu_pixman_image_unref(linebuf); - fclose(f); - return; - -write_err: - error_setg(errp, "failed to write to file '%s': %s", filename, - strerror(errno)); - unlink(filename); - goto out; -} - -/* save the vga display in a PPM image even if no display is - available */ -static void vga_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp) -{ - VGACommonState *s = opaque; - DisplaySurface *surface = qemu_console_surface(s->con); - - if (cswitch) { - vga_invalidate_display(s); - } - vga_hw_update(); - ppm_save(filename, surface, errp); -} diff --git a/hw/display/vga_int.h b/hw/display/vga_int.h index 260f7d6948..66f9f3ceed 100644 --- a/hw/display/vga_int.h +++ b/hw/display/vga_int.h @@ -152,10 +152,7 @@ typedef struct VGACommonState { uint32_t cursor_offset; unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b); - vga_hw_update_ptr update; - vga_hw_invalidate_ptr invalidate; - vga_hw_screen_dump_ptr screen_dump; - vga_hw_text_update_ptr text_update; + const GraphicHwOps *hw_ops; bool full_update_text; bool full_update_gfx; /* hardware mouse cursor support */ @@ -198,7 +195,6 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val); uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr); void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val); void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2); -void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp); int vga_ioport_invalid(VGACommonState *s, uint32_t addr); diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index bcad47a68d..263bf0915e 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -39,8 +39,6 @@ struct vmsvga_state_s { VGACommonState vga; int invalidated; - int depth; - int bypp; int enable; int config; struct { @@ -55,6 +53,7 @@ struct vmsvga_state_s { uint32_t *scratch; int new_width; int new_height; + int new_depth; uint32_t guest; uint32_t svgaid; int syncing; @@ -721,61 +720,88 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) uint32_t caps; struct vmsvga_state_s *s = opaque; DisplaySurface *surface = qemu_console_surface(s->vga.con); + PixelFormat pf; + uint32_t ret; switch (s->index) { case SVGA_REG_ID: - return s->svgaid; + ret = s->svgaid; + break; case SVGA_REG_ENABLE: - return s->enable; + ret = s->enable; + break; case SVGA_REG_WIDTH: - return surface_width(surface); + ret = s->new_width ? s->new_width : surface_width(surface); + break; case SVGA_REG_HEIGHT: - return surface_height(surface); + ret = s->new_height ? s->new_height : surface_height(surface); + break; case SVGA_REG_MAX_WIDTH: - return SVGA_MAX_WIDTH; + ret = SVGA_MAX_WIDTH; + break; case SVGA_REG_MAX_HEIGHT: - return SVGA_MAX_HEIGHT; + ret = SVGA_MAX_HEIGHT; + break; case SVGA_REG_DEPTH: - return s->depth; + ret = (s->new_depth == 32) ? 24 : s->new_depth; + break; case SVGA_REG_BITS_PER_PIXEL: - return (s->depth + 7) & ~7; + case SVGA_REG_HOST_BITS_PER_PIXEL: + ret = s->new_depth; + break; case SVGA_REG_PSEUDOCOLOR: - return 0x0; + ret = 0x0; + break; case SVGA_REG_RED_MASK: - return surface->pf.rmask; + pf = qemu_default_pixelformat(s->new_depth); + ret = pf.rmask; + break; case SVGA_REG_GREEN_MASK: - return surface->pf.gmask; + pf = qemu_default_pixelformat(s->new_depth); + ret = pf.gmask; + break; case SVGA_REG_BLUE_MASK: - return surface->pf.bmask; + pf = qemu_default_pixelformat(s->new_depth); + ret = pf.bmask; + break; case SVGA_REG_BYTES_PER_LINE: - return s->bypp * s->new_width; + if (s->new_width) { + ret = (s->new_depth * s->new_width) / 8; + } else { + ret = surface_stride(surface); + } + break; case SVGA_REG_FB_START: { struct pci_vmsvga_state_s *pci_vmsvga = container_of(s, struct pci_vmsvga_state_s, chip); - return pci_get_bar_addr(&pci_vmsvga->card, 1); + ret = pci_get_bar_addr(&pci_vmsvga->card, 1); + break; } case SVGA_REG_FB_OFFSET: - return 0x0; + ret = 0x0; + break; case SVGA_REG_VRAM_SIZE: - return s->vga.vram_size; /* No physical VRAM besides the framebuffer */ + ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ + break; case SVGA_REG_FB_SIZE: - return s->vga.vram_size; + ret = s->vga.vram_size; + break; case SVGA_REG_CAPABILITIES: caps = SVGA_CAP_NONE; @@ -791,66 +817,92 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) SVGA_CAP_CURSOR_BYPASS; } #endif - return caps; + ret = caps; + break; case SVGA_REG_MEM_START: { struct pci_vmsvga_state_s *pci_vmsvga = container_of(s, struct pci_vmsvga_state_s, chip); - return pci_get_bar_addr(&pci_vmsvga->card, 2); + ret = pci_get_bar_addr(&pci_vmsvga->card, 2); + break; } case SVGA_REG_MEM_SIZE: - return s->fifo_size; + ret = s->fifo_size; + break; case SVGA_REG_CONFIG_DONE: - return s->config; + ret = s->config; + break; case SVGA_REG_SYNC: case SVGA_REG_BUSY: - return s->syncing; + ret = s->syncing; + break; case SVGA_REG_GUEST_ID: - return s->guest; + ret = s->guest; + break; case SVGA_REG_CURSOR_ID: - return s->cursor.id; + ret = s->cursor.id; + break; case SVGA_REG_CURSOR_X: - return s->cursor.x; + ret = s->cursor.x; + break; case SVGA_REG_CURSOR_Y: - return s->cursor.x; + ret = s->cursor.x; + break; case SVGA_REG_CURSOR_ON: - return s->cursor.on; - - case SVGA_REG_HOST_BITS_PER_PIXEL: - return (s->depth + 7) & ~7; + ret = s->cursor.on; + break; case SVGA_REG_SCRATCH_SIZE: - return s->scratch_size; + ret = s->scratch_size; + break; case SVGA_REG_MEM_REGS: case SVGA_REG_NUM_DISPLAYS: case SVGA_REG_PITCHLOCK: case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: - return 0; + ret = 0; + break; default: if (s->index >= SVGA_SCRATCH_BASE && s->index < SVGA_SCRATCH_BASE + s->scratch_size) { - return s->scratch[s->index - SVGA_SCRATCH_BASE]; + ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; + break; } printf("%s: Bad register %02x\n", __func__, s->index); + ret = 0; + break; } - return 0; + if (s->index >= SVGA_SCRATCH_BASE) { + trace_vmware_scratch_read(s->index, ret); + } else if (s->index >= SVGA_PALETTE_BASE) { + trace_vmware_palette_read(s->index, ret); + } else { + trace_vmware_value_read(s->index, ret); + } + return ret; } static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) { struct vmsvga_state_s *s = opaque; + if (s->index >= SVGA_SCRATCH_BASE) { + trace_vmware_scratch_write(s->index, value); + } else if (s->index >= SVGA_PALETTE_BASE) { + trace_vmware_palette_write(s->index, value); + } else { + trace_vmware_value_write(s->index, value); + } switch (s->index) { case SVGA_REG_ID: if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { @@ -861,7 +913,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) case SVGA_REG_ENABLE: s->enable = !!value; s->invalidated = 1; - s->vga.invalidate(&s->vga); + s->vga.hw_ops->invalidate(&s->vga); if (s->enable && s->config) { vga_dirty_log_stop(&s->vga); } else { @@ -888,9 +940,10 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) break; case SVGA_REG_BITS_PER_PIXEL: - if (value != s->depth) { + if (value != 32) { printf("%s: Bad bits per pixel: %i bits\n", __func__, value); s->config = 0; + s->invalidated = 1; } break; @@ -986,8 +1039,14 @@ static inline void vmsvga_check_size(struct vmsvga_state_s *s) DisplaySurface *surface = qemu_console_surface(s->vga.con); if (s->new_width != surface_width(surface) || - s->new_height != surface_height(surface)) { - qemu_console_resize(s->vga.con, s->new_width, s->new_height); + s->new_height != surface_height(surface) || + s->new_depth != surface_bits_per_pixel(surface)) { + int stride = (s->new_depth * s->new_width) / 8; + trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); + surface = qemu_create_displaysurface_from(s->new_width, s->new_height, + s->new_depth, stride, + s->vga.vram_ptr, false); + dpy_gfx_replace_surface(s->vga.con, surface); s->invalidated = 1; } } @@ -995,15 +1054,16 @@ static inline void vmsvga_check_size(struct vmsvga_state_s *s) static void vmsvga_update_display(void *opaque) { struct vmsvga_state_s *s = opaque; - DisplaySurface *surface = qemu_console_surface(s->vga.con); + DisplaySurface *surface; bool dirty = false; if (!s->enable) { - s->vga.update(&s->vga); + s->vga.hw_ops->gfx_update(&s->vga); return; } vmsvga_check_size(s); + surface = qemu_console_surface(s->vga.con); vmsvga_fifo_run(s); vmsvga_update_rect_flush(s); @@ -1020,8 +1080,6 @@ static void vmsvga_update_display(void *opaque) } if (s->invalidated || dirty) { s->invalidated = 0; - memcpy(surface_data(surface), s->vga.vram_ptr, - surface_stride(surface) * surface_height(surface)); dpy_gfx_update(s->vga.con, 0, 0, surface_width(surface), surface_height(surface)); } @@ -1054,44 +1112,19 @@ static void vmsvga_invalidate_display(void *opaque) { struct vmsvga_state_s *s = opaque; if (!s->enable) { - s->vga.invalidate(&s->vga); + s->vga.hw_ops->invalidate(&s->vga); return; } s->invalidated = 1; } -/* save the vga display in a PPM image even if no display is - available */ -static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch, - Error **errp) -{ - struct vmsvga_state_s *s = opaque; - DisplaySurface *surface = qemu_console_surface(s->vga.con); - - if (!s->enable) { - s->vga.screen_dump(&s->vga, filename, cswitch, errp); - return; - } - - if (surface_bits_per_pixel(surface) == 32) { - DisplaySurface *ds = qemu_create_displaysurface_from( - surface_width(surface), - surface_height(surface), - 32, - surface_stride(surface), - s->vga.vram_ptr, false); - ppm_save(filename, ds, errp); - g_free(ds); - } -} - static void vmsvga_text_update(void *opaque, console_ch_t *chardata) { struct vmsvga_state_s *s = opaque; - if (s->vga.text_update) { - s->vga.text_update(&s->vga, chardata); + if (s->vga.hw_ops->text_update) { + s->vga.hw_ops->text_update(&s->vga, chardata); } } @@ -1113,7 +1146,7 @@ static const VMStateDescription vmstate_vmware_vga_internal = { .minimum_version_id_old = 0, .post_load = vmsvga_post_load, .fields = (VMStateField[]) { - VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s), + VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), VMSTATE_INT32(enable, struct vmsvga_state_s), VMSTATE_INT32(config, struct vmsvga_state_s), VMSTATE_INT32(cursor.id, struct vmsvga_state_s), @@ -1146,19 +1179,19 @@ static const VMStateDescription vmstate_vmware_vga = { } }; +static const GraphicHwOps vmsvga_ops = { + .invalidate = vmsvga_invalidate_display, + .gfx_update = vmsvga_update_display, + .text_update = vmsvga_text_update, +}; + static void vmsvga_init(struct vmsvga_state_s *s, MemoryRegion *address_space, MemoryRegion *io) { - DisplaySurface *surface; - s->scratch_size = SVGA_SCRATCH_SIZE; s->scratch = g_malloc(s->scratch_size * 4); - s->vga.con = graphic_console_init(vmsvga_update_display, - vmsvga_invalidate_display, - vmsvga_screen_dump, - vmsvga_text_update, s); - surface = qemu_console_surface(s->vga.con); + s->vga.con = graphic_console_init(&vmsvga_ops, s); s->fifo_size = SVGA_FIFO_SIZE; memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size); @@ -1168,10 +1201,7 @@ static void vmsvga_init(struct vmsvga_state_s *s, vga_common_init(&s->vga); vga_init(&s->vga, address_space, io, true); vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); - /* Save some values here in case they are changed later. - * This is suspicious and needs more though why it is needed. */ - s->depth = surface_bits_per_pixel(surface); - s->bypp = surface_bytes_per_pixel(surface); + s->new_depth = 32; } static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c index e371569585..f2eb89fa7f 100644 --- a/hw/display/xenfb.c +++ b/hw/display/xenfb.c @@ -78,7 +78,6 @@ struct XenFB { void *pixels; int fbpages; int feature_update; - int refresh_period; int bug_trigger; int have_console; int do_resize; @@ -646,7 +645,7 @@ static void xenfb_guest_copy(struct XenFB *xenfb, int x, int y, int w, int h) dpy_gfx_update(xenfb->c.con, x, y, w, h); } -#if 0 /* def XENFB_TYPE_REFRESH_PERIOD */ +#ifdef XENFB_TYPE_REFRESH_PERIOD static int xenfb_queue_full(struct XenFB *xenfb) { struct xenfb_page *page = xenfb->c.page; @@ -704,39 +703,7 @@ static void xenfb_update(void *opaque) if (xenfb->c.xendev.be_state != XenbusStateConnected) return; - if (xenfb->feature_update) { -#if 0 /* XENFB_TYPE_REFRESH_PERIOD */ - struct DisplayChangeListener *l; - int period = 99999999; - int idle = 1; - - if (xenfb_queue_full(xenfb)) - return; - - QLIST_FOREACH(l, &xenfb->c.ds->listeners, next) { - if (l->idle) - continue; - idle = 0; - if (!l->gui_timer_interval) { - if (period > GUI_REFRESH_INTERVAL) - period = GUI_REFRESH_INTERVAL; - } else { - if (period > l->gui_timer_interval) - period = l->gui_timer_interval; - } - } - if (idle) - period = XENFB_NO_REFRESH; - - if (xenfb->refresh_period != period) { - xenfb_send_refresh_period(xenfb, period); - xenfb->refresh_period = period; - xen_be_printf(&xenfb->c.xendev, 1, "refresh period: %d\n", period); - } -#else - ; /* nothing */ -#endif - } else { + if (!xenfb->feature_update) { /* we don't get update notifications, thus use the * sledge hammer approach ... */ xenfb->up_fullscreen = 1; @@ -785,6 +752,20 @@ static void xenfb_update(void *opaque) xenfb->up_fullscreen = 0; } +static void xenfb_update_interval(void *opaque, uint64_t interval) +{ + struct XenFB *xenfb = opaque; + + if (xenfb->feature_update) { +#ifdef XENFB_TYPE_REFRESH_PERIOD + if (xenfb_queue_full(xenfb)) { + return; + } + xenfb_send_refresh_period(xenfb, interval); +#endif + } +} + /* QEMU display state changed, so refresh the framebuffer copy */ static void xenfb_invalidate(void *opaque) { @@ -858,10 +839,6 @@ static void xenfb_handle_events(struct XenFB *xenfb) static int fb_init(struct XenDevice *xendev) { - struct XenFB *fb = container_of(xendev, struct XenFB, c.xendev); - - fb->refresh_period = -1; - #ifdef XENFB_TYPE_RESIZE xenstore_write_be_int(xendev, "feature-resize", 1); #endif @@ -977,6 +954,12 @@ struct XenDevOps xen_framebuffer_ops = { .frontend_changed = fb_frontend_changed, }; +static const GraphicHwOps xenfb_ops = { + .invalidate = xenfb_invalidate, + .gfx_update = xenfb_update, + .update_interval = xenfb_update_interval, +}; + /* * FIXME/TODO: Kill this. * Temporary needed while DisplayState reorganization is in flight. @@ -1004,11 +987,7 @@ wait_more: /* vfb */ fb = container_of(xfb, struct XenFB, c.xendev); - fb->c.con = graphic_console_init(xenfb_update, - xenfb_invalidate, - NULL, - NULL, - fb); + fb->c.con = graphic_console_init(&xenfb_ops, fb); fb->have_console = 1; /* vkbd */ diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 8db1a74acf..1c23762210 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -27,17 +27,39 @@ #include "hw/ptimer.h" #include "qemu/log.h" #include "hw/qdev-addr.h" +#include "qapi/qmp/qerror.h" #include "hw/stream.h" #define D(x) +#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma" +#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream" +#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream" + +#define XILINX_AXI_DMA(obj) \ + OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA) + +#define XILINX_AXI_DMA_DATA_STREAM(obj) \ + OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ + TYPE_XILINX_AXI_DMA_DATA_STREAM) + +#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \ + OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ + TYPE_XILINX_AXI_DMA_CONTROL_STREAM) + #define R_DMACR (0x00 / 4) #define R_DMASR (0x04 / 4) #define R_CURDESC (0x08 / 4) #define R_TAILDESC (0x10 / 4) #define R_MAX (0x30 / 4) +#define CONTROL_PAYLOAD_WORDS 5 +#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) + +typedef struct XilinxAXIDMA XilinxAXIDMA; +typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave; + enum { DMACR_RUNSTOP = 1, DMACR_TAILPTR_MODE = 2, @@ -59,7 +81,7 @@ struct SDesc { uint64_t reserved; uint32_t control; uint32_t status; - uint32_t app[6]; + uint8_t app[CONTROL_PAYLOAD_SIZE]; }; enum { @@ -87,15 +109,28 @@ struct Stream { int pos; unsigned int complete_cnt; uint32_t regs[R_MAX]; + uint8_t app[20]; +}; + +struct XilinxAXIDMAStreamSlave { + Object parent; + + struct XilinxAXIDMA *dma; }; struct XilinxAXIDMA { SysBusDevice busdev; MemoryRegion iomem; uint32_t freqhz; - StreamSlave *tx_dev; + StreamSlave *tx_data_dev; + StreamSlave *tx_control_dev; + XilinxAXIDMAStreamSlave rx_data_dev; + XilinxAXIDMAStreamSlave rx_control_dev; struct Stream streams[2]; + + StreamCanPushNotifyFn notify; + void *notify_opaque; }; /* @@ -161,7 +196,6 @@ static void stream_desc_show(struct SDesc *d) static void stream_desc_load(struct Stream *s, hwaddr addr) { struct SDesc *d = &s->desc; - int i; cpu_physical_memory_read(addr, (void *) d, sizeof *d); @@ -170,24 +204,17 @@ static void stream_desc_load(struct Stream *s, hwaddr addr) d->nxtdesc = le64_to_cpu(d->nxtdesc); d->control = le32_to_cpu(d->control); d->status = le32_to_cpu(d->status); - for (i = 0; i < ARRAY_SIZE(d->app); i++) { - d->app[i] = le32_to_cpu(d->app[i]); - } } static void stream_desc_store(struct Stream *s, hwaddr addr) { struct SDesc *d = &s->desc; - int i; /* Convert from host endianness into LE. */ d->buffer_address = cpu_to_le64(d->buffer_address); d->nxtdesc = cpu_to_le64(d->nxtdesc); d->control = cpu_to_le32(d->control); d->status = cpu_to_le32(d->status); - for (i = 0; i < ARRAY_SIZE(d->app); i++) { - d->app[i] = cpu_to_le32(d->app[i]); - } cpu_physical_memory_write(addr, (void *) d, sizeof *d); } @@ -239,13 +266,12 @@ static void stream_complete(struct Stream *s) } } -static void stream_process_mem2s(struct Stream *s, - StreamSlave *tx_dev) +static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, + StreamSlave *tx_control_dev) { uint32_t prev_d; unsigned char txbuf[16 * 1024]; unsigned int txlen; - uint32_t app[6]; if (!stream_running(s) || stream_idle(s)) { return; @@ -255,13 +281,13 @@ static void stream_process_mem2s(struct Stream *s, stream_desc_load(s, s->regs[R_CURDESC]); if (s->desc.status & SDESC_STATUS_COMPLETE) { - s->regs[R_DMASR] |= DMASR_IDLE; + s->regs[R_DMASR] |= DMASR_HALTED; break; } if (stream_desc_sof(&s->desc)) { s->pos = 0; - memcpy(app, s->desc.app, sizeof app); + stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app)); } txlen = s->desc.control & SDESC_CTRL_LEN_MASK; @@ -275,7 +301,7 @@ static void stream_process_mem2s(struct Stream *s, s->pos += txlen; if (stream_desc_eof(&s->desc)) { - stream_push(tx_dev, txbuf, s->pos, app); + stream_push(tx_data_dev, txbuf, s->pos); s->pos = 0; stream_complete(s); } @@ -294,23 +320,23 @@ static void stream_process_mem2s(struct Stream *s, } } -static void stream_process_s2mem(struct Stream *s, - unsigned char *buf, size_t len, uint32_t *app) +static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf, + size_t len) { uint32_t prev_d; unsigned int rxlen; - int pos = 0; + size_t pos = 0; int sof = 1; if (!stream_running(s) || stream_idle(s)) { - return; + return 0; } while (len) { stream_desc_load(s, s->regs[R_CURDESC]); if (s->desc.status & SDESC_STATUS_COMPLETE) { - s->regs[R_DMASR] |= DMASR_IDLE; + s->regs[R_DMASR] |= DMASR_HALTED; break; } @@ -326,12 +352,8 @@ static void stream_process_s2mem(struct Stream *s, /* Update the descriptor. */ if (!len) { - int i; - stream_complete(s); - for (i = 0; i < 5; i++) { - s->desc.app[i] = app[i]; - } + memcpy(s->desc.app, s->app, sizeof(s->desc.app)); s->desc.status |= SDESC_STATUS_EOF; } @@ -348,25 +370,69 @@ static void stream_process_s2mem(struct Stream *s, break; } } + + return pos; +} + +static void xilinx_axidma_reset(DeviceState *dev) +{ + int i; + XilinxAXIDMA *s = XILINX_AXI_DMA(dev); + + for (i = 0; i < 2; i++) { + stream_reset(&s->streams[i]); + } } -static void -axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app) +static size_t +xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf, + size_t len) { - struct XilinxAXIDMA *d = FROM_SYSBUS(typeof(*d), SYS_BUS_DEVICE(obj)); - struct Stream *s = &d->streams[1]; + XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); + struct Stream *s = &cs->dma->streams[1]; - if (!app) { - hw_error("No stream app data!\n"); + if (len != CONTROL_PAYLOAD_SIZE) { + hw_error("AXI DMA requires %d byte control stream payload\n", + (int)CONTROL_PAYLOAD_SIZE); } - stream_process_s2mem(s, buf, len, app); + + memcpy(s->app, buf, len); + return len; +} + +static bool +xilinx_axidma_data_stream_can_push(StreamSlave *obj, + StreamCanPushNotifyFn notify, + void *notify_opaque) +{ + XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); + struct Stream *s = &ds->dma->streams[1]; + + if (!stream_running(s) || stream_idle(s)) { + ds->dma->notify = notify; + ds->dma->notify_opaque = notify_opaque; + return false; + } + + return true; +} + +static size_t +xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len) +{ + XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); + struct Stream *s = &ds->dma->streams[1]; + size_t ret; + + ret = stream_process_s2mem(s, buf, len); stream_update_irq(s); + return ret; } static uint64_t axidma_read(void *opaque, hwaddr addr, unsigned size) { - struct XilinxAXIDMA *d = opaque; + XilinxAXIDMA *d = opaque; struct Stream *s; uint32_t r = 0; int sid; @@ -401,7 +467,7 @@ static uint64_t axidma_read(void *opaque, hwaddr addr, static void axidma_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - struct XilinxAXIDMA *d = opaque; + XilinxAXIDMA *d = opaque; struct Stream *s; int sid; @@ -439,7 +505,7 @@ static void axidma_write(void *opaque, hwaddr addr, s->regs[addr] = value; s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */ if (!sid) { - stream_process_mem2s(s, d->tx_dev); + stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev); } break; default: @@ -448,6 +514,10 @@ static void axidma_write(void *opaque, hwaddr addr, s->regs[addr] = value; break; } + if (sid == 1 && d->notify) { + d->notify(d->notify_opaque); + d->notify = NULL; + } stream_update_irq(s); } @@ -457,58 +527,131 @@ static const MemoryRegionOps axidma_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int xilinx_axidma_init(SysBusDevice *dev) +static void xilinx_axidma_realize(DeviceState *dev, Error **errp) { - struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), dev); - int i; - - sysbus_init_irq(dev, &s->streams[0].irq); - sysbus_init_irq(dev, &s->streams[1].irq); + XilinxAXIDMA *s = XILINX_AXI_DMA(dev); + XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); + XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( + &s->rx_control_dev); + Error *local_errp = NULL; + + object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA, + (Object **)&ds->dma, &local_errp); + object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA, + (Object **)&cs->dma, &local_errp); + if (local_errp) { + goto xilinx_axidma_realize_fail; + } + object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_errp); + object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_errp); + if (local_errp) { + goto xilinx_axidma_realize_fail; + } - memory_region_init_io(&s->iomem, &axidma_ops, s, - "xlnx.axi-dma", R_MAX * 4 * 2); - sysbus_init_mmio(dev, &s->iomem); + int i; for (i = 0; i < 2; i++) { - stream_reset(&s->streams[i]); s->streams[i].nr = i; s->streams[i].bh = qemu_bh_new(timer_hit, &s->streams[i]); s->streams[i].ptimer = ptimer_init(s->streams[i].bh); ptimer_set_freq(s->streams[i].ptimer, s->freqhz); } - return 0; + return; + +xilinx_axidma_realize_fail: + if (!*errp) { + *errp = local_errp; + } } -static void xilinx_axidma_initfn(Object *obj) +static void xilinx_axidma_init(Object *obj) { - struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); + XilinxAXIDMA *s = XILINX_AXI_DMA(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + Error *errp = NULL; object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, - (Object **) &s->tx_dev, NULL); + (Object **) &s->tx_data_dev, &errp); + assert_no_error(errp); + object_property_add_link(obj, "axistream-control-connected", + TYPE_STREAM_SLAVE, + (Object **) &s->tx_control_dev, &errp); + assert_no_error(errp); + + object_initialize(&s->rx_data_dev, TYPE_XILINX_AXI_DMA_DATA_STREAM); + object_initialize(&s->rx_control_dev, TYPE_XILINX_AXI_DMA_CONTROL_STREAM); + object_property_add_child(OBJECT(s), "axistream-connected-target", + (Object *)&s->rx_data_dev, &errp); + assert_no_error(errp); + object_property_add_child(OBJECT(s), "axistream-control-connected-target", + (Object *)&s->rx_control_dev, &errp); + assert_no_error(errp); + + sysbus_init_irq(sbd, &s->streams[0].irq); + sysbus_init_irq(sbd, &s->streams[1].irq); + + memory_region_init_io(&s->iomem, &axidma_ops, s, + "xlnx.axi-dma", R_MAX * 4 * 2); + sysbus_init_mmio(sbd, &s->iomem); } static Property axidma_properties[] = { - DEFINE_PROP_UINT32("freqhz", struct XilinxAXIDMA, freqhz, 50000000), + DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000), DEFINE_PROP_END_OF_LIST(), }; static void axidma_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); - k->init = xilinx_axidma_init; + dc->realize = xilinx_axidma_realize, + dc->reset = xilinx_axidma_reset; dc->props = axidma_properties; - ssc->push = axidma_push; +} + +static StreamSlaveClass xilinx_axidma_data_stream_class = { + .push = xilinx_axidma_data_stream_push, + .can_push = xilinx_axidma_data_stream_can_push, +}; + +static StreamSlaveClass xilinx_axidma_control_stream_class = { + .push = xilinx_axidma_control_stream_push, +}; + +static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data) +{ + StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); + + ssc->push = ((StreamSlaveClass *)data)->push; + ssc->can_push = ((StreamSlaveClass *)data)->can_push; } static const TypeInfo axidma_info = { - .name = "xlnx.axi-dma", + .name = TYPE_XILINX_AXI_DMA, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(struct XilinxAXIDMA), + .instance_size = sizeof(XilinxAXIDMA), .class_init = axidma_class_init, - .instance_init = xilinx_axidma_initfn, + .instance_init = xilinx_axidma_init, +}; + +static const TypeInfo xilinx_axidma_data_stream_info = { + .name = TYPE_XILINX_AXI_DMA_DATA_STREAM, + .parent = TYPE_OBJECT, + .instance_size = sizeof(struct XilinxAXIDMAStreamSlave), + .class_init = xilinx_axidma_stream_class_init, + .class_data = &xilinx_axidma_data_stream_class, + .interfaces = (InterfaceInfo[]) { + { TYPE_STREAM_SLAVE }, + { } + } +}; + +static const TypeInfo xilinx_axidma_control_stream_info = { + .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM, + .parent = TYPE_OBJECT, + .instance_size = sizeof(struct XilinxAXIDMAStreamSlave), + .class_init = xilinx_axidma_stream_class_init, + .class_data = &xilinx_axidma_control_stream_class, .interfaces = (InterfaceInfo[]) { { TYPE_STREAM_SLAVE }, { } @@ -518,6 +661,8 @@ static const TypeInfo axidma_info = { static void xilinx_axidma_register_types(void) { type_register_static(&axidma_info); + type_register_static(&xilinx_axidma_data_stream_info); + type_register_static(&xilinx_axidma_control_stream_info); } type_init(xilinx_axidma_register_types) diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index ed9b448d07..3a10c0710c 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -60,6 +60,9 @@ typedef struct VAPICROMState { bool rom_mapped_writable; } VAPICROMState; +#define TYPE_VAPIC "kvmvapic" +#define VAPIC(obj) OBJECT_CHECK(VAPICROMState, (obj), TYPE_VAPIC) + #define TPR_INSTR_ABS_MODRM 0x1 #define TPR_INSTR_MATCH_MODRM_REG 0x2 @@ -690,7 +693,7 @@ static const MemoryRegionOps vapic_ops = { static int vapic_init(SysBusDevice *dev) { - VAPICROMState *s = FROM_SYSBUS(VAPICROMState, dev); + VAPICROMState *s = VAPIC(dev); memory_region_init_io(&s->io, &vapic_ops, s, "kvmvapic", 2); sysbus_add_io(dev, VAPIC_IO_PORT, &s->io); @@ -806,7 +809,7 @@ static void vapic_class_init(ObjectClass *klass, void *data) } static const TypeInfo vapic_type = { - .name = "kvmvapic", + .name = TYPE_VAPIC, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(VAPICROMState), .class_init = vapic_class_init, diff --git a/hw/intc/ioapic_common.c b/hw/intc/ioapic_common.c index 42c7adc691..5c5bb3caaa 100644 --- a/hw/intc/ioapic_common.c +++ b/hw/intc/ioapic_common.c @@ -59,7 +59,7 @@ static int ioapic_dispatch_post_load(void *opaque, int version_id) static int ioapic_init_common(SysBusDevice *dev) { - IOAPICCommonState *s = FROM_SYSBUS(IOAPICCommonState, dev); + IOAPICCommonState *s = IOAPIC_COMMON(dev); IOAPICCommonClass *info; static int ioapic_no; diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index ae7ff44423..334046808f 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -79,6 +79,7 @@ petalogix_ml605_init(QEMUMachineInitArgs *args) const char *cpu_model = args->cpu_model; MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev, *dma, *eth0; + Object *ds, *cs; MicroBlazeCPU *cpu; SysBusDevice *busdev; CPUMBState *env; @@ -134,14 +135,25 @@ petalogix_ml605_init(QEMUMachineInitArgs *args) dma = qdev_create(NULL, "xlnx.axi-dma"); /* FIXME: attach to the sysbus instead */ - object_property_add_child(container_get(qdev_get_machine(), "/unattached"), - "xilinx-dma", OBJECT(dma), NULL); - - xilinx_axiethernet_init(eth0, &nd_table[0], STREAM_SLAVE(dma), - 0x82780000, irq[3], 0x1000, 0x1000); - - xilinx_axidma_init(dma, STREAM_SLAVE(eth0), 0x84600000, irq[1], irq[0], - 100 * 1000000); + object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0), + NULL); + object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma), + NULL); + + ds = object_property_get_link(OBJECT(dma), + "axistream-connected-target", NULL); + cs = object_property_get_link(OBJECT(dma), + "axistream-control-connected-target", NULL); + xilinx_axiethernet_init(eth0, &nd_table[0], STREAM_SLAVE(ds), + STREAM_SLAVE(cs), 0x82780000, irq[3], 0x1000, + 0x1000); + + ds = object_property_get_link(OBJECT(eth0), + "axistream-connected-target", NULL); + cs = object_property_get_link(OBJECT(eth0), + "axistream-control-connected-target", NULL); + xilinx_axidma_init(dma, STREAM_SLAVE(ds), STREAM_SLAVE(cs), 0x84600000, + irq[1], irq[0], 100 * 1000000); { SSIBus *spi; diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 07c4badd98..8989e95297 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -32,12 +32,30 @@ #define DPHY(x) +#define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" +#define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" +#define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" + +#define XILINX_AXI_ENET(obj) \ + OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) + +#define XILINX_AXI_ENET_DATA_STREAM(obj) \ + OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ + TYPE_XILINX_AXI_ENET_DATA_STREAM) + +#define XILINX_AXI_ENET_CONTROL_STREAM(obj) \ + OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ + TYPE_XILINX_AXI_ENET_CONTROL_STREAM) + /* Advertisement control register. */ #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define CONTROL_PAYLOAD_WORDS 5 +#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) + struct PHY { uint32_t regs[32]; @@ -306,11 +324,23 @@ struct TEMAC { void *parent; }; +typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; +typedef struct XilinxAXIEnet XilinxAXIEnet; + +struct XilinxAXIEnetStreamSlave { + Object parent; + + struct XilinxAXIEnet *enet; +} ; + struct XilinxAXIEnet { SysBusDevice busdev; MemoryRegion iomem; qemu_irq irq; - StreamSlave *tx_dev; + StreamSlave *tx_data_dev; + StreamSlave *tx_control_dev; + XilinxAXIEnetStreamSlave rx_data_dev; + XilinxAXIEnetStreamSlave rx_control_dev; NICState *nic; NICConf conf; @@ -361,42 +391,50 @@ struct XilinxAXIEnet { /* 32K x 1 lookup filter. */ uint32_t ext_mtable[1024]; + uint32_t hdr[CONTROL_PAYLOAD_WORDS]; uint8_t *rxmem; + uint32_t rxsize; + uint32_t rxpos; + + uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; + uint32_t rxappsize; }; -static void axienet_rx_reset(struct XilinxAXIEnet *s) +static void axienet_rx_reset(XilinxAXIEnet *s) { s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; } -static void axienet_tx_reset(struct XilinxAXIEnet *s) +static void axienet_tx_reset(XilinxAXIEnet *s) { s->tc = TC_JUM | TC_TX | TC_VLAN; } -static inline int axienet_rx_resetting(struct XilinxAXIEnet *s) +static inline int axienet_rx_resetting(XilinxAXIEnet *s) { return s->rcw[1] & RCW1_RST; } -static inline int axienet_rx_enabled(struct XilinxAXIEnet *s) +static inline int axienet_rx_enabled(XilinxAXIEnet *s) { return s->rcw[1] & RCW1_RX; } -static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s) +static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) { return !!(s->regs[R_RAF] & RAF_EMCF_EN); } -static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s) +static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) { return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); } -static void axienet_reset(struct XilinxAXIEnet *s) +static void xilinx_axienet_reset(DeviceState *d) { + XilinxAXIEnet *s = XILINX_AXI_ENET(d); + axienet_rx_reset(s); axienet_tx_reset(s); @@ -406,7 +444,7 @@ static void axienet_reset(struct XilinxAXIEnet *s) s->emmc = EMMC_LINKSPEED_100MB; } -static void enet_update_irq(struct XilinxAXIEnet *s) +static void enet_update_irq(XilinxAXIEnet *s) { s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; qemu_set_irq(s->irq, !!s->regs[R_IP]); @@ -414,7 +452,7 @@ static void enet_update_irq(struct XilinxAXIEnet *s) static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) { - struct XilinxAXIEnet *s = opaque; + XilinxAXIEnet *s = opaque; uint32_t r = 0; addr >>= 2; @@ -506,7 +544,7 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) static void enet_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - struct XilinxAXIEnet *s = opaque; + XilinxAXIEnet *s = opaque; struct TEMAC *t = &s->TEMAC; addr >>= 2; @@ -620,10 +658,10 @@ static const MemoryRegionOps enet_ops = { static int eth_can_rx(NetClientState *nc) { - struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc); + XilinxAXIEnet *s = qemu_get_nic_opaque(nc); /* RX enabled? */ - return !axienet_rx_resetting(s) && axienet_rx_enabled(s); + return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); } static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) @@ -641,13 +679,38 @@ static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) return match; } +static void axienet_eth_rx_notify(void *opaque) +{ + XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); + + while (s->rxappsize && stream_can_push(s->tx_control_dev, + axienet_eth_rx_notify, s)) { + size_t ret = stream_push(s->tx_control_dev, + (void *)s->rxapp + CONTROL_PAYLOAD_SIZE + - s->rxappsize, s->rxappsize); + s->rxappsize -= ret; + } + + while (s->rxsize && stream_can_push(s->tx_data_dev, + axienet_eth_rx_notify, s)) { + size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, + s->rxsize); + s->rxsize -= ret; + s->rxpos += ret; + if (!s->rxsize) { + s->regs[R_IS] |= IS_RX_COMPLETE; + } + } + enet_update_irq(s); +} + static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) { - struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc); + XilinxAXIEnet *s = qemu_get_nic_opaque(nc); static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; - uint32_t app[6] = {0}; + uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; int promisc = s->fmi & (1 << 31); int unicast, broadcast, multicast, ip_multicast = 0; uint32_t csum32; @@ -778,9 +841,15 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) /* Good frame. */ app[2] |= 1 << 6; - stream_push(s->tx_dev, (void *)s->rxmem, size, app); + s->rxsize = size; + s->rxpos = 0; + for (i = 0; i < ARRAY_SIZE(app); ++i) { + app[i] = cpu_to_le32(app[i]); + } + s->rxappsize = CONTROL_PAYLOAD_SIZE; + memcpy(s->rxapp, app, s->rxappsize); + axienet_eth_rx_notify(s); - s->regs[R_IS] |= IS_RX_COMPLETE; enet_update_irq(s); return size; } @@ -788,38 +857,59 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) static void eth_cleanup(NetClientState *nc) { /* FIXME. */ - struct XilinxAXIEnet *s = qemu_get_nic_opaque(nc); + XilinxAXIEnet *s = qemu_get_nic_opaque(nc); g_free(s->rxmem); g_free(s); } -static void -axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr) +static size_t +xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) { - struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); + int i; + XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); + XilinxAXIEnet *s = cs->enet; + + if (len != CONTROL_PAYLOAD_SIZE) { + hw_error("AXI Enet requires %d byte control stream payload\n", + (int)CONTROL_PAYLOAD_SIZE); + } + + memcpy(s->hdr, buf, len); + + for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { + s->hdr[i] = le32_to_cpu(s->hdr[i]); + } + return len; +} + +static size_t +xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) +{ + XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); + XilinxAXIEnet *s = ds->enet; /* TX enable ? */ if (!(s->tc & TC_TX)) { - return; + return size; } /* Jumbo or vlan sizes ? */ if (!(s->tc & TC_JUM)) { if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { - return; + return size; } } - if (hdr[0] & 1) { - unsigned int start_off = hdr[1] >> 16; - unsigned int write_off = hdr[1] & 0xffff; + if (s->hdr[0] & 1) { + unsigned int start_off = s->hdr[1] >> 16; + unsigned int write_off = s->hdr[1] & 0xffff; uint32_t tmp_csum; uint16_t csum; tmp_csum = net_checksum_add(size - start_off, (uint8_t *)buf + start_off); /* Accumulate the seed. */ - tmp_csum += hdr[2] & 0xffff; + tmp_csum += s->hdr[2] & 0xffff; /* Fold the 32bit partial checksum. */ csum = net_checksum_finish(tmp_csum); @@ -834,6 +924,8 @@ axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr) s->stats.tx_bytes += size; s->regs[R_IS] |= IS_TX_COMPLETE; enet_update_irq(s); + + return size; } static NetClientInfo net_xilinx_enet_info = { @@ -844,18 +936,30 @@ static NetClientInfo net_xilinx_enet_info = { .cleanup = eth_cleanup, }; -static int xilinx_enet_init(SysBusDevice *dev) +static void xilinx_enet_realize(DeviceState *dev, Error **errp) { - struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev); - - sysbus_init_irq(dev, &s->irq); - - memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000); - sysbus_init_mmio(dev, &s->iomem); + XilinxAXIEnet *s = XILINX_AXI_ENET(dev); + XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); + XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( + &s->rx_control_dev); + Error *local_errp = NULL; + + object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", + (Object **) &ds->enet, &local_errp); + object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", + (Object **) &cs->enet, &local_errp); + if (local_errp) { + goto xilinx_enet_realize_fail; + } + object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_errp); + object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_errp); + if (local_errp) { + goto xilinx_enet_realize_fail; + } qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, - object_get_typename(OBJECT(dev)), dev->qdev.id, s); + object_get_typename(OBJECT(dev)), dev->id, s); qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); tdk_init(&s->TEMAC.phy); @@ -864,46 +968,93 @@ static int xilinx_enet_init(SysBusDevice *dev) s->TEMAC.parent = s; s->rxmem = g_malloc(s->c_rxmem); - axienet_reset(s); + return; - return 0; +xilinx_enet_realize_fail: + if (!*errp) { + *errp = local_errp; + } } -static void xilinx_enet_initfn(Object *obj) +static void xilinx_enet_init(Object *obj) { - struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); + XilinxAXIEnet *s = XILINX_AXI_ENET(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); Error *errp = NULL; object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, - (Object **) &s->tx_dev, &errp); + (Object **) &s->tx_data_dev, &errp); assert_no_error(errp); + object_property_add_link(obj, "axistream-control-connected", + TYPE_STREAM_SLAVE, + (Object **) &s->tx_control_dev, &errp); + assert_no_error(errp); + + object_initialize(&s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM); + object_initialize(&s->rx_control_dev, TYPE_XILINX_AXI_ENET_CONTROL_STREAM); + object_property_add_child(OBJECT(s), "axistream-connected-target", + (Object *)&s->rx_data_dev, &errp); + assert_no_error(errp); + object_property_add_child(OBJECT(s), "axistream-control-connected-target", + (Object *)&s->rx_control_dev, &errp); + assert_no_error(errp); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000); + sysbus_init_mmio(sbd, &s->iomem); } static Property xilinx_enet_properties[] = { - DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7), - DEFINE_PROP_UINT32("rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000), - DEFINE_PROP_UINT32("txmem", struct XilinxAXIEnet, c_txmem, 0x1000), - DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf), + DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), + DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), + DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), + DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), DEFINE_PROP_END_OF_LIST(), }; static void xilinx_enet_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); - k->init = xilinx_enet_init; + dc->realize = xilinx_enet_realize; dc->props = xilinx_enet_properties; - ssc->push = axienet_stream_push; + dc->reset = xilinx_axienet_reset; +} + +static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data) +{ + StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); + + ssc->push = data; } static const TypeInfo xilinx_enet_info = { - .name = "xlnx.axi-ethernet", + .name = TYPE_XILINX_AXI_ENET, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(struct XilinxAXIEnet), + .instance_size = sizeof(XilinxAXIEnet), .class_init = xilinx_enet_class_init, - .instance_init = xilinx_enet_initfn, + .instance_init = xilinx_enet_init, +}; + +static const TypeInfo xilinx_enet_data_stream_info = { + .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, + .parent = TYPE_OBJECT, + .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), + .class_init = xilinx_enet_stream_class_init, + .class_data = xilinx_axienet_data_stream_push, + .interfaces = (InterfaceInfo[]) { + { TYPE_STREAM_SLAVE }, + { } + } +}; + +static const TypeInfo xilinx_enet_control_stream_info = { + .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, + .parent = TYPE_OBJECT, + .instance_size = sizeof(struct XilinxAXIEnetStreamSlave), + .class_init = xilinx_enet_stream_class_init, + .class_data = xilinx_axienet_control_stream_push, .interfaces = (InterfaceInfo[]) { { TYPE_STREAM_SLAVE }, { } @@ -913,6 +1064,8 @@ static const TypeInfo xilinx_enet_info = { static void xilinx_enet_register_types(void) { type_register_static(&xilinx_enet_info); + type_register_static(&xilinx_enet_data_stream_info); + type_register_static(&xilinx_enet_control_stream_info); } type_init(xilinx_enet_register_types) diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index 7c8fc364c8..f8d32bc04e 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -78,6 +78,8 @@ static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size) memory_region_add_subregion(get_system_memory(), 0, ram_memory); } +static const GraphicHwOps no_ops; + static void puv3_load_kernel(const char *kernel_filename) { int size; @@ -92,7 +94,7 @@ static void puv3_load_kernel(const char *kernel_filename) } /* cheat curses that we have a graphic console, only under ocd console */ - graphic_console_init(NULL, NULL, NULL, NULL, NULL); + graphic_console_init(&no_ops, NULL); } static void puv3_init(QEMUMachineInitArgs *args) |