diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/apb_pci.c | 16 | ||||
| -rw-r--r-- | hw/cs4231.c | 6 | ||||
| -rw-r--r-- | hw/esp.c | 158 | ||||
| -rw-r--r-- | hw/iommu.c | 100 | ||||
| -rw-r--r-- | hw/slavio_intctl.c | 66 | ||||
| -rw-r--r-- | hw/slavio_misc.c | 106 | ||||
| -rw-r--r-- | hw/slavio_serial.c | 194 | ||||
| -rw-r--r-- | hw/slavio_timer.c | 68 | ||||
| -rw-r--r-- | hw/sun4m.c | 44 | ||||
| -rw-r--r-- | hw/sun4u.c | 46 | ||||
| -rw-r--r-- | hw/tcx.c | 112 |
11 files changed, 458 insertions, 458 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c index 1de3353843..fe9189247e 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -70,7 +70,7 @@ static CPUReadMemoryFunc *pci_apb_config_read[] = { }; static void apb_config_writel (void *opaque, target_phys_addr_t addr, - uint32_t val) + uint32_t val) { //PCIBus *s = opaque; @@ -80,14 +80,14 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr, case 0x18: // AFAR case 0x20: // Diagnostic case 0x28: // Target address space - // XXX + // XXX default: - break; + break; } } static uint32_t apb_config_readl (void *opaque, - target_phys_addr_t addr) + target_phys_addr_t addr) { //PCIBus *s = opaque; uint32_t val; @@ -98,10 +98,10 @@ static uint32_t apb_config_readl (void *opaque, case 0x18: // AFAR case 0x20: // Diagnostic case 0x28: // Target address space - // XXX + // XXX default: - val = 0; - break; + val = 0; + break; } return val; } @@ -222,7 +222,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read, pci_apb_config_write, s); apb_config = cpu_register_io_memory(0, apb_config_read, - apb_config_write, s); + apb_config_write, s); pci_mem_data = cpu_register_io_memory(0, pci_apb_read, pci_apb_write, s); pci_ioport = cpu_register_io_memory(0, pci_apb_ioread, diff --git a/hw/cs4231.c b/hw/cs4231.c index 390ef746f6..9829800388 100644 --- a/hw/cs4231.c +++ b/hw/cs4231.c @@ -79,11 +79,11 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) break; } DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret); - break; + break; default: ret = s->regs[saddr]; DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret); - break; + break; } return ret; } @@ -122,7 +122,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) break; default: s->regs[saddr] = val; - break; + break; } } @@ -107,9 +107,9 @@ static int get_cmd(ESPState *s, uint8_t *buf) if (s->dma) { espdma_memory_read(s->dma_opaque, buf, dmalen); } else { - buf[0] = 0; - memcpy(&buf[1], s->ti_buf, dmalen); - dmalen++; + buf[0] = 0; + memcpy(&buf[1], s->ti_buf, dmalen); + dmalen++; } s->ti_size = 0; @@ -124,11 +124,11 @@ static int get_cmd(ESPState *s, uint8_t *buf) if (target >= MAX_DISKS || !s->scsi_dev[target]) { // No such drive - s->rregs[4] = STAT_IN; - s->rregs[5] = INTR_DC; - s->rregs[6] = SEQ_0; - qemu_irq_raise(s->irq); - return 0; + s->rregs[4] = STAT_IN; + s->rregs[5] = INTR_DC; + s->rregs[6] = SEQ_0; + qemu_irq_raise(s->irq); + return 0; } s->current_dev = s->scsi_dev[target]; return dmalen; @@ -190,14 +190,14 @@ static void write_response(ESPState *s) s->ti_buf[1] = 0; if (s->dma) { espdma_memory_write(s->dma_opaque, s->ti_buf, 2); - s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; - s->rregs[5] = INTR_BS | INTR_FC; - s->rregs[6] = SEQ_CD; + s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; + s->rregs[5] = INTR_BS | INTR_FC; + s->rregs[6] = SEQ_CD; } else { - s->ti_size = 2; - s->ti_rptr = 0; - s->ti_wptr = 0; - s->rregs[7] = 2; + s->ti_size = 2; + s->ti_rptr = 0; + s->ti_wptr = 0; + s->rregs[7] = 2; } qemu_irq_raise(s->irq); } @@ -359,9 +359,9 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); switch (saddr) { case 2: - // FIFO - if (s->ti_size > 0) { - s->ti_size--; + // FIFO + if (s->ti_size > 0) { + s->ti_size--; if ((s->rregs[4] & 6) == 0) { /* Data in/out. */ fprintf(stderr, "esp: PIO data read not implemented\n"); @@ -370,20 +370,20 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) s->rregs[2] = s->ti_buf[s->ti_rptr++]; } qemu_irq_raise(s->irq); - } - if (s->ti_size == 0) { + } + if (s->ti_size == 0) { s->ti_rptr = 0; s->ti_wptr = 0; } - break; + break; case 5: // interrupt // Clear interrupt/error status bits s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE); - qemu_irq_lower(s->irq); + qemu_irq_lower(s->irq); break; default: - break; + break; } return s->rregs[saddr]; } @@ -401,7 +401,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) s->rregs[4] &= ~STAT_TC; break; case 2: - // FIFO + // FIFO if (s->do_cmd) { s->cmdbuf[s->cmdlen++] = val & 0xff; } else if ((s->rregs[4] & 6) == 0) { @@ -413,73 +413,73 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) s->ti_size++; s->ti_buf[s->ti_wptr++] = val & 0xff; } - break; + break; case 3: s->rregs[saddr] = val; - // Command - if (val & 0x80) { - s->dma = 1; + // Command + if (val & 0x80) { + s->dma = 1; /* Reload DMA counter. */ s->rregs[0] = s->wregs[0]; s->rregs[1] = s->wregs[1]; - } else { - s->dma = 0; - } - switch(val & 0x7f) { - case 0: - DPRINTF("NOP (%2.2x)\n", val); - break; - case 1: - DPRINTF("Flush FIFO (%2.2x)\n", val); + } else { + s->dma = 0; + } + switch(val & 0x7f) { + case 0: + DPRINTF("NOP (%2.2x)\n", val); + break; + case 1: + DPRINTF("Flush FIFO (%2.2x)\n", val); //s->ti_size = 0; - s->rregs[5] = INTR_FC; - s->rregs[6] = 0; - break; - case 2: - DPRINTF("Chip reset (%2.2x)\n", val); - esp_reset(s); - break; - case 3: - DPRINTF("Bus reset (%2.2x)\n", val); - s->rregs[5] = INTR_RST; + s->rregs[5] = INTR_FC; + s->rregs[6] = 0; + break; + case 2: + DPRINTF("Chip reset (%2.2x)\n", val); + esp_reset(s); + break; + case 3: + DPRINTF("Bus reset (%2.2x)\n", val); + s->rregs[5] = INTR_RST; if (!(s->wregs[8] & 0x40)) { qemu_irq_raise(s->irq); } - break; - case 0x10: - handle_ti(s); - break; - case 0x11: - DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); - write_response(s); - break; - case 0x12: - DPRINTF("Message Accepted (%2.2x)\n", val); - write_response(s); - s->rregs[5] = INTR_DC; - s->rregs[6] = 0; - break; - case 0x1a: - DPRINTF("Set ATN (%2.2x)\n", val); - break; - case 0x42: - DPRINTF("Set ATN (%2.2x)\n", val); - handle_satn(s); - break; - case 0x43: - DPRINTF("Set ATN & stop (%2.2x)\n", val); - handle_satn_stop(s); - break; + break; + case 0x10: + handle_ti(s); + break; + case 0x11: + DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); + write_response(s); + break; + case 0x12: + DPRINTF("Message Accepted (%2.2x)\n", val); + write_response(s); + s->rregs[5] = INTR_DC; + s->rregs[6] = 0; + break; + case 0x1a: + DPRINTF("Set ATN (%2.2x)\n", val); + break; + case 0x42: + DPRINTF("Set ATN (%2.2x)\n", val); + handle_satn(s); + break; + case 0x43: + DPRINTF("Set ATN & stop (%2.2x)\n", val); + handle_satn_stop(s); + break; case 0x44: DPRINTF("Enable selection (%2.2x)\n", val); break; - default: - DPRINTF("Unhandled ESP command (%2.2x)\n", val); - break; - } - break; + default: + DPRINTF("Unhandled ESP command (%2.2x)\n", val); + break; + } + break; case 4 ... 7: - break; + break; case 8: s->rregs[saddr] = val; break; @@ -492,7 +492,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) s->rregs[saddr] = val; break; default: - break; + break; } s->wregs[saddr] = val; } diff --git a/hw/iommu.c b/hw/iommu.c index 0ee8c718ea..55d39b9fd7 100644 --- a/hw/iommu.c +++ b/hw/iommu.c @@ -81,7 +81,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0) #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses - produced by this device as pure + produced by this device as pure physical. */ #define IOMMU_SBCFG_MASK 0x00010003 @@ -98,7 +98,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0) #define PAGE_SHIFT 12 #define PAGE_SIZE (1 << PAGE_SHIFT) -#define PAGE_MASK (PAGE_SIZE - 1) +#define PAGE_MASK (PAGE_SIZE - 1) typedef struct IOMMUState { target_phys_addr_t addr; @@ -114,9 +114,9 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) saddr = (addr - s->addr) >> 2; switch (saddr) { default: - DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]); - return s->regs[saddr]; - break; + DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]); + return s->regs[saddr]; + break; } return 0; } @@ -130,61 +130,61 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val DPRINTF("write reg[%d] = %x\n", (int)saddr, val); switch (saddr) { case IOMMU_CTRL: - switch (val & IOMMU_CTRL_RNGE) { - case IOMMU_RNGE_16MB: - s->iostart = 0xffffffffff000000ULL; - break; - case IOMMU_RNGE_32MB: - s->iostart = 0xfffffffffe000000ULL; - break; - case IOMMU_RNGE_64MB: - s->iostart = 0xfffffffffc000000ULL; - break; - case IOMMU_RNGE_128MB: - s->iostart = 0xfffffffff8000000ULL; - break; - case IOMMU_RNGE_256MB: - s->iostart = 0xfffffffff0000000ULL; - break; - case IOMMU_RNGE_512MB: - s->iostart = 0xffffffffe0000000ULL; - break; - case IOMMU_RNGE_1GB: - s->iostart = 0xffffffffc0000000ULL; - break; - default: - case IOMMU_RNGE_2GB: - s->iostart = 0xffffffff80000000ULL; - break; - } - DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); - s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); - break; + switch (val & IOMMU_CTRL_RNGE) { + case IOMMU_RNGE_16MB: + s->iostart = 0xffffffffff000000ULL; + break; + case IOMMU_RNGE_32MB: + s->iostart = 0xfffffffffe000000ULL; + break; + case IOMMU_RNGE_64MB: + s->iostart = 0xfffffffffc000000ULL; + break; + case IOMMU_RNGE_128MB: + s->iostart = 0xfffffffff8000000ULL; + break; + case IOMMU_RNGE_256MB: + s->iostart = 0xfffffffff0000000ULL; + break; + case IOMMU_RNGE_512MB: + s->iostart = 0xffffffffe0000000ULL; + break; + case IOMMU_RNGE_1GB: + s->iostart = 0xffffffffc0000000ULL; + break; + default: + case IOMMU_RNGE_2GB: + s->iostart = 0xffffffff80000000ULL; + break; + } + DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); + s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); + break; case IOMMU_BASE: - s->regs[saddr] = val & IOMMU_BASE_MASK; - break; + s->regs[saddr] = val & IOMMU_BASE_MASK; + break; case IOMMU_TLBFLUSH: - DPRINTF("tlb flush %x\n", val); - s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; - break; + DPRINTF("tlb flush %x\n", val); + s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; + break; case IOMMU_PGFLUSH: - DPRINTF("page flush %x\n", val); - s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; - break; + DPRINTF("page flush %x\n", val); + s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; + break; case IOMMU_SBCFG0: case IOMMU_SBCFG1: case IOMMU_SBCFG2: case IOMMU_SBCFG3: - s->regs[saddr] = val & IOMMU_SBCFG_MASK; - break; + s->regs[saddr] = val & IOMMU_SBCFG_MASK; + break; case IOMMU_ARBEN: // XXX implement SBus probing: fault when reading unmapped // addresses, fault cause and address stored to MMU/IOMMU - s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; - break; + s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; + break; default: - s->regs[saddr] = val; - break; + s->regs[saddr] = val; + break; } } @@ -283,7 +283,7 @@ static void iommu_save(QEMUFile *f, void *opaque) int i; for (i = 0; i < IOMMU_NREGS; i++) - qemu_put_be32s(f, &s->regs[i]); + qemu_put_be32s(f, &s->regs[i]); qemu_put_be64s(f, &s->iostart); } diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index f604702f88..5412228770 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -100,21 +100,21 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); switch (saddr) { case 1: // clear pending softints - if (val & 0x4000) - val |= 80000000; - val &= 0xfffe0000; - s->intreg_pending[cpu] &= ~val; + if (val & 0x4000) + val |= 80000000; + val &= 0xfffe0000; + s->intreg_pending[cpu] &= ~val; slavio_check_interrupts(s); - DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); - break; + DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); + break; case 2: // set softint - val &= 0xfffe0000; - s->intreg_pending[cpu] |= val; + val &= 0xfffe0000; + s->intreg_pending[cpu] |= val; slavio_check_interrupts(s); - DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); - break; + DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); + break; default: - break; + break; } } @@ -165,27 +165,27 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); switch (saddr) { case 2: // clear (enable) - // Force clear unused bits - val &= ~0x4fb2007f; - s->intregm_disabled &= ~val; - DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); - slavio_check_interrupts(s); - break; + // Force clear unused bits + val &= ~0x4fb2007f; + s->intregm_disabled &= ~val; + DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); + slavio_check_interrupts(s); + break; case 3: // set (disable, clear pending) - // Force clear unused bits - val &= ~0x4fb2007f; - s->intregm_disabled |= val; - s->intregm_pending &= ~val; + // Force clear unused bits + val &= ~0x4fb2007f; + s->intregm_disabled |= val; + s->intregm_pending &= ~val; slavio_check_interrupts(s); - DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); - break; + DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); + break; case 4: - s->target_cpu = val & (MAX_CPUS - 1); + s->target_cpu = val & (MAX_CPUS - 1); slavio_check_interrupts(s); - DPRINTF("Set master irq cpu %d\n", s->target_cpu); - break; + DPRINTF("Set master irq cpu %d\n", s->target_cpu); + break; default: - break; + break; } } @@ -207,7 +207,7 @@ void slavio_pic_info(void *opaque) int i; for (i = 0; i < MAX_CPUS; i++) { - term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); + term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); } term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled); } @@ -310,7 +310,7 @@ static void slavio_intctl_save(QEMUFile *f, void *opaque) int i; for (i = 0; i < MAX_CPUS; i++) { - qemu_put_be32s(f, &s->intreg_pending[i]); + qemu_put_be32s(f, &s->intreg_pending[i]); } qemu_put_be32s(f, &s->intregm_pending); qemu_put_be32s(f, &s->intregm_disabled); @@ -326,7 +326,7 @@ static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id) return -EINVAL; for (i = 0; i < MAX_CPUS; i++) { - qemu_get_be32s(f, &s->intreg_pending[i]); + qemu_get_be32s(f, &s->intreg_pending[i]); } qemu_get_be32s(f, &s->intregm_pending); qemu_get_be32s(f, &s->intregm_disabled); @@ -341,7 +341,7 @@ static void slavio_intctl_reset(void *opaque) int i; for (i = 0; i < MAX_CPUS; i++) { - s->intreg_pending[i] = 0; + s->intreg_pending[i] = 0; } s->intregm_disabled = ~0xffb2007f; s->intregm_pending = 0; @@ -363,8 +363,8 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, s->intbit_to_level = intbit_to_level; for (i = 0; i < MAX_CPUS; i++) { - slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); - cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, + slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); + cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, slavio_intctl_io_memory); s->cpu_irqs[i] = parent_irq[i]; } diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c index 34072c6238..1a2c11a15f 100644 --- a/hw/slavio_misc.c +++ b/hw/slavio_misc.c @@ -76,9 +76,9 @@ void slavio_set_power_fail(void *opaque, int power_failing) MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config); if (power_failing && (s->config & 0x8)) { - s->aux2 |= 0x4; + s->aux2 |= 0x4; } else { - s->aux2 &= ~0x4; + s->aux2 &= ~0x4; } slavio_misc_update_irq(s); } @@ -89,44 +89,44 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32 switch (addr & 0xfff0000) { case 0x1800000: - MISC_DPRINTF("Write config %2.2x\n", val & 0xff); - s->config = val & 0xff; - slavio_misc_update_irq(s); - break; + MISC_DPRINTF("Write config %2.2x\n", val & 0xff); + s->config = val & 0xff; + slavio_misc_update_irq(s); + break; case 0x1900000: - MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); - s->aux1 = val & 0xff; - break; + MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); + s->aux1 = val & 0xff; + break; case 0x1910000: - val &= 0x3; - MISC_DPRINTF("Write aux2 %2.2x\n", val); - val |= s->aux2 & 0x4; - if (val & 0x2) // Clear Power Fail int - val &= 0x1; - s->aux2 = val; - if (val & 1) - qemu_system_shutdown_request(); - slavio_misc_update_irq(s); - break; + val &= 0x3; + MISC_DPRINTF("Write aux2 %2.2x\n", val); + val |= s->aux2 & 0x4; + if (val & 0x2) // Clear Power Fail int + val &= 0x1; + s->aux2 = val; + if (val & 1) + qemu_system_shutdown_request(); + slavio_misc_update_irq(s); + break; case 0x1a00000: - MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); - s->diag = val & 0xff; - break; + MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); + s->diag = val & 0xff; + break; case 0x1b00000: - MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); - s->mctrl = val & 0xff; - break; + MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); + s->mctrl = val & 0xff; + break; case 0x1f00000: - MISC_DPRINTF("Write system control %2.2x\n", val & 0xff); - if (val & 1) { - s->sysctrl = 0x2; - qemu_system_reset_request(); - } - break; + MISC_DPRINTF("Write system control %2.2x\n", val & 0xff); + if (val & 1) { + s->sysctrl = 0x2; + qemu_system_reset_request(); + } + break; case 0xa000000: - MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); + MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); - break; + break; } } @@ -137,32 +137,32 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) switch (addr & 0xfff0000) { case 0x1800000: - ret = s->config; - MISC_DPRINTF("Read config %2.2x\n", ret); - break; + ret = s->config; + MISC_DPRINTF("Read config %2.2x\n", ret); + break; case 0x1900000: - ret = s->aux1; - MISC_DPRINTF("Read aux1 %2.2x\n", ret); - break; + ret = s->aux1; + MISC_DPRINTF("Read aux1 %2.2x\n", ret); + break; case 0x1910000: - ret = s->aux2; - MISC_DPRINTF("Read aux2 %2.2x\n", ret); - break; + ret = s->aux2; + MISC_DPRINTF("Read aux2 %2.2x\n", ret); + break; case 0x1a00000: - ret = s->diag; - MISC_DPRINTF("Read diag %2.2x\n", ret); - break; + ret = s->diag; + MISC_DPRINTF("Read diag %2.2x\n", ret); + break; case 0x1b00000: - ret = s->mctrl; - MISC_DPRINTF("Read modem control %2.2x\n", ret); - break; + ret = s->mctrl; + MISC_DPRINTF("Read modem control %2.2x\n", ret); + break; case 0x1f00000: - MISC_DPRINTF("Read system control %2.2x\n", ret); - ret = s->sysctrl; - break; + MISC_DPRINTF("Read system control %2.2x\n", ret); + ret = s->sysctrl; + break; case 0xa000000: - MISC_DPRINTF("Read power management %2.2x\n", ret); - break; + MISC_DPRINTF("Read power management %2.2x\n", ret); + break; } return ret; } diff --git a/hw/slavio_serial.c b/hw/slavio_serial.c index 1aa5e7a174..2eb3379b49 100644 --- a/hw/slavio_serial.c +++ b/hw/slavio_serial.c @@ -139,7 +139,7 @@ static uint32_t get_queue(void *opaque) int val; if (q->count == 0) { - return 0; + return 0; } else { val = q->data[q->rptr]; if (++q->rptr == SERIO_QUEUE_SIZE) @@ -148,17 +148,17 @@ static uint32_t get_queue(void *opaque) } SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val); if (q->count > 0) - serial_receive_byte(s, 0); + serial_receive_byte(s, 0); return val; } static int slavio_serial_update_irq_chn(ChannelState *s) { if ((s->wregs[1] & 1) && // interrupts enabled - (((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending - ((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) && - s->rxint == 1) || // rx ints enabled, pending - ((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p + (((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending + ((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) && + s->rxint == 1) || // rx ints enabled, pending + ((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p return 1; } return 0; @@ -181,8 +181,8 @@ static void slavio_serial_reset_chn(ChannelState *s) s->reg = 0; for (i = 0; i < SERIAL_SIZE; i++) { - s->rregs[i] = 0; - s->wregs[i] = 0; + s->rregs[i] = 0; + s->wregs[i] = 0; } s->wregs[4] = 4; s->wregs[9] = 0xc0; @@ -367,82 +367,82 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint s = &serial->chn[channel]; switch (saddr) { case 0: - SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff); - newreg = 0; - switch (s->reg) { - case 0: - newreg = val & 7; - val &= 0x38; - switch (val) { - case 8: - newreg |= 0x8; - break; - case 0x28: + SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff); + newreg = 0; + switch (s->reg) { + case 0: + newreg = val & 7; + val &= 0x38; + switch (val) { + case 8: + newreg |= 0x8; + break; + case 0x28: clr_txint(s); - break; - case 0x38: + break; + case 0x38: if (s->rxint_under_svc) clr_rxint(s); else if (s->txint_under_svc) clr_txint(s); - break; - default: - break; - } - break; + break; + default: + break; + } + break; case 1 ... 3: case 6 ... 8: case 10 ... 11: case 14 ... 15: - s->wregs[s->reg] = val; - break; + s->wregs[s->reg] = val; + break; case 4: case 5: case 12: case 13: - s->wregs[s->reg] = val; + s->wregs[s->reg] = val; slavio_serial_update_parameters(s); - break; - case 9: - switch (val & 0xc0) { - case 0: - default: - break; - case 0x40: - slavio_serial_reset_chn(&serial->chn[1]); - return; - case 0x80: - slavio_serial_reset_chn(&serial->chn[0]); - return; - case 0xc0: - slavio_serial_reset(serial); - return; - } - break; - default: - break; - } - if (s->reg == 0) - s->reg = newreg; - else - s->reg = 0; - break; + break; + case 9: + switch (val & 0xc0) { + case 0: + default: + break; + case 0x40: + slavio_serial_reset_chn(&serial->chn[1]); + return; + case 0x80: + slavio_serial_reset_chn(&serial->chn[0]); + return; + case 0xc0: + slavio_serial_reset(serial); + return; + } + break; + default: + break; + } + if (s->reg == 0) + s->reg = newreg; + else + s->reg = 0; + break; case 1: - SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val); + SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val); s->tx = val; - if (s->wregs[5] & 8) { // tx enabled - if (s->chr) - qemu_chr_write(s->chr, &s->tx, 1); - else if (s->type == kbd) { - handle_kbd_command(s, val); - } - } + if (s->wregs[5] & 8) { // tx enabled + if (s->chr) + qemu_chr_write(s->chr, &s->tx, 1); + else if (s->type == kbd) { + handle_kbd_command(s, val); + } + } s->rregs[0] |= 4; // Tx buffer empty s->rregs[1] |= 1; // All sent set_txint(s); - break; + break; default: - break; + break; } } @@ -459,21 +459,21 @@ static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr) s = &serial->chn[channel]; switch (saddr) { case 0: - SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]); - ret = s->rregs[s->reg]; - s->reg = 0; - return ret; + SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]); + ret = s->rregs[s->reg]; + s->reg = 0; + return ret; case 1: - s->rregs[0] &= ~1; + s->rregs[0] &= ~1; clr_rxint(s); - if (s->type == kbd || s->type == mouse) - ret = get_queue(s); - else - ret = s->rx; - SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret); - return ret; + if (s->type == kbd || s->type == mouse) + ret = get_queue(s); + else + ret = s->rx; + SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret); + return ret; default: - break; + break; } return 0; } @@ -484,10 +484,10 @@ static int serial_can_receive(void *opaque) int ret; if (((s->wregs[3] & 1) == 0) // Rx not enabled - || ((s->rregs[0] & 1) == 1)) // char already available - ret = 0; + || ((s->rregs[0] & 1) == 1)) // char already available + ret = 0; else - ret = 1; + ret = 1; //SER_DPRINTF("channel %c can receive %d\n", CHN_C(s), ret); return ret; } @@ -584,7 +584,7 @@ static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id) ret = slavio_serial_load_chn(f, &s->chn[0], version_id); if (ret != 0) - return ret; + return ret; ret = slavio_serial_load_chn(f, &s->chn[1], version_id); return ret; @@ -607,13 +607,13 @@ SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, s->chn[1].chr = chr2; for (i = 0; i < 2; i++) { - s->chn[i].irq = irq; - s->chn[i].chn = 1 - i; - s->chn[i].type = ser; - if (s->chn[i].chr) { - qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, + s->chn[i].irq = irq; + s->chn[i].chn = 1 - i; + s->chn[i].type = ser; + if (s->chn[i].chr) { + qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, serial_receive1, serial_event, &s->chn[i]); - } + } } s->chn[0].otherchn = &s->chn[1]; s->chn[1].otherchn = &s->chn[0]; @@ -698,21 +698,21 @@ static void handle_kbd_command(ChannelState *s, int val) switch (val) { case 1: // Reset, return type code clear_queue(s); - put_queue(s, 0xff); - put_queue(s, 4); // Type 4 - put_queue(s, 0x7f); - break; + put_queue(s, 0xff); + put_queue(s, 4); // Type 4 + put_queue(s, 0x7f); + break; case 0xe: // Set leds s->led_mode = 1; break; case 7: // Query layout case 0xf: clear_queue(s); - put_queue(s, 0xfe); - put_queue(s, 0); // XXX, layout? - break; + put_queue(s, 0xfe); + put_queue(s, 0); // XXX, layout? + break; default: - break; + break; } } @@ -768,9 +768,9 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq) if (!s) return; for (i = 0; i < 2; i++) { - s->chn[i].irq = irq; - s->chn[i].chn = 1 - i; - s->chn[i].chr = NULL; + s->chn[i].irq = irq; + s->chn[i].chn = 1 - i; + s->chn[i].chr = NULL; } s->chn[0].otherchn = &s->chn[1]; s->chn[1].otherchn = &s->chn[0]; diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c index 80fe15a6c7..fa4b95b3fd 100644 --- a/hw/slavio_timer.c +++ b/hw/slavio_timer.c @@ -86,7 +86,7 @@ static void slavio_timer_irq(void *opaque) DPRINTF("callback: count %x%08x\n", s->counthigh, s->count); s->reached = 0x80000000; if (s->mode != 1) - qemu_irq_raise(s->irq); + qemu_irq_raise(s->irq); } static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) @@ -97,34 +97,34 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) saddr = (addr & TIMER_MAXADDR) >> 2; switch (saddr) { case 0: - // read limit (system counter mode) or read most signifying - // part of counter (user mode) - if (s->mode != 1) { - // clear irq + // read limit (system counter mode) or read most signifying + // part of counter (user mode) + if (s->mode != 1) { + // clear irq qemu_irq_lower(s->irq); - s->reached = 0; + s->reached = 0; ret = s->limit & 0x7fffffff; - } - else { - slavio_timer_get_out(s); + } + else { + slavio_timer_get_out(s); ret = s->counthigh & 0x7fffffff; - } + } break; case 1: - // read counter and reached bit (system mode) or read lsbits - // of counter (user mode) - slavio_timer_get_out(s); - if (s->mode != 1) + // read counter and reached bit (system mode) or read lsbits + // of counter (user mode) + slavio_timer_get_out(s); + if (s->mode != 1) ret = (s->count & 0x7fffffff) | s->reached; - else + else ret = s->count; break; case 3: - // read start/stop status + // read start/stop status ret = s->stopped; break; case 4: - // read user/system mode + // read user/system mode ret = s->slave_mode; break; default: @@ -161,14 +161,14 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 qemu_irq_lower(s->irq); // fall through case 2: - // set limit without resetting counter + // set limit without resetting counter s->limit = val & 0x7ffffe00ULL; if (!s->limit) s->limit = 0x7ffffe00ULL; ptimer_set_limit(s->timer, s->limit >> 9, reload); - break; + break; case 1: - // set user counter limit LSW, reset counter + // set user counter limit LSW, reset counter if (s->mode == 1) { qemu_irq_lower(s->irq); s->limit &= 0x7fffffff00000000ULL; @@ -179,20 +179,20 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 } break; case 3: - // start/stop user counter - if (s->mode == 1) { - if (val & 1) { + // start/stop user counter + if (s->mode == 1) { + if (val & 1) { ptimer_stop(s->timer); - s->stopped = 1; - } - else { + s->stopped = 1; + } + else { ptimer_run(s->timer, 0); - s->stopped = 0; - } - } - break; + s->stopped = 0; + } + } + break; case 4: - // bit 0: user (1) or system (0) counter mode + // bit 0: user (1) or system (0) counter mode { unsigned int i; @@ -211,9 +211,9 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3 } s->slave_mode = val & ((1 << MAX_CPUS) - 1); } - break; + break; default: - break; + break; } } @@ -294,7 +294,7 @@ static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, ptimer_set_period(s->timer, 500ULL); slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read, - slavio_timer_mem_write, s); + slavio_timer_mem_write, s); if (mode < 2) cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory); else diff --git a/hw/sun4m.c b/hw/sun4m.c index af96474bf8..1d9f76605e 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -52,7 +52,7 @@ #define PROM_SIZE_MAX (512 * 1024) #define PROM_PADDR 0xff0000000ULL #define PROM_VADDR 0xffd00000 -#define PROM_FILENAME "openbios-sparc32" +#define PROM_FILENAME "openbios-sparc32" #define MAX_CPUS 16 #define MAX_PILS 16 @@ -158,9 +158,9 @@ static void nvram_finish_partition (m48t59_t *nvram, uint32_t start, extern int nographic; static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, - int boot_device, uint32_t RAM_size, - uint32_t kernel_size, - int width, int height, int depth, + int boot_device, uint32_t RAM_size, + uint32_t kernel_size, + int width, int height, int depth, int machine_id) { unsigned char tmp = 0; @@ -179,8 +179,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); nvram_set_lword(nvram, 0x3C, kernel_size); if (cmdline) { - strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); - nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); + strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); + nvram_set_lword(nvram, 0x40, CMDLINE_ADDR); nvram_set_lword(nvram, 0x44, strlen(cmdline)); } // initrd_image, initrd_size passed differently @@ -444,13 +444,13 @@ static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device, kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, NULL); if (kernel_size < 0) - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); - if (kernel_size < 0) - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + if (kernel_size < 0) + kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); if (kernel_size < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); - exit(1); + exit(1); } /* load initrd */ @@ -464,14 +464,14 @@ static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device, } } if (initrd_size > 0) { - for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { - if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) - == 0x48647253) { // HdrS - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); - break; - } - } + for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { + if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) + == 0x48647253) { // HdrS + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); + break; + } + } } } nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, @@ -509,8 +509,8 @@ static const struct hwdef hwdefs[] = { .cs_irq = 5, .machine_id = 0x80, .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, }, }, /* SS-10 */ @@ -542,8 +542,8 @@ static const struct hwdef hwdefs[] = { .cs_irq = -1, .machine_id = 0x72, .intbit_to_level = { - 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, - 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, + 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, + 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, }, }, }; diff --git a/hw/sun4u.c b/hw/sun4u.c index cc5e200838..3b08340536 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -28,12 +28,12 @@ #define CMDLINE_ADDR 0x003ff000 #define INITRD_LOAD_ADDR 0x00300000 #define PROM_SIZE_MAX (512 * 1024) -#define PROM_ADDR 0x1fff0000000ULL -#define PROM_VADDR 0x000ffd00000ULL +#define PROM_ADDR 0x1fff0000000ULL +#define PROM_VADDR 0x000ffd00000ULL #define APB_SPECIAL_BASE 0x1fe00000000ULL -#define APB_MEM_BASE 0x1ff00000000ULL -#define VGA_BASE (APB_MEM_BASE + 0x400000ULL) -#define PROM_FILENAME "openbios-sparc64" +#define APB_MEM_BASE 0x1ff00000000ULL +#define VGA_BASE (APB_MEM_BASE + 0x400000ULL) +#define PROM_FILENAME "openbios-sparc64" #define NVRAM_SIZE 0x2000 /* TSC handling */ @@ -162,10 +162,10 @@ uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) odd = count & 1; count &= ~1; for (i = 0; i != count; i++) { - crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); + crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); } if (odd) { - crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); + crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); } return crc; @@ -387,9 +387,9 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); if (ret < 0) { - fprintf(stderr, "qemu: could not load prom '%s'\n", - buf); - exit(1); + fprintf(stderr, "qemu: could not load prom '%s'\n", + buf); + exit(1); } kernel_size = 0; @@ -398,13 +398,13 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, /* XXX: put correct offset */ kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); if (kernel_size < 0) - kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); - if (kernel_size < 0) - kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); + if (kernel_size < 0) + kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); if (kernel_size < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); - exit(1); + exit(1); } /* load initrd */ @@ -417,14 +417,14 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, } } if (initrd_size > 0) { - for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { - if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) - == 0x48647253) { // HdrS - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); - stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); - break; - } - } + for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { + if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) + == 0x48647253) { // HdrS + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); + stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); + break; + } + } } } pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); @@ -446,7 +446,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, for(i = 0; i < nb_nics; i++) { if (!nd_table[i].model) nd_table[i].model = "ne2k_pci"; - pci_nic_init(pci_bus, &nd_table[i], -1); + pci_nic_init(pci_bus, &nd_table[i], -1); } irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); @@ -84,39 +84,39 @@ static void update_palette_entries(TCXState *s, int start, int end) } static void tcx_draw_line32(TCXState *s1, uint8_t *d, - const uint8_t *s, int width) + const uint8_t *s, int width) { int x; uint8_t val; uint32_t *p = (uint32_t *)d; for(x = 0; x < width; x++) { - val = *s++; + val = *s++; *p++ = s1->palette[val]; } } static void tcx_draw_line16(TCXState *s1, uint8_t *d, - const uint8_t *s, int width) + const uint8_t *s, int width) { int x; uint8_t val; uint16_t *p = (uint16_t *)d; for(x = 0; x < width; x++) { - val = *s++; + val = *s++; *p++ = s1->palette[val]; } } static void tcx_draw_line8(TCXState *s1, uint8_t *d, - const uint8_t *s, int width) + const uint8_t *s, int width) { int x; uint8_t val; for(x = 0; x < width; x++) { - val = *s++; + val = *s++; *d++ = s1->palette[val]; } } @@ -183,7 +183,7 @@ static void tcx_update_display(void *opaque) void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); if (ts->ds->depth == 0) - return; + return; page = ts->vram_offset; y_start = -1; page_min = 0xffffffff; @@ -195,55 +195,55 @@ static void tcx_update_display(void *opaque) switch (ts->ds->depth) { case 32: - f = tcx_draw_line32; - break; + f = tcx_draw_line32; + break; case 15: case 16: - f = tcx_draw_line16; - break; + f = tcx_draw_line16; + break; default: case 8: - f = tcx_draw_line8; - break; + f = tcx_draw_line8; + break; case 0: - return; + return; } for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { - if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { - if (y_start < 0) + if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { + if (y_start < 0) y_start = y; if (page < page_min) page_min = page; if (page > page_max) page_max = page; - f(ts, d, s, ts->width); - d += dd; - s += ds; - f(ts, d, s, ts->width); - d += dd; - s += ds; - f(ts, d, s, ts->width); - d += dd; - s += ds; - f(ts, d, s, ts->width); - d += dd; - s += ds; - } else { + f(ts, d, s, ts->width); + d += dd; + s += ds; + f(ts, d, s, ts->width); + d += dd; + s += ds; + f(ts, d, s, ts->width); + d += dd; + s += ds; + f(ts, d, s, ts->width); + d += dd; + s += ds; + } else { if (y_start >= 0) { /* flush to display */ dpy_update(ts->ds, 0, y_start, ts->width, y - y_start); y_start = -1; } - d += dd * 4; - s += ds * 4; - } + d += dd * 4; + s += ds * 4; + } } if (y_start >= 0) { - /* flush to display */ - dpy_update(ts->ds, 0, y_start, - ts->width, y - y_start); + /* flush to display */ + dpy_update(ts->ds, 0, y_start, + ts->width, y - y_start); } /* reset modified pages */ if (page_min <= page_max) { @@ -334,7 +334,7 @@ static void tcx_invalidate_display(void *opaque) int i; for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { - cpu_physical_memory_set_dirty(s->vram_offset + i); + cpu_physical_memory_set_dirty(s->vram_offset + i); } } @@ -424,32 +424,32 @@ static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; switch (saddr) { case 0: - s->dac_index = val >> 24; - s->dac_state = 0; - break; + s->dac_index = val >> 24; + s->dac_state = 0; + break; case 1: - switch (s->dac_state) { - case 0: - s->r[s->dac_index] = val >> 24; + switch (s->dac_state) { + case 0: + s->r[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); - s->dac_state++; - break; - case 1: - s->g[s->dac_index] = val >> 24; + s->dac_state++; + break; + case 1: + s->g[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); - s->dac_state++; - break; - case 2: - s->b[s->dac_index] = val >> 24; + s->dac_state++; + break; + case 2: + s->b[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement - default: - s->dac_state = 0; - break; - } - break; + default: + s->dac_state = 0; + break; + } + break; default: - break; + break; } return; } |