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-rw-r--r--hw/arm_timer.c4
-rw-r--r--hw/axis_dev88.c31
-rw-r--r--hw/cirrus_vga.c1
-rw-r--r--hw/dma.c17
-rw-r--r--hw/elf_ops.h5
-rw-r--r--hw/isa.h2
-rw-r--r--hw/lsi53c895a.c4
-rw-r--r--hw/mips_jazz.c13
-rw-r--r--hw/mips_malta.c13
-rw-r--r--hw/pc.c46
-rw-r--r--hw/pc.h5
-rw-r--r--hw/pci-hotplug.c51
-rw-r--r--hw/pckbd.c112
-rw-r--r--hw/pflash_cfi01.c20
-rw-r--r--hw/ppc_prep.c15
-rw-r--r--hw/sparc32_dma.c12
-rw-r--r--hw/sun4m.c6
-rw-r--r--hw/sun4u.c6
-rw-r--r--hw/vga.c2
-rw-r--r--hw/vhost_net.c2
-rw-r--r--hw/vmmouse.c2
21 files changed, 222 insertions, 147 deletions
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 9fef191cbc..9073ffc007 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -71,7 +71,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
{
uint32_t limit;
- if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
+ if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
/* Free running. */
if (s->control & TIMER_CTRL_32BIT)
limit = 0xffffffff;
@@ -113,7 +113,7 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset,
case 1: freq >>= 4; break;
case 2: freq >>= 8; break;
}
- arm_timer_recalibrate(s, 0);
+ arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
ptimer_set_freq(s->timer, freq);
if (s->control & TIMER_CTRL_ENABLE) {
/* Restart the timer if still enabled. */
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index 5516e42528..7d59c96ca1 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -240,13 +240,22 @@ static CPUWriteMemoryFunc * const gpio_write[] = {
#define INTMEM_SIZE (128 * 1024)
-static uint32_t bootstrap_pc;
+static struct {
+ uint32_t bootstrap_pc;
+ uint32_t regs[16];
+} loadargs;
+
static void main_cpu_reset(void *opaque)
{
+ int i;
+
CPUState *env = opaque;
cpu_reset(env);
- env->pc = bootstrap_pc;
+ env->pc = loadargs.bootstrap_pc;
+ for (i = 0; i < 16; i++) {
+ env->regs[i] = loadargs.regs[i];
+ }
}
static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
@@ -352,15 +361,15 @@ void axisdev88_init (ram_addr_t ram_size,
devboard SDK. */
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
&entry, NULL, &high, 0, ELF_MACHINE, 0);
- bootstrap_pc = entry;
+ loadargs.bootstrap_pc = entry;
if (kernel_size < 0) {
/* Takes a kimage from the axis devboard SDK. */
kernel_size = load_image_targphys(kernel_filename, 0x40004000,
ram_size);
- bootstrap_pc = 0x40004000;
- env->regs[9] = 0x40004000 + kernel_size;
+ loadargs.bootstrap_pc = 0x40004000;
+ loadargs.regs[9] = 0x40004000 + kernel_size;
}
- env->regs[8] = 0x56902387; /* RAM init magic. */
+ loadargs.regs[8] = 0x56902387; /* RAM init magic. */
if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) {
if (kcmdline_len > 256) {
@@ -368,15 +377,11 @@ void axisdev88_init (ram_addr_t ram_size,
exit(1);
}
/* Let the kernel know we are modifying the cmdline. */
- env->regs[10] = 0x87109563;
- env->regs[11] = 0x40000000;
- pstrcpy_targphys("cmdline", env->regs[11], 256, kernel_cmdline);
+ loadargs.regs[10] = 0x87109563;
+ loadargs.regs[11] = 0x40000000;
+ pstrcpy_targphys("cmdline", loadargs.regs[11], 256, kernel_cmdline);
}
}
- env->pc = bootstrap_pc;
-
- printf ("pc =%x\n", env->pc);
- printf ("ram size =%ld\n", ram_size);
}
static QEMUMachine axisdev88_machine = {
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 9f61a01d45..ba4828996a 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2985,7 +2985,6 @@ static const VMStateDescription vmstate_pci_cirrus_vga = {
.version_id = 2,
.minimum_version_id = 2,
.minimum_version_id_old = 2,
- .post_load = cirrus_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
diff --git a/hw/dma.c b/hw/dma.c
index e5f7af7a88..5b215211e1 100644
--- a/hw/dma.c
+++ b/hw/dma.c
@@ -57,6 +57,7 @@ static struct dma_cont {
uint8_t flip_flop;
int dshift;
struct dma_regs regs[4];
+ qemu_irq *cpu_request_exit;
} dma_controllers[2];
enum {
@@ -444,9 +445,9 @@ int DMA_write_memory (int nchan, void *buf, int pos, int len)
/* request the emulator to transfer a new DMA memory block ASAP */
void DMA_schedule(int nchan)
{
- CPUState *env = cpu_single_env;
- if (env)
- cpu_exit(env);
+ struct dma_cont *d = &dma_controllers[nchan > 3];
+
+ qemu_irq_pulse(*d->cpu_request_exit);
}
static void dma_reset(void *opaque)
@@ -464,12 +465,14 @@ static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
static void dma_init2(struct dma_cont *d, int base, int dshift,
- int page_base, int pageh_base)
+ int page_base, int pageh_base,
+ qemu_irq *cpu_request_exit)
{
static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
int i;
d->dshift = dshift;
+ d->cpu_request_exit = cpu_request_exit;
for (i = 0; i < 8; i++) {
register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
@@ -539,12 +542,12 @@ static const VMStateDescription vmstate_dma = {
}
};
-void DMA_init (int high_page_enable)
+void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
{
dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
- high_page_enable ? 0x480 : -1);
+ high_page_enable ? 0x480 : -1, cpu_request_exit);
dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
- high_page_enable ? 0x488 : -1);
+ high_page_enable ? 0x488 : -1, cpu_request_exit);
vmstate_register (0, &vmstate_dma, &dma_controllers[0]);
vmstate_register (1, &vmstate_dma, &dma_controllers[1]);
diff --git a/hw/elf_ops.h b/hw/elf_ops.h
index 69c07571b6..27d1ab9bc2 100644
--- a/hw/elf_ops.h
+++ b/hw/elf_ops.h
@@ -216,6 +216,11 @@ static int glue(load_elf, SZ)(const char *name, int fd,
if (EM_386 != ehdr.e_machine)
goto fail;
break;
+ case EM_MICROBLAZE:
+ if (EM_MICROBLAZE != ehdr.e_machine)
+ if (EM_MICROBLAZE_OLD != ehdr.e_machine)
+ goto fail;
+ break;
default:
if (elf_machine != ehdr.e_machine)
goto fail;
diff --git a/hw/isa.h b/hw/isa.h
index 97f69a25cb..aaf0272c25 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -41,7 +41,7 @@ int DMA_write_memory (int nchan, void *buf, int pos, int size);
void DMA_hold_DREQ (int nchan);
void DMA_release_DREQ (int nchan);
void DMA_schedule(int nchan);
-void DMA_init (int high_page_enable);
+void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit);
void DMA_register_channel (int nchan,
DMA_transfer_handler transfer_handler,
void *opaque);
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index 9d3c44d1c7..f5a91ba10a 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -543,7 +543,7 @@ static void lsi_do_dma(LSIState *s, int out)
return;
}
- id = s->current->tag >> 8;
+ id = (s->current->tag >> 8) & 0xf;
dev = s->bus.devs[id];
if (!dev) {
lsi_bad_selection(s, id);
@@ -745,7 +745,7 @@ static void lsi_do_command(LSIState *s)
s->sfbr = buf[0];
s->command_complete = 0;
- id = s->select_tag >> 8;
+ id = (s->select_tag >> 8) & 0xf;
dev = s->bus.devs[id];
if (!dev) {
lsi_bad_selection(s, id);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 6e0ec8fd36..ead3a00c3d 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -114,6 +114,15 @@ static void audio_init(qemu_irq *pic)
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
+static void cpu_request_exit(void *opaque, int irq, int level)
+{
+ CPUState *env = cpu_single_env;
+
+ if (env && level) {
+ cpu_exit(env);
+ }
+}
+
static
void mips_jazz_init (ram_addr_t ram_size,
const char *cpu_model,
@@ -130,6 +139,7 @@ void mips_jazz_init (ram_addr_t ram_size,
PITState *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset;
+ qemu_irq *cpu_exit_irq;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
@@ -189,7 +199,8 @@ void mips_jazz_init (ram_addr_t ram_size,
i8259 = i8259_init(env->irq[4]);
isa_bus_new(NULL);
isa_bus_irqs(i8259);
- DMA_init(0);
+ cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
+ DMA_init(0, cpu_exit_irq);
pit = pit_init(0x40, i8259[0]);
pcspk_init(pit);
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 792709bf5a..a8f9d152dd 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -763,6 +763,15 @@ static void main_cpu_reset(void *opaque)
}
}
+static void cpu_request_exit(void *opaque, int irq, int level)
+{
+ CPUState *env = cpu_single_env;
+
+ if (env && level) {
+ cpu_exit(env);
+ }
+}
+
static
void mips_malta_init (ram_addr_t ram_size,
const char *boot_device,
@@ -781,6 +790,7 @@ void mips_malta_init (ram_addr_t ram_size,
FDCtrl *floppy_controller;
MaltaFPGAState *malta_fpga;
qemu_irq *i8259;
+ qemu_irq *cpu_exit_irq;
int piix4_devfn;
uint8_t *eeprom_buf;
i2c_bus *smbus;
@@ -943,7 +953,8 @@ void mips_malta_init (ram_addr_t ram_size,
qdev_init_nofail(eeprom);
}
pit = pit_init(0x40, isa_reserve_irq(0));
- DMA_init(0);
+ cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
+ DMA_init(0, cpu_exit_irq);
/* Super I/O */
isa_dev = isa_create_simple("i8042");
diff --git a/hw/pc.c b/hw/pc.c
index 7715b17d56..e7f31d3848 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -365,26 +365,12 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
rtc_set_memory(s, 0x39, val);
}
-void ioport_set_a20(int enable)
+static void handle_a20_line_change(void *opaque, int irq, int level)
{
- /* XXX: send to all CPUs ? */
- cpu_x86_set_a20(first_cpu, enable);
-}
-
-int ioport_get_a20(void)
-{
- return ((first_cpu->a20_mask >> 20) & 1);
-}
+ CPUState *cpu = opaque;
-static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
-{
- ioport_set_a20((val >> 1) & 1);
- /* XXX: bit 0 is fast reset */
-}
-
-static uint32_t ioport92_read(void *opaque, uint32_t addr)
-{
- return ioport_get_a20() << 1;
+ /* XXX: send to all CPUs ? */
+ cpu_x86_set_a20(cpu, level);
}
/***********************************************************/
@@ -928,6 +914,15 @@ void pc_vga_init(PCIBus *pci_bus)
}
}
+static void cpu_request_exit(void *opaque, int irq, int level)
+{
+ CPUState *env = cpu_single_env;
+
+ if (env && level) {
+ cpu_exit(env);
+ }
+}
+
void pc_basic_device_init(qemu_irq *isa_irq,
FDCtrl **floppy_controller,
ISADevice **rtc_state)
@@ -935,6 +930,9 @@ void pc_basic_device_init(qemu_irq *isa_irq,
int i;
DriveInfo *fd[MAX_FD];
PITState *pit;
+ qemu_irq *a20_line;
+ ISADevice *i8042;
+ qemu_irq *cpu_exit_irq;
register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
@@ -944,9 +942,6 @@ void pc_basic_device_init(qemu_irq *isa_irq,
qemu_register_boot_set(pc_boot_set, *rtc_state);
- register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
- register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
-
pit = pit_init(0x40, isa_reserve_irq(0));
pcspk_init(pit);
if (!no_hpet) {
@@ -965,8 +960,13 @@ void pc_basic_device_init(qemu_irq *isa_irq,
}
}
- isa_create_simple("i8042");
- DMA_init(0);
+ a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
+ i8042 = isa_create_simple("i8042");
+ i8042_setup_a20_line(i8042, a20_line);
+ vmmouse_init(i8042);
+
+ cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
+ DMA_init(0, cpu_exit_irq);
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
diff --git a/hw/pc.h b/hw/pc.h
index 654b7b33d6..73cccefff7 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -75,6 +75,8 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
target_phys_addr_t base, ram_addr_t size,
target_phys_addr_t mask);
+void i8042_isa_mouse_fake_event(void *opaque);
+void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
/* pc.c */
extern int fd_bootchk;
@@ -104,9 +106,6 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
FDCtrl *floppy_controller, ISADevice *s);
void pc_pci_device_init(PCIBus *pci_bus);
-void ioport_set_a20(int enable);
-int ioport_get_a20(void);
-
typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);
diff --git a/hw/pci-hotplug.c b/hw/pci-hotplug.c
index cc45c504ad..37ac015f7d 100644
--- a/hw/pci-hotplug.c
+++ b/hw/pci-hotplug.c
@@ -33,7 +33,6 @@
#include "scsi.h"
#include "virtio-blk.h"
#include "qemu-config.h"
-#include "qemu-objects.h"
#if defined(TARGET_I386)
static PCIDevice *qemu_pci_hot_add_nic(Monitor *mon,
@@ -224,36 +223,7 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
return dev;
}
-void pci_device_hot_add_print(Monitor *mon, const QObject *data)
-{
- QDict *qdict;
-
- assert(qobject_type(data) == QTYPE_QDICT);
- qdict = qobject_to_qdict(data);
-
- monitor_printf(mon, "OK domain %d, bus %d, slot %d, function %d\n",
- (int) qdict_get_int(qdict, "domain"),
- (int) qdict_get_int(qdict, "bus"),
- (int) qdict_get_int(qdict, "slot"),
- (int) qdict_get_int(qdict, "function"));
-
-}
-
-/**
- * pci_device_hot_add(): Hot add a PCI device
- *
- * Return a QDict with the following device information:
- *
- * - "domain": domain number
- * - "bus": bus number
- * - "slot": slot number
- * - "function": function number
- *
- * Example:
- *
- * { "domain": 0, "bus": 0, "slot": 5, "function": 0 }
- */
-int pci_device_hot_add(Monitor *mon, const QDict *qdict, QObject **ret_data)
+void pci_device_hot_add(Monitor *mon, const QDict *qdict)
{
PCIDevice *dev = NULL;
const char *pci_addr = qdict_get_str(qdict, "pci_addr");
@@ -278,20 +248,14 @@ int pci_device_hot_add(Monitor *mon, const QDict *qdict, QObject **ret_data)
dev = qemu_pci_hot_add_storage(mon, pci_addr, opts);
} else {
monitor_printf(mon, "invalid type: %s\n", type);
- return -1;
}
if (dev) {
- *ret_data =
- qobject_from_jsonf("{ 'domain': 0, 'bus': %d, 'slot': %d, "
- "'function': %d }", pci_bus_num(dev->bus),
- PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
- } else {
+ monitor_printf(mon, "OK domain %d, bus %d, slot %d, function %d\n",
+ 0, pci_bus_num(dev->bus), PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn));
+ } else
monitor_printf(mon, "failed to add %s\n", opts);
- return -1;
- }
-
- return 0;
}
#endif
@@ -313,8 +277,7 @@ int pci_device_hot_remove(Monitor *mon, const char *pci_addr)
return qdev_unplug(&d->qdev);
}
-int do_pci_device_hot_remove(Monitor *mon, const QDict *qdict,
- QObject **ret_data)
+void do_pci_device_hot_remove(Monitor *mon, const QDict *qdict)
{
- return pci_device_hot_remove(mon, qdict_get_str(qdict, "pci_addr"));
+ pci_device_hot_remove(mon, qdict_get_str(qdict, "pci_addr"));
}
diff --git a/hw/pckbd.c b/hw/pckbd.c
index e83b8a6bcb..381228479e 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -29,6 +29,12 @@
/* debug PC keyboard */
//#define DEBUG_KBD
+#ifdef DEBUG_KBD
+#define DPRINTF(fmt, ...) \
+ do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
/* Keyboard Controller Commands */
#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
@@ -87,6 +93,12 @@
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80
+/* Output Port Bits */
+#define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
+#define KBD_OUT_A20 0x02 /* x86 only */
+#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
+#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
+
/* Mouse Commands */
#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
@@ -116,6 +128,7 @@ typedef struct KBDState {
uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
uint8_t status;
uint8_t mode;
+ uint8_t outport;
/* Bitmask of devices with data available. */
uint8_t pending;
void *kbd;
@@ -123,6 +136,7 @@ typedef struct KBDState {
qemu_irq irq_kbd;
qemu_irq irq_mouse;
+ qemu_irq *a20_out;
target_phys_addr_t mask;
} KBDState;
@@ -136,11 +150,14 @@ static void kbd_update_irq(KBDState *s)
irq_kbd_level = 0;
irq_mouse_level = 0;
s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
+ s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
if (s->pending) {
s->status |= KBD_STAT_OBF;
+ s->outport |= KBD_OUT_OBF;
/* kbd data takes priority over aux data. */
if (s->pending == KBD_PENDING_AUX) {
s->status |= KBD_STAT_MOUSE_OBF;
+ s->outport |= KBD_OUT_MOUSE_OBF;
if (s->mode & KBD_MODE_MOUSE_INT)
irq_mouse_level = 1;
} else {
@@ -180,9 +197,7 @@ static uint32_t kbd_read_status(void *opaque, uint32_t addr)
KBDState *s = opaque;
int val;
val = s->status;
-#if defined(DEBUG_KBD)
- printf("kbd: read status=0x%02x\n", val);
-#endif
+ DPRINTF("kbd: read status=0x%02x\n", val);
return val;
}
@@ -194,13 +209,35 @@ static void kbd_queue(KBDState *s, int b, int aux)
ps2_queue(s->kbd, b);
}
+static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ KBDState *s = opaque;
+
+ DPRINTF("kbd: write outport=0x%02x\n", val);
+ s->outport = val;
+ if (s->a20_out) {
+ qemu_set_irq(*s->a20_out, (val >> 1) & 1);
+ }
+ if (!(val & 1)) {
+ qemu_system_reset_request();
+ }
+}
+
+static uint32_t ioport92_read(void *opaque, uint32_t addr)
+{
+ KBDState *s = opaque;
+ uint32_t ret;
+
+ ret = s->outport;
+ DPRINTF("kbd: read outport=0x%02x\n", ret);
+ return ret;
+}
+
static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
{
KBDState *s = opaque;
-#ifdef DEBUG_KBD
- printf("kbd: write cmd=0x%02x\n", val);
-#endif
+ DPRINTF("kbd: write cmd=0x%02x\n", val);
switch(val) {
case KBD_CCMD_READ_MODE:
kbd_queue(s, s->mode, 0);
@@ -240,26 +277,20 @@ static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
kbd_queue(s, 0x00, 0);
break;
case KBD_CCMD_READ_OUTPORT:
- /* XXX: check that */
-#ifdef TARGET_I386
- val = 0x01 | (ioport_get_a20() << 1);
-#else
- val = 0x01;
-#endif
- if (s->status & KBD_STAT_OBF)
- val |= 0x10;
- if (s->status & KBD_STAT_MOUSE_OBF)
- val |= 0x20;
- kbd_queue(s, val, 0);
+ kbd_queue(s, s->outport, 0);
break;
-#ifdef TARGET_I386
case KBD_CCMD_ENABLE_A20:
- ioport_set_a20(1);
+ if (s->a20_out) {
+ qemu_irq_raise(*s->a20_out);
+ }
+ s->outport |= KBD_OUT_A20;
break;
case KBD_CCMD_DISABLE_A20:
- ioport_set_a20(0);
+ if (s->a20_out) {
+ qemu_irq_lower(*s->a20_out);
+ }
+ s->outport &= ~KBD_OUT_A20;
break;
-#endif
case KBD_CCMD_RESET:
qemu_system_reset_request();
break;
@@ -282,9 +313,7 @@ static uint32_t kbd_read_data(void *opaque, uint32_t addr)
else
val = ps2_read_data(s->kbd);
-#if defined(DEBUG_KBD)
- printf("kbd: read data=0x%02x\n", val);
-#endif
+ DPRINTF("kbd: read data=0x%02x\n", val);
return val;
}
@@ -292,9 +321,7 @@ static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
{
KBDState *s = opaque;
-#ifdef DEBUG_KBD
- printf("kbd: write data=0x%02x\n", val);
-#endif
+ DPRINTF("kbd: write data=0x%02x\n", val);
switch(s->write_cmd) {
case 0:
@@ -313,12 +340,7 @@ static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
kbd_queue(s, val, 1);
break;
case KBD_CCMD_WRITE_OUTPORT:
-#ifdef TARGET_I386
- ioport_set_a20((val >> 1) & 1);
-#endif
- if (!(val & 1)) {
- qemu_system_reset_request();
- }
+ ioport92_write(s, 0, val);
break;
case KBD_CCMD_WRITE_MOUSE:
ps2_write_mouse(s->mouse, val);
@@ -335,6 +357,7 @@ static void kbd_reset(void *opaque)
s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
+ s->outport = KBD_OUT_RESET | KBD_OUT_A20;
}
static const VMStateDescription vmstate_kbd = {
@@ -401,9 +424,6 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
-#ifdef TARGET_I386
- vmmouse_init(s->mouse);
-#endif
qemu_register_reset(kbd_reset, s);
}
@@ -412,6 +432,21 @@ typedef struct ISAKBDState {
KBDState kbd;
} ISAKBDState;
+void i8042_isa_mouse_fake_event(void *opaque)
+{
+ ISADevice *dev = opaque;
+ KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
+
+ ps2_mouse_fake_event(s->mouse);
+}
+
+void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
+{
+ KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
+
+ s->a20_out = a20_out;
+}
+
static const VMStateDescription vmstate_kbd_isa = {
.name = "pckbd",
.version_id = 3,
@@ -434,12 +469,11 @@ static int i8042_initfn(ISADevice *dev)
register_ioport_write(0x60, 1, 1, kbd_write_data, s);
register_ioport_read(0x64, 1, 1, kbd_read_status, s);
register_ioport_write(0x64, 1, 1, kbd_write_command, s);
+ register_ioport_read(0x92, 1, 1, ioport92_read, s);
+ register_ioport_write(0x92, 1, 1, ioport92_write, s);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
-#ifdef TARGET_I386
- vmmouse_init(s->mouse);
-#endif
qemu_register_reset(kbd_reset, s);
return 0;
}
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 20fe93d63c..19e13d632d 100644
--- a/hw/pflash_cfi01.c
+++ b/hw/pflash_cfi01.c
@@ -166,6 +166,22 @@ static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
ret = pfl->status;
DPRINTF("%s: status %x\n", __func__, ret);
break;
+ case 0x90:
+ switch (boff) {
+ case 0:
+ ret = pfl->ident[0] << 8 | pfl->ident[1];
+ DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
+ break;
+ case 1:
+ ret = pfl->ident[2] << 8 | pfl->ident[3];
+ DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
+ break;
+ default:
+ DPRINTF("%s: Read Device Information boff=%x\n", __func__, boff);
+ ret = 0;
+ break;
+ }
+ break;
case 0x98: /* Query mode */
if (boff > pfl->cfi_len)
ret = 0;
@@ -283,6 +299,10 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
DPRINTF("%s: Read status register\n", __func__);
pfl->cmd = cmd;
return;
+ case 0x90: /* Read Device ID */
+ DPRINTF("%s: Read Device information\n", __func__);
+ pfl->cmd = cmd;
+ return;
case 0x98: /* CFI query */
DPRINTF("%s: CFI query\n", __func__);
break;
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 09a98819d1..16c9950740 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -547,6 +547,15 @@ static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
#define NVRAM_SIZE 0x2000
+static void cpu_request_exit(void *opaque, int irq, int level)
+{
+ CPUState *env = cpu_single_env;
+
+ if (env && level) {
+ cpu_exit(env);
+ }
+}
+
/* PowerPC PREP hardware initialisation */
static void ppc_prep_init (ram_addr_t ram_size,
const char *boot_device,
@@ -565,6 +574,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
PCIBus *pci_bus;
qemu_irq *i8259;
+ qemu_irq *cpu_exit_irq;
int ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *fd[MAX_FD];
@@ -719,7 +729,10 @@ static void ppc_prep_init (ram_addr_t ram_size,
hd[2 * i + 1]);
}
isa_create_simple("i8042");
- DMA_init(1);
+
+ cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
+ DMA_init(1, cpu_exit_irq);
+
// SB16_init();
for(i = 0; i < MAX_FD; i++) {
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index 3ceb851e91..b52170787b 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -62,6 +62,9 @@
#define DMA_DRAIN_FIFO 0x40
#define DMA_RESET 0x80
+/* XXX SCSI and ethernet should have different read-only bit masks */
+#define DMA_CSR_RO_MASK 0xfe000007
+
typedef struct DMAState DMAState;
struct DMAState {
@@ -187,7 +190,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
switch (saddr) {
case 0:
if (val & DMA_INTREN) {
- if (val & DMA_INTR) {
+ if (s->dmaregs[0] & DMA_INTR) {
DPRINTF("Raise IRQ\n");
qemu_irq_raise(s->irq);
}
@@ -204,16 +207,17 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
val &= ~DMA_DRAIN_FIFO;
} else if (val == 0)
val = DMA_DRAIN_FIFO;
- val &= 0x0fffffff;
+ val &= ~DMA_CSR_RO_MASK;
val |= DMA_VER;
+ s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
break;
case 1:
s->dmaregs[0] |= DMA_LOADED;
- break;
+ /* fall through */
default:
+ s->dmaregs[saddr] = val;
break;
}
- s->dmaregs[saddr] = val;
}
static CPUReadMemoryFunc * const dma_mem_read[3] = {
diff --git a/hw/sun4m.c b/hw/sun4m.c
index 9a79120b1d..7ba0f763bc 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -152,7 +152,11 @@ int DMA_write_memory (int nchan, void *buf, int pos, int size)
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
-void DMA_init (int high_page_enable) {}
+
+void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
+{
+}
+
void DMA_register_channel (int nchan,
DMA_transfer_handler transfer_handler,
void *opaque)
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 24ea367d1a..e9a1e231e9 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -105,7 +105,11 @@ int DMA_write_memory (int nchan, void *buf, int pos, int size)
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
-void DMA_init (int high_page_enable) {}
+
+void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
+{
+}
+
void DMA_register_channel (int nchan,
DMA_transfer_handler transfer_handler,
void *opaque)
diff --git a/hw/vga.c b/hw/vga.c
index 87a1bb06d1..01de1e1b04 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -232,7 +232,7 @@ static void vga_precise_update_retrace_info(VGACommonState *s)
"clocking_mode = %d\n"
"clock_sel = %d %d\n"
"dots = %d\n"
- "ticks/char = %lld\n"
+ "ticks/char = %" PRId64 "\n"
"\n",
(double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
htotal_chars,
diff --git a/hw/vhost_net.c b/hw/vhost_net.c
index 2e292eea26..26dae797bf 100644
--- a/hw/vhost_net.c
+++ b/hw/vhost_net.c
@@ -99,7 +99,7 @@ struct vhost_net *vhost_net_init(VLANClientState *backend, int devfd)
goto fail;
}
if (~net->dev.features & net->dev.backend_features) {
- fprintf(stderr, "vhost lacks feature mask %llu for backend\n",
+ fprintf(stderr, "vhost lacks feature mask %" PRIu64 " for backend\n",
~net->dev.features & net->dev.backend_features);
vhost_dev_cleanup(&net->dev);
goto fail;
diff --git a/hw/vmmouse.c b/hw/vmmouse.c
index bb6e6056d6..afebad9a0a 100644
--- a/hw/vmmouse.c
+++ b/hw/vmmouse.c
@@ -97,7 +97,7 @@ static void vmmouse_mouse_event(void *opaque, int x, int y, int dz, int buttons_
/* need to still generate PS2 events to notify driver to
read from queue */
- ps2_mouse_fake_event(s->ps2_mouse);
+ i8042_isa_mouse_fake_event(s->ps2_mouse);
}
static void vmmouse_update_handler(VMMouseState *s)
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-28 06:04:47 +0000