diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/ads7846.c | 24 | ||||
| -rw-r--r-- | hw/axis_dev88.c | 2 | ||||
| -rw-r--r-- | hw/blizzard.c | 28 | ||||
| -rw-r--r-- | hw/cbus.c | 85 | ||||
| -rw-r--r-- | hw/devices.h | 48 | ||||
| -rw-r--r-- | hw/ecc.c | 8 | ||||
| -rw-r--r-- | hw/flash.h | 26 | ||||
| -rw-r--r-- | hw/gumstix.c | 4 | ||||
| -rw-r--r-- | hw/i2c.h | 8 | ||||
| -rw-r--r-- | hw/ide.c | 32 | ||||
| -rw-r--r-- | hw/lm832x.c | 38 | ||||
| -rw-r--r-- | hw/mainstone.c | 2 | ||||
| -rw-r--r-- | hw/mainstone.h | 2 | ||||
| -rw-r--r-- | hw/max111x.c | 30 | ||||
| -rw-r--r-- | hw/max7310.c | 28 | ||||
| -rw-r--r-- | hw/mst_fpga.c | 2 | ||||
| -rw-r--r-- | hw/nand.c | 42 | ||||
| -rw-r--r-- | hw/nseries.c | 12 | ||||
| -rw-r--r-- | hw/omap.h | 8 | ||||
| -rw-r--r-- | hw/omap1.c | 10 | ||||
| -rw-r--r-- | hw/omap2.c | 2 | ||||
| -rw-r--r-- | hw/omap_mmc.c | 2 | ||||
| -rw-r--r-- | hw/onenand.c | 34 | ||||
| -rw-r--r-- | hw/palm.c | 4 | ||||
| -rw-r--r-- | hw/pcmcia.h | 14 | ||||
| -rw-r--r-- | hw/pl181.c | 2 | ||||
| -rw-r--r-- | hw/pxa.h | 88 | ||||
| -rw-r--r-- | hw/pxa2xx.c | 190 | ||||
| -rw-r--r-- | hw/pxa2xx_dma.c | 42 | ||||
| -rw-r--r-- | hw/pxa2xx_gpio.c | 32 | ||||
| -rw-r--r-- | hw/pxa2xx_keypad.c | 20 | ||||
| -rw-r--r-- | hw/pxa2xx_lcd.c | 54 | ||||
| -rw-r--r-- | hw/pxa2xx_mmci.c | 42 | ||||
| -rw-r--r-- | hw/pxa2xx_pcmcia.c | 36 | ||||
| -rw-r--r-- | hw/pxa2xx_pic.c | 24 | ||||
| -rw-r--r-- | hw/pxa2xx_timer.c | 22 | ||||
| -rw-r--r-- | hw/sd.c | 8 | ||||
| -rw-r--r-- | hw/sd.h | 6 | ||||
| -rw-r--r-- | hw/sharpsl.h | 7 | ||||
| -rw-r--r-- | hw/spitz.c | 88 | ||||
| -rw-r--r-- | hw/ssi-sd.c | 2 | ||||
| -rw-r--r-- | hw/tc6393xb.c | 50 | ||||
| -rw-r--r-- | hw/tc6393xb_template.h | 2 | ||||
| -rw-r--r-- | hw/tmp105.c | 30 | ||||
| -rw-r--r-- | hw/tosa.c | 20 | ||||
| -rw-r--r-- | hw/tsc2005.c | 32 | ||||
| -rw-r--r-- | hw/tsc210x.c | 96 | ||||
| -rw-r--r-- | hw/tusb6010.c | 40 | ||||
| -rw-r--r-- | hw/twl92230.c | 44 | ||||
| -rw-r--r-- | hw/usb-musb.c | 138 | ||||
| -rw-r--r-- | hw/usb.h | 10 | ||||
| -rw-r--r-- | hw/wm8750.c | 65 | ||||
| -rw-r--r-- | hw/zaurus.c | 28 |
53 files changed, 856 insertions, 857 deletions
diff --git a/hw/ads7846.c b/hw/ads7846.c index b39c00f515..9fa18c7cff 100644 --- a/hw/ads7846.c +++ b/hw/ads7846.c @@ -11,7 +11,7 @@ #include "devices.h" #include "console.h" -struct ads7846_state_s { +struct ADS7846State { qemu_irq interrupt; int input[8]; @@ -46,7 +46,7 @@ struct ads7846_state_s { #define ADS_Z1POS(x, y) 600 #define ADS_Z2POS(x, y) (600 + 6000 / ADS_XPOS(x, y)) -static void ads7846_int_update(struct ads7846_state_s *s) +static void ads7846_int_update(ADS7846State *s) { if (s->interrupt) qemu_set_irq(s->interrupt, s->pressure == 0); @@ -54,14 +54,14 @@ static void ads7846_int_update(struct ads7846_state_s *s) uint32_t ads7846_read(void *opaque) { - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque; + ADS7846State *s = (ADS7846State *) opaque; return s->output; } void ads7846_write(void *opaque, uint32_t value) { - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque; + ADS7846State *s = (ADS7846State *) opaque; switch (s->cycle ++) { case 0: @@ -94,7 +94,7 @@ void ads7846_write(void *opaque, uint32_t value) static void ads7846_ts_event(void *opaque, int x, int y, int z, int buttons_state) { - struct ads7846_state_s *s = opaque; + ADS7846State *s = opaque; if (buttons_state) { x = 0x7fff - x; @@ -113,7 +113,7 @@ static void ads7846_ts_event(void *opaque, static void ads7846_save(QEMUFile *f, void *opaque) { - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque; + ADS7846State *s = (ADS7846State *) opaque; int i; for (i = 0; i < 8; i ++) @@ -125,7 +125,7 @@ static void ads7846_save(QEMUFile *f, void *opaque) static int ads7846_load(QEMUFile *f, void *opaque, int version_id) { - struct ads7846_state_s *s = (struct ads7846_state_s *) opaque; + ADS7846State *s = (ADS7846State *) opaque; int i; for (i = 0; i < 8; i ++) @@ -140,12 +140,12 @@ static int ads7846_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct ads7846_state_s *ads7846_init(qemu_irq penirq) +ADS7846State *ads7846_init(qemu_irq penirq) { - struct ads7846_state_s *s; - s = (struct ads7846_state_s *) - qemu_mallocz(sizeof(struct ads7846_state_s)); - memset(s, 0, sizeof(struct ads7846_state_s)); + ADS7846State *s; + s = (ADS7846State *) + qemu_mallocz(sizeof(ADS7846State)); + memset(s, 0, sizeof(ADS7846State)); s->interrupt = penirq; diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c index 85ca81e772..e9f2ecee9d 100644 --- a/hw/axis_dev88.c +++ b/hw/axis_dev88.c @@ -37,7 +37,7 @@ struct nand_state_t { - struct nand_flash_s *nand; + NANDFlashState *nand; unsigned int rdy:1; unsigned int ale:1; unsigned int cle:1; diff --git a/hw/blizzard.c b/hw/blizzard.c index 0f6801631a..40739d5e86 100644 --- a/hw/blizzard.c +++ b/hw/blizzard.c @@ -28,7 +28,7 @@ typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int); -struct blizzard_s { +typedef struct { uint8_t reg; uint32_t addr; int swallow; @@ -120,7 +120,7 @@ struct blizzard_s { int pitch; blizzard_fn_t line_fn; } data; -}; +} BlizzardState; /* Bytes(!) per pixel */ static const int blizzard_iformat_bpp[0x10] = { @@ -144,7 +144,7 @@ static inline void blizzard_rgb2yuv(int r, int g, int b, *v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13); } -static void blizzard_window(struct blizzard_s *s) +static void blizzard_window(BlizzardState *s) { uint8_t *src, *dst; int bypp[2]; @@ -175,7 +175,7 @@ static void blizzard_window(struct blizzard_s *s) fn(dst, src, bypl[2]); } -static int blizzard_transfer_setup(struct blizzard_s *s) +static int blizzard_transfer_setup(BlizzardState *s) { if (s->source > 3 || !s->bpp || s->ix[1] < s->ix[0] || s->iy[1] < s->iy[0]) @@ -199,7 +199,7 @@ static int blizzard_transfer_setup(struct blizzard_s *s) return 1; } -static void blizzard_reset(struct blizzard_s *s) +static void blizzard_reset(BlizzardState *s) { s->reg = 0; s->swallow = 0; @@ -280,14 +280,14 @@ static void blizzard_reset(struct blizzard_s *s) } static inline void blizzard_invalidate_display(void *opaque) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; s->invalidate = 1; } static uint16_t blizzard_reg_read(void *opaque, uint8_t reg) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; switch (reg) { case 0x00: /* Revision Code */ @@ -490,7 +490,7 @@ static uint16_t blizzard_reg_read(void *opaque, uint8_t reg) static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; switch (reg) { case 0x04: /* PLL M-Divider */ @@ -831,7 +831,7 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value) uint16_t s1d13745_read(void *opaque, int dc) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; uint16_t value = blizzard_reg_read(s, s->reg); if (s->swallow -- > 0) @@ -844,7 +844,7 @@ uint16_t s1d13745_read(void *opaque, int dc) void s1d13745_write(void *opaque, int dc, uint16_t value) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; if (s->swallow -- > 0) return; @@ -860,7 +860,7 @@ void s1d13745_write(void *opaque, int dc, uint16_t value) void s1d13745_write_block(void *opaque, int dc, void *buf, size_t len, int pitch) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; while (len > 0) { if (s->reg == 0x90 && dc && @@ -886,7 +886,7 @@ void s1d13745_write_block(void *opaque, int dc, static void blizzard_update_display(void *opaque) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; int y, bypp, bypl, bwidth; uint8_t *src, *dst; @@ -935,7 +935,7 @@ static void blizzard_update_display(void *opaque) } static void blizzard_screen_dump(void *opaque, const char *filename) { - struct blizzard_s *s = (struct blizzard_s *) opaque; + BlizzardState *s = (BlizzardState *) opaque; blizzard_update_display(opaque); if (s && ds_get_data(s->state)) @@ -955,7 +955,7 @@ static void blizzard_screen_dump(void *opaque, const char *filename) { void *s1d13745_init(qemu_irq gpio_int) { - struct blizzard_s *s = (struct blizzard_s *) qemu_mallocz(sizeof(*s)); + BlizzardState *s = (BlizzardState *) qemu_mallocz(sizeof(*s)); s->fb = qemu_malloc(0x180000); @@ -28,9 +28,14 @@ //#define DEBUG -struct cbus_slave_s; -struct cbus_priv_s { - struct cbus_s cbus; +typedef struct { + void *opaque; + void (*io)(void *opaque, int rw, int reg, uint16_t *val); + int addr; +} CBusSlave; + +typedef struct { + CBus cbus; int sel; int dat; @@ -48,16 +53,10 @@ struct cbus_priv_s { cbus_value, } cycle; - struct cbus_slave_s *slave[8]; -}; - -struct cbus_slave_s { - void *opaque; - void (*io)(void *opaque, int rw, int reg, uint16_t *val); - int addr; -}; + CBusSlave *slave[8]; +} CBusPriv; -static void cbus_io(struct cbus_priv_s *s) +static void cbus_io(CBusPriv *s) { if (s->slave[s->addr]) s->slave[s->addr]->io(s->slave[s->addr]->opaque, @@ -66,7 +65,7 @@ static void cbus_io(struct cbus_priv_s *s) hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr); } -static void cbus_cycle(struct cbus_priv_s *s) +static void cbus_cycle(CBusPriv *s) { switch (s->cycle) { case cbus_address: @@ -97,7 +96,7 @@ static void cbus_cycle(struct cbus_priv_s *s) static void cbus_clk(void *opaque, int line, int level) { - struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; + CBusPriv *s = (CBusPriv *) opaque; if (!s->sel && level && !s->clk) { if (s->dir) @@ -114,14 +113,14 @@ static void cbus_clk(void *opaque, int line, int level) static void cbus_dat(void *opaque, int line, int level) { - struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; + CBusPriv *s = (CBusPriv *) opaque; s->dat = level; } static void cbus_sel(void *opaque, int line, int level) { - struct cbus_priv_s *s = (struct cbus_priv_s *) opaque; + CBusPriv *s = (CBusPriv *) opaque; if (!level) { s->dir = 1; @@ -132,9 +131,9 @@ static void cbus_sel(void *opaque, int line, int level) s->sel = level; } -struct cbus_s *cbus_init(qemu_irq dat) +CBus *cbus_init(qemu_irq dat) { - struct cbus_priv_s *s = (struct cbus_priv_s *) qemu_mallocz(sizeof(*s)); + CBusPriv *s = (CBusPriv *) qemu_mallocz(sizeof(*s)); s->dat_out = dat; s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0]; @@ -148,16 +147,16 @@ struct cbus_s *cbus_init(qemu_irq dat) return &s->cbus; } -void cbus_attach(struct cbus_s *bus, void *slave_opaque) +void cbus_attach(CBus *bus, void *slave_opaque) { - struct cbus_slave_s *slave = (struct cbus_slave_s *) slave_opaque; - struct cbus_priv_s *s = (struct cbus_priv_s *) bus; + CBusSlave *slave = (CBusSlave *) slave_opaque; + CBusPriv *s = (CBusPriv *) bus; s->slave[slave->addr] = slave; } /* Retu/Vilma */ -struct cbus_retu_s { +typedef struct { uint16_t irqst; uint16_t irqen; uint16_t cc[2]; @@ -172,10 +171,10 @@ struct cbus_retu_s { int is_vilma; qemu_irq irq; - struct cbus_slave_s cbus; -}; + CBusSlave cbus; +} CBusRetu; -static void retu_interrupt_update(struct cbus_retu_s *s) +static void retu_interrupt_update(CBusRetu *s) { qemu_set_irq(s->irq, s->irqst & ~s->irqen); } @@ -237,7 +236,7 @@ enum { retu_adc_self_temp = 13, /* RETU temperature */ }; -static inline uint16_t retu_read(struct cbus_retu_s *s, int reg) +static inline uint16_t retu_read(CBusRetu *s, int reg) { #ifdef DEBUG printf("RETU read at %02x\n", reg); @@ -304,7 +303,7 @@ static inline uint16_t retu_read(struct cbus_retu_s *s, int reg) } } -static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val) +static inline void retu_write(CBusRetu *s, int reg, uint16_t val) { #ifdef DEBUG printf("RETU write of %04x at %02x\n", val, reg); @@ -379,7 +378,7 @@ static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val) static void retu_io(void *opaque, int rw, int reg, uint16_t *val) { - struct cbus_retu_s *s = (struct cbus_retu_s *) opaque; + CBusRetu *s = (CBusRetu *) opaque; if (rw) *val = retu_read(s, reg); @@ -389,7 +388,7 @@ static void retu_io(void *opaque, int rw, int reg, uint16_t *val) void *retu_init(qemu_irq irq, int vilma) { - struct cbus_retu_s *s = (struct cbus_retu_s *) qemu_mallocz(sizeof(*s)); + CBusRetu *s = (CBusRetu *) qemu_mallocz(sizeof(*s)); s->irq = irq; s->irqen = 0xffff; @@ -419,8 +418,8 @@ void *retu_init(qemu_irq irq, int vilma) void retu_key_event(void *retu, int state) { - struct cbus_slave_s *slave = (struct cbus_slave_s *) retu; - struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque; + CBusSlave *slave = (CBusSlave *) retu; + CBusRetu *s = (CBusRetu *) slave->opaque; s->irqst |= 1 << retu_int_pwr; retu_interrupt_update(s); @@ -434,8 +433,8 @@ void retu_key_event(void *retu, int state) #if 0 static void retu_head_event(void *retu, int state) { - struct cbus_slave_s *slave = (struct cbus_slave_s *) retu; - struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque; + CBusSlave *slave = (CBusSlave *) retu; + CBusRetu *s = (CBusRetu *) slave->opaque; if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */ /* TODO: reissue the interrupt every 100ms or so. */ @@ -451,8 +450,8 @@ static void retu_head_event(void *retu, int state) static void retu_hook_event(void *retu, int state) { - struct cbus_slave_s *slave = (struct cbus_slave_s *) retu; - struct cbus_retu_s *s = (struct cbus_retu_s *) slave->opaque; + CBusSlave *slave = (CBusSlave *) retu; + CBusRetu *s = (CBusRetu *) slave->opaque; if ((s->cc[0] & 0x500) == 0x500) { /* TODO: reissue the interrupt every 100ms or so. */ @@ -468,7 +467,7 @@ static void retu_hook_event(void *retu, int state) #endif /* Tahvo/Betty */ -struct cbus_tahvo_s { +typedef struct { uint16_t irqst; uint16_t irqen; uint8_t charger; @@ -478,10 +477,10 @@ struct cbus_tahvo_s { int is_betty; qemu_irq irq; - struct cbus_slave_s cbus; -}; + CBusSlave cbus; +} CBusTahvo; -static void tahvo_interrupt_update(struct cbus_tahvo_s *s) +static void tahvo_interrupt_update(CBusTahvo *s) { qemu_set_irq(s->irq, s->irqst & ~s->irqen); } @@ -501,7 +500,7 @@ static void tahvo_interrupt_update(struct cbus_tahvo_s *s) #define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */ #define TAHVO_REG_FRR 0x0d /* (RO) FR */ -static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg) +static inline uint16_t tahvo_read(CBusTahvo *s, int reg) { #ifdef DEBUG printf("TAHVO read at %02x\n", reg); @@ -543,7 +542,7 @@ static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg) } } -static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val) +static inline void tahvo_write(CBusTahvo *s, int reg, uint16_t val) { #ifdef DEBUG printf("TAHVO write of %04x at %02x\n", val, reg); @@ -595,7 +594,7 @@ static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val) static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val) { - struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) opaque; + CBusTahvo *s = (CBusTahvo *) opaque; if (rw) *val = tahvo_read(s, reg); @@ -605,7 +604,7 @@ static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val) void *tahvo_init(qemu_irq irq, int betty) { - struct cbus_tahvo_s *s = (struct cbus_tahvo_s *) qemu_mallocz(sizeof(*s)); + CBusTahvo *s = (CBusTahvo *) qemu_mallocz(sizeof(*s)); s->irq = irq; s->irqen = 0xffff; diff --git a/hw/devices.h b/hw/devices.h index 7914b3305a..4d4a4896bf 100644 --- a/hw/devices.h +++ b/hw/devices.h @@ -11,27 +11,25 @@ int ssd0323_xfer_ssi(void *opaque, int data); void *ssd0323_init(qemu_irq *cmd_p); /* ads7846.c */ -struct ads7846_state_s; +typedef struct ADS7846State ADS7846State; uint32_t ads7846_read(void *opaque); void ads7846_write(void *opaque, uint32_t value); -struct ads7846_state_s *ads7846_init(qemu_irq penirq); +ADS7846State *ads7846_init(qemu_irq penirq); /* tsc210x.c */ -struct uwire_slave_s; -struct mouse_transform_info_s; -struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio); -struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, +uWireSlave *tsc2102_init(qemu_irq pint, AudioState *audio); +uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav, AudioState *audio); -struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip); +I2SCodec *tsc210x_codec(uWireSlave *chip); uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len); -void tsc210x_set_transform(struct uwire_slave_s *chip, - struct mouse_transform_info_s *info); -void tsc210x_key_event(struct uwire_slave_s *chip, int key, int down); +void tsc210x_set_transform(uWireSlave *chip, + MouseTransformInfo *info); +void tsc210x_key_event(uWireSlave *chip, int key, int down); /* tsc2005.c */ void *tsc2005_init(qemu_irq pintdav); uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len); -void tsc2005_set_transform(void *opaque, struct mouse_transform_info_s *info); +void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); /* stellaris_input.c */ void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode); @@ -44,13 +42,13 @@ void s1d13745_write_block(void *opaque, int dc, uint16_t s1d13745_read(void *opaque, int dc); /* cbus.c */ -struct cbus_s { +typedef struct { qemu_irq clk; qemu_irq dat; qemu_irq sel; -}; -struct cbus_s *cbus_init(qemu_irq dat_out); -void cbus_attach(struct cbus_s *bus, void *slave_opaque); +} CBus; +CBus *cbus_init(qemu_irq dat_out); +void cbus_attach(CBus *bus, void *slave_opaque); void *retu_init(qemu_irq irq, int vilma); void *tahvo_init(qemu_irq irq, int betty); @@ -58,20 +56,20 @@ void *tahvo_init(qemu_irq irq, int betty); void retu_key_event(void *retu, int state); /* tusb6010.c */ -struct tusb_s; -struct tusb_s *tusb6010_init(qemu_irq intr); -int tusb6010_sync_io(struct tusb_s *s); -int tusb6010_async_io(struct tusb_s *s); -void tusb6010_power(struct tusb_s *s, int on); +typedef struct TUSBState TUSBState; +TUSBState *tusb6010_init(qemu_irq intr); +int tusb6010_sync_io(TUSBState *s); +int tusb6010_async_io(TUSBState *s); +void tusb6010_power(TUSBState *s, int on); /* tc6393xb.c */ -struct tc6393xb_s; +typedef struct TC6393xbState TC6393xbState; #define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */ -struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq); -void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line, +TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq); +void tc6393xb_gpio_out_set(TC6393xbState *s, int line, qemu_irq handler); -qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s); -qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s); +qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s); +qemu_irq tc6393xb_l3v_get(TC6393xbState *s); /* sm501.c */ void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq, @@ -50,7 +50,7 @@ static const uint8_t nand_ecc_precalc_table[] = { }; /* Update ECC parity count. */ -uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample) +uint8_t ecc_digest(ECCState *s, uint8_t sample) { uint8_t idx = nand_ecc_precalc_table[sample]; @@ -65,7 +65,7 @@ uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample) } /* Reinitialise the counters. */ -void ecc_reset(struct ecc_state_s *s) +void ecc_reset(ECCState *s) { s->lp[0] = 0x0000; s->lp[1] = 0x0000; @@ -74,7 +74,7 @@ void ecc_reset(struct ecc_state_s *s) } /* Save/restore */ -void ecc_put(QEMUFile *f, struct ecc_state_s *s) +void ecc_put(QEMUFile *f, ECCState *s) { qemu_put_8s(f, &s->cp); qemu_put_be16s(f, &s->lp[0]); @@ -82,7 +82,7 @@ void ecc_put(QEMUFile *f, struct ecc_state_s *s) qemu_put_be16s(f, &s->count); } -void ecc_get(QEMUFile *f, struct ecc_state_s *s) +void ecc_get(QEMUFile *f, ECCState *s) { qemu_get_8s(f, &s->cp); qemu_get_be16s(f, &s->lp[0]); diff --git a/hw/flash.h b/hw/flash.h index faba93d7e1..69aef8ce29 100644 --- a/hw/flash.h +++ b/hw/flash.h @@ -17,14 +17,14 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, uint16_t unlock_addr0, uint16_t unlock_addr1); /* nand.c */ -struct nand_flash_s; -struct nand_flash_s *nand_init(int manf_id, int chip_id); -void nand_done(struct nand_flash_s *s); -void nand_setpins(struct nand_flash_s *s, +typedef struct NANDFlashState NANDFlashState; +NANDFlashState *nand_init(int manf_id, int chip_id); +void nand_done(NANDFlashState *s); +void nand_setpins(NANDFlashState *s, int cle, int ale, int ce, int wp, int gnd); -void nand_getpins(struct nand_flash_s *s, int *rb); -void nand_setio(struct nand_flash_s *s, uint8_t value); -uint8_t nand_getio(struct nand_flash_s *s); +void nand_getpins(NANDFlashState *s, int *rb); +void nand_setio(NANDFlashState *s, uint8_t value); +uint8_t nand_getio(NANDFlashState *s); #define NAND_MFR_TOSHIBA 0x98 #define NAND_MFR_SAMSUNG 0xec @@ -42,13 +42,13 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq); void *onenand_raw_otp(void *opaque); /* ecc.c */ -struct ecc_state_s { +typedef struct { uint8_t cp; /* Column parity */ uint16_t lp[2]; /* Line parity */ uint16_t count; -}; +} ECCState; -uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample); -void ecc_reset(struct ecc_state_s *s); -void ecc_put(QEMUFile *f, struct ecc_state_s *s); -void ecc_get(QEMUFile *f, struct ecc_state_s *s); +uint8_t ecc_digest(ECCState *s, uint8_t sample); +void ecc_reset(ECCState *s); +void ecc_put(QEMUFile *f, ECCState *s); +void ecc_get(QEMUFile *f, ECCState *s); diff --git a/hw/gumstix.c b/hw/gumstix.c index cce86fba69..d116126d15 100644 --- a/hw/gumstix.c +++ b/hw/gumstix.c @@ -46,7 +46,7 @@ static void connex_init(ram_addr_t ram_size, int vga_ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - struct pxa2xx_state_s *cpu; + PXA2xxState *cpu; int index; uint32_t connex_rom = 0x01000000; @@ -80,7 +80,7 @@ static void verdex_init(ram_addr_t ram_size, int vga_ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - struct pxa2xx_state_s *cpu; + PXA2xxState *cpu; int index; uint32_t verdex_rom = 0x02000000; @@ -46,12 +46,12 @@ void i2c_slave_save(QEMUFile *f, i2c_slave *dev); void i2c_slave_load(QEMUFile *f, i2c_slave *dev); /* max111x.c */ -struct max111x_s; +typedef struct MAX111xState MAX111xState; uint32_t max111x_read(void *opaque); void max111x_write(void *opaque, uint32_t value); -struct max111x_s *max1110_init(qemu_irq cb); -struct max111x_s *max1111_init(qemu_irq cb); -void max111x_set_input(struct max111x_s *s, int line, uint8_t value); +MAX111xState *max1110_init(qemu_irq cb); +MAX111xState *max1111_init(qemu_irq cb); +void max111x_set_input(MAX111xState *s, int line, uint8_t value); /* max7310.c */ i2c_slave *max7310_init(i2c_bus *bus); @@ -3859,9 +3859,9 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, #define METADATA_SIZE 0x20 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */ -struct md_s { +typedef struct { IDEState ide[2]; - struct pcmcia_card_s card; + PCMCIACardState card; uint32_t attr_base; uint32_t io_base; @@ -3873,7 +3873,7 @@ struct md_s { uint8_t ctrl; uint16_t io; int cycle; -}; +} MicroDriveState; /* Register bitfields */ enum md_opt { @@ -3902,7 +3902,7 @@ enum md_ctrl { CTRL_SRST = 0x04, }; -static inline void md_interrupt_update(struct md_s *s) +static inline void md_interrupt_update(MicroDriveState *s) { if (!s->card.slot) return; @@ -3915,7 +3915,7 @@ static inline void md_interrupt_update(struct md_s *s) static void md_set_irq(void *opaque, int irq, int level) { - struct md_s *s = (struct md_s *) opaque; + MicroDriveState *s = (MicroDriveState *) opaque; if (level) s->stat |= STAT_INT; else @@ -3924,7 +3924,7 @@ static void md_set_irq(void *opaque, int irq, int level) md_interrupt_update(s); } -static void md_reset(struct md_s *s) +static void md_reset(MicroDriveState *s) { s->opt = OPT_MODE_MMAP; s->stat = 0; @@ -3936,7 +3936,7 @@ static void md_reset(struct md_s *s) static uint8_t md_attr_read(void *opaque, uint32_t at) { - struct md_s *s = (struct md_s *) opaque; + MicroDriveState *s = (MicroDriveState *) opaque; if (at < s->attr_base) { if (at < s->card.cis_len) return s->card.cis[at]; @@ -3969,7 +3969,7 @@ static uint8_t md_attr_read(void *opaque, uint32_t at) static void md_attr_write(void *opaque, uint32_t at, uint8_t value) { - struct md_s *s = (struct md_s *) opaque; + MicroDriveState *s = (MicroDriveState *) opaque; at -= s->attr_base; switch (at) { @@ -4000,7 +4000,7 @@ static void md_attr_write(void *opaque, uint32_t at, uint8_t value) static uint16_t md_common_read(void *opaque, uint32_t at) { - struct md_s *s = (struct md_s *) opaque; + MicroDriveState *s = (MicroDriveState *) opaque; uint16_t ret; at -= s->io_base; @@ -4059,7 +4059,7 @@ static uint16_t md_common_read(void *opaque, uint32_t at) static void md_common_write(void *opaque, uint32_t at, uint16_t value) { - struct md_s *s = (struct md_s *) opaque; + MicroDriveState *s = (MicroDriveState *) opaque; at -= s->io_base; switch (s->opt & OPT_MODE) { @@ -4120,7 +4120,7 @@ static void md_common_write(void *opaque, uint32_t at, uint16_t value) static void md_save(QEMUFile *f, void *opaque) { - struct md_s *s = (struct md_s *) opaque; + MicroDriveState *s = (MicroDriveState *) opaque; int i; uint8_t drive1_selected; @@ -4142,7 +4142,7 @@ static void md_save(QEMUFile *f, void *opaque) static int md_load(QEMUFile *f, void *opaque, int version_id) { - struct md_s *s = (struct md_s *) opaque; + MicroDriveState *s = (MicroDriveState *) opaque; int i; uint8_t drive1_selected; @@ -4351,7 +4351,7 @@ static const uint8_t dscm1xxxx_cis[0x14a] = { static int dscm1xxxx_attach(void *opaque) { - struct md_s *md = (struct md_s *) opaque; + MicroDriveState *md = (MicroDriveState *) opaque; md->card.attr_read = md_attr_read; md->card.attr_write = md_attr_write; md->card.common_read = md_common_read; @@ -4371,14 +4371,14 @@ static int dscm1xxxx_attach(void *opaque) static int dscm1xxxx_detach(void *opaque) { - struct md_s *md = (struct md_s *) opaque; + MicroDriveState *md = (MicroDriveState *) opaque; md_reset(md); return 0; } -struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv) +PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv) { - struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s)); + MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState)); md->card.state = md; md->card.attach = dscm1xxxx_attach; md->card.detach = dscm1xxxx_detach; diff --git a/hw/lm832x.c b/hw/lm832x.c index 6479e1487c..f3915f0d91 100644 --- a/hw/lm832x.c +++ b/hw/lm832x.c @@ -24,7 +24,7 @@ #include "qemu-timer.h" #include "console.h" -struct lm_kbd_s { +typedef struct { i2c_slave i2c; int i2c_dir; int i2c_cycle; @@ -66,7 +66,7 @@ struct lm_kbd_s { uint8_t addr[3]; QEMUTimer *tm[3]; } pwm; -}; +} LM823KbdState; #define INT_KEYPAD (1 << 0) #define INT_ERROR (1 << 3) @@ -78,16 +78,16 @@ struct lm_kbd_s { #define ERR_KEYOVR (1 << 2) #define ERR_FIFOOVR (1 << 6) -static void lm_kbd_irq_update(struct lm_kbd_s *s) +static void lm_kbd_irq_update(LM823KbdState *s) { qemu_set_irq(s->nirq, !s->status); } -static void lm_kbd_gpio_update(struct lm_kbd_s *s) +static void lm_kbd_gpio_update(LM823KbdState *s) { } -static void lm_kbd_reset(struct lm_kbd_s *s) +static void lm_kbd_reset(LM823KbdState *s) { s->config = 0x80; s->status = INT_NOINIT; @@ -100,18 +100,18 @@ static void lm_kbd_reset(struct lm_kbd_s *s) lm_kbd_gpio_update(s); } -static void lm_kbd_error(struct lm_kbd_s *s, int err) +static void lm_kbd_error(LM823KbdState *s, int err) { s->error |= err; s->status |= INT_ERROR; lm_kbd_irq_update(s); } -static void lm_kbd_pwm_tick(struct lm_kbd_s *s, int line) +static void lm_kbd_pwm_tick(LM823KbdState *s, int line) { } -static void lm_kbd_pwm_start(struct lm_kbd_s *s, int line) +static void lm_kbd_pwm_start(LM823KbdState *s, int line) { lm_kbd_pwm_tick(s, line); } @@ -158,7 +158,7 @@ enum { #define LM832x_MAX_KPX 8 #define LM832x_MAX_KPY 12 -static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte) +static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte) { int ret; @@ -239,7 +239,7 @@ static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte) return ret >> (byte << 3); } -static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value) +static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value) { switch (reg) { case LM832x_CMD_WRITE_CFG: @@ -378,7 +378,7 @@ static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value) static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event) { - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; + LM823KbdState *s = (LM823KbdState *) i2c; switch (event) { case I2C_START_RECV: @@ -394,14 +394,14 @@ static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event) static int lm_i2c_rx(i2c_slave *i2c) { - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; + LM823KbdState *s = (LM823KbdState *) i2c; return lm_kbd_read(s, s->reg, s->i2c_cycle ++); } static int lm_i2c_tx(i2c_slave *i2c, uint8_t data) { - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; + LM823KbdState *s = (LM823KbdState *) i2c; if (!s->i2c_cycle) s->reg = data; @@ -414,7 +414,7 @@ static int lm_i2c_tx(i2c_slave *i2c, uint8_t data) static void lm_kbd_save(QEMUFile *f, void *opaque) { - struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; + LM823KbdState *s = (LM823KbdState *) opaque; int i; i2c_slave_save(f, &s->i2c); @@ -450,7 +450,7 @@ static void lm_kbd_save(QEMUFile *f, void *opaque) static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id) { - struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; + LM823KbdState *s = (LM823KbdState *) opaque; int i; i2c_slave_load(f, &s->i2c); @@ -489,11 +489,11 @@ static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq) +i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq) { - struct lm_kbd_s *s; + LM823KbdState *s; - s = (struct lm_kbd_s *) i2c_slave_init(bus, 0, sizeof(struct lm_kbd_s)); + s = (LM823KbdState *) i2c_slave_init(bus, 0, sizeof(LM823KbdState)); s->model = 0x8323; s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s); s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s); @@ -514,7 +514,7 @@ struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq) void lm832x_key_event(struct i2c_slave *i2c, int key, int state) { - struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; + LM823KbdState *s = (LM823KbdState *) i2c; if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR)) return; diff --git a/hw/mainstone.c b/hw/mainstone.c index 522254a68e..0e3082f9bf 100644 --- a/hw/mainstone.c +++ b/hw/mainstone.c @@ -75,7 +75,7 @@ static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size, { uint32_t sector_len = 256 * 1024; target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; - struct pxa2xx_state_s *cpu; + PXA2xxState *cpu; qemu_irq *mst_irq; int i, index; diff --git a/hw/mainstone.h b/hw/mainstone.h index f970b9f270..9618c0632a 100644 --- a/hw/mainstone.h +++ b/hw/mainstone.h @@ -33,6 +33,6 @@ #define S1_IRQ 15 extern qemu_irq -*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq); +*mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq); #endif /* __MAINSTONE_H__ */ diff --git a/hw/max111x.c b/hw/max111x.c index 15392a21fc..c19154d749 100644 --- a/hw/max111x.c +++ b/hw/max111x.c @@ -10,7 +10,7 @@ #include "hw.h" #include "i2c.h" -struct max111x_s { +struct MAX111xState { qemu_irq interrupt; uint8_t tb1, rb2, rb3; int cycle; @@ -36,7 +36,7 @@ struct max111x_s { uint32_t max111x_read(void *opaque) { - struct max111x_s *s = (struct max111x_s *) opaque; + MAX111xState *s = (MAX111xState *) opaque; if (!s->tb1) return 0; @@ -54,7 +54,7 @@ uint32_t max111x_read(void *opaque) /* Interpret a control-byte */ void max111x_write(void *opaque, uint32_t value) { - struct max111x_s *s = (struct max111x_s *) opaque; + MAX111xState *s = (MAX111xState *) opaque; int measure, chan; /* Ignore the value if START bit is zero */ @@ -92,7 +92,7 @@ void max111x_write(void *opaque, uint32_t value) static void max111x_save(QEMUFile *f, void *opaque) { - struct max111x_s *s = (struct max111x_s *) opaque; + MAX111xState *s = (MAX111xState *) opaque; int i; qemu_put_8s(f, &s->tb1); @@ -106,7 +106,7 @@ static void max111x_save(QEMUFile *f, void *opaque) static int max111x_load(QEMUFile *f, void *opaque, int version_id) { - struct max111x_s *s = (struct max111x_s *) opaque; + MAX111xState *s = (MAX111xState *) opaque; int i; qemu_get_8s(f, &s->tb1); @@ -121,12 +121,12 @@ static int max111x_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static struct max111x_s *max111x_init(qemu_irq cb) +static MAX111xState *max111x_init(qemu_irq cb) { - struct max111x_s *s; - s = (struct max111x_s *) - qemu_mallocz(sizeof(struct max111x_s)); - memset(s, 0, sizeof(struct max111x_s)); + MAX111xState *s; + s = (MAX111xState *) + qemu_mallocz(sizeof(MAX111xState)); + memset(s, 0, sizeof(MAX111xState)); s->interrupt = cb; @@ -146,21 +146,21 @@ static struct max111x_s *max111x_init(qemu_irq cb) return s; } -struct max111x_s *max1110_init(qemu_irq cb) +MAX111xState *max1110_init(qemu_irq cb) { - struct max111x_s *s = max111x_init(cb); + MAX111xState *s = max111x_init(cb); s->inputs = 8; return s; } -struct max111x_s *max1111_init(qemu_irq cb) +MAX111xState *max1111_init(qemu_irq cb) { - struct max111x_s *s = max111x_init(cb); + MAX111xState *s = max111x_init(cb); s->inputs = 4; return s; } -void max111x_set_input(struct max111x_s *s, int line, uint8_t value) +void max111x_set_input(MAX111xState *s, int line, uint8_t value) { if (line >= s->inputs) { printf("%s: There's no input %i\n", __FUNCTION__, line); diff --git a/hw/max7310.c b/hw/max7310.c index ee57581030..f2a4b1b3d9 100644 --- a/hw/max7310.c +++ b/hw/max7310.c @@ -10,7 +10,7 @@ #include "hw.h" #include "i2c.h" -struct max7310_s { +typedef struct { i2c_slave i2c; int i2c_command_byte; int len; @@ -22,11 +22,11 @@ struct max7310_s { uint8_t command; qemu_irq handler[8]; qemu_irq *gpio_in; -}; +} MAX7310State; void max7310_reset(i2c_slave *i2c) { - struct max7310_s *s = (struct max7310_s *) i2c; + MAX7310State *s = (MAX7310State *) i2c; s->level &= s->direction; s->direction = 0xff; s->polarity = 0xf0; @@ -36,7 +36,7 @@ void max7310_reset(i2c_slave *i2c) static int max7310_rx(i2c_slave *i2c) { - struct max7310_s *s = (struct max7310_s *) i2c; + MAX7310State *s = (MAX7310State *) i2c; switch (s->command) { case 0x00: /* Input port */ @@ -71,7 +71,7 @@ static int max7310_rx(i2c_slave *i2c) static int max7310_tx(i2c_slave *i2c, uint8_t data) { - struct max7310_s *s = (struct max7310_s *) i2c; + MAX7310State *s = (MAX7310State *) i2c; uint8_t diff; int line; @@ -126,7 +126,7 @@ static int max7310_tx(i2c_slave *i2c, uint8_t data) static void max7310_event(i2c_slave *i2c, enum i2c_event event) { - struct max7310_s *s = (struct max7310_s *) i2c; + MAX7310State *s = (MAX7310State *) i2c; s->len = 0; switch (event) { @@ -146,7 +146,7 @@ static void max7310_event(i2c_slave *i2c, enum i2c_event event) static void max7310_save(QEMUFile *f, void *opaque) { - struct max7310_s *s = (struct max7310_s *) opaque; + MAX7310State *s = (MAX7310State *) opaque; qemu_put_be32(f, s->i2c_command_byte); qemu_put_be32(f, s->len); @@ -162,7 +162,7 @@ static void max7310_save(QEMUFile *f, void *opaque) static int max7310_load(QEMUFile *f, void *opaque, int version_id) { - struct max7310_s *s = (struct max7310_s *) opaque; + MAX7310State *s = (MAX7310State *) opaque; s->i2c_command_byte = qemu_get_be32(f); s->len = qemu_get_be32(f); @@ -179,7 +179,7 @@ static int max7310_load(QEMUFile *f, void *opaque, int version_id) static void max7310_gpio_set(void *opaque, int line, int level) { - struct max7310_s *s = (struct max7310_s *) opaque; + MAX7310State *s = (MAX7310State *) opaque; if (line >= ARRAY_SIZE(s->handler) || line < 0) hw_error("bad GPIO line"); @@ -191,10 +191,10 @@ static void max7310_gpio_set(void *opaque, int line, int level) /* MAX7310 is SMBus-compatible (can be used with only SMBus protocols), * but also accepts sequences that are not SMBus so return an I2C device. */ -struct i2c_slave *max7310_init(i2c_bus *bus) +i2c_slave *max7310_init(i2c_bus *bus) { - struct max7310_s *s = (struct max7310_s *) - i2c_slave_init(bus, 0, sizeof(struct max7310_s)); + MAX7310State *s = (MAX7310State *) + i2c_slave_init(bus, 0, sizeof(MAX7310State)); s->i2c.event = max7310_event; s->i2c.recv = max7310_rx; s->i2c.send = max7310_tx; @@ -210,13 +210,13 @@ struct i2c_slave *max7310_init(i2c_bus *bus) qemu_irq *max7310_gpio_in_get(i2c_slave *i2c) { - struct max7310_s *s = (struct max7310_s *) i2c; + MAX7310State *s = (MAX7310State *) i2c; return s->gpio_in; } void max7310_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler) { - struct max7310_s *s = (struct max7310_s *) i2c; + MAX7310State *s = (MAX7310State *) i2c; if (line >= ARRAY_SIZE(s->handler) || line < 0) hw_error("bad GPIO line"); diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c index c7bda34d52..84eedb7976 100644 --- a/hw/mst_fpga.c +++ b/hw/mst_fpga.c @@ -216,7 +216,7 @@ mst_fpga_load(QEMUFile *f, void *opaque, int version_id) return 0; } -qemu_irq *mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq) +qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq) { mst_irq_state *s; int iomemtype; @@ -45,7 +45,7 @@ # define MAX_PAGE 0x800 # define MAX_OOB 0x40 -struct nand_flash_s { +struct NANDFlashState { uint8_t manf_id, chip_id; int size, pages; int page_shift, oob_shift, erase_shift, addr_shift; @@ -64,9 +64,9 @@ struct nand_flash_s { int status; int offset; - void (*blk_write)(struct nand_flash_s *s); - void (*blk_erase)(struct nand_flash_s *s); - void (*blk_load)(struct nand_flash_s *s, uint32_t addr, int offset); + void (*blk_write)(NANDFlashState *s); + void (*blk_erase)(NANDFlashState *s); + void (*blk_load)(NANDFlashState *s, uint32_t addr, int offset); }; # define NAND_NO_AUTOINCR 0x00000001 @@ -106,7 +106,7 @@ struct nand_flash_s { # include "nand.c" /* Information based on Linux drivers/mtd/nand/nand_ids.c */ -static const struct nand_info_s { +static const struct { int size; int width; int page_shift; @@ -200,7 +200,7 @@ static const struct nand_info_s { [0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 }, }; -static void nand_reset(struct nand_flash_s *s) +static void nand_reset(NANDFlashState *s) { s->cmd = NAND_CMD_READ0; s->addr = 0; @@ -210,7 +210,7 @@ static void nand_reset(struct nand_flash_s *s) s->status &= NAND_IOSTATUS_UNPROTCT; } -static void nand_command(struct nand_flash_s *s) +static void nand_command(NANDFlashState *s) { switch (s->cmd) { case NAND_CMD_READ0: @@ -279,7 +279,7 @@ static void nand_command(struct nand_flash_s *s) static void nand_save(QEMUFile *f, void *opaque) { - struct nand_flash_s *s = (struct nand_flash_s *) opaque; + NANDFlashState *s = (NANDFlashState *) opaque; qemu_put_byte(f, s->cle); qemu_put_byte(f, s->ale); qemu_put_byte(f, s->ce); @@ -299,7 +299,7 @@ static void nand_save(QEMUFile *f, void *opaque) static int nand_load(QEMUFile *f, void *opaque, int version_id) { - struct nand_flash_s *s = (struct nand_flash_s *) opaque; + NANDFlashState *s = (NANDFlashState *) opaque; s->cle = qemu_get_byte(f); s->ale = qemu_get_byte(f); s->ce = qemu_get_byte(f); @@ -325,7 +325,7 @@ static int nand_load(QEMUFile *f, void *opaque, int version_id) * * CE, WP and R/B are active low. */ -void nand_setpins(struct nand_flash_s *s, +void nand_setpins(NANDFlashState *s, int cle, int ale, int ce, int wp, int gnd) { s->cle = cle; @@ -339,12 +339,12 @@ void nand_setpins(struct nand_flash_s *s, s->status &= ~NAND_IOSTATUS_UNPROTCT; } -void nand_getpins(struct nand_flash_s *s, int *rb) +void nand_getpins(NANDFlashState *s, int *rb) { *rb = 1; } -void nand_setio(struct nand_flash_s *s, uint8_t value) +void nand_setio(NANDFlashState *s, uint8_t value) { if (!s->ce && s->cle) { if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { @@ -415,7 +415,7 @@ void nand_setio(struct nand_flash_s *s, uint8_t value) } } -uint8_t nand_getio(struct nand_flash_s *s) +uint8_t nand_getio(NANDFlashState *s) { int offset; @@ -438,17 +438,17 @@ uint8_t nand_getio(struct nand_flash_s *s) return *(s->ioaddr ++); } -struct nand_flash_s *nand_init(int manf_id, int chip_id) +NANDFlashState *nand_init(int manf_id, int chip_id) { int pagesize; - struct nand_flash_s *s; + NANDFlashState *s; int index; if (nand_flash_ids[chip_id].size == 0) { hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__); } - s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct nand_flash_s)); + s = (NANDFlashState *) qemu_mallocz(sizeof(NANDFlashState)); index = drive_get_index(IF_MTD, 0, 0); if (index != -1) s->bdrv = drives_table[index].bdrv; @@ -499,7 +499,7 @@ struct nand_flash_s *nand_init(int manf_id, int chip_id) return s; } -void nand_done(struct nand_flash_s *s) +void nand_done(NANDFlashState *s) { if (s->bdrv) { bdrv_close(s->bdrv); @@ -515,7 +515,7 @@ void nand_done(struct nand_flash_s *s) #else /* Program a single page */ -static void glue(nand_blk_write_, PAGE_SIZE)(struct nand_flash_s *s) +static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s) { uint32_t off, page, sector, soff; uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200]; @@ -561,7 +561,7 @@ static void glue(nand_blk_write_, PAGE_SIZE)(struct nand_flash_s *s) } /* Erase a single block */ -static void glue(nand_blk_erase_, PAGE_SIZE)(struct nand_flash_s *s) +static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s) { uint32_t i, page, addr; uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, }; @@ -606,7 +606,7 @@ static void glue(nand_blk_erase_, PAGE_SIZE)(struct nand_flash_s *s) } } -static void glue(nand_blk_load_, PAGE_SIZE)(struct nand_flash_s *s, +static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s, uint32_t addr, int offset) { if (PAGE(addr) >= s->pages) @@ -638,7 +638,7 @@ static void glue(nand_blk_load_, PAGE_SIZE)(struct nand_flash_s *s, s->addr += PAGE_SIZE; } -static void glue(nand_init_, PAGE_SIZE)(struct nand_flash_s *s) +static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s) { s->oob_shift = PAGE_SHIFT - 5; s->pages = s->size >> PAGE_SHIFT; diff --git a/hw/nseries.c b/hw/nseries.c index ab75183fd4..55df20e6d1 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -40,14 +40,14 @@ struct n800_s { struct { void *opaque; uint32_t (*txrx)(void *opaque, uint32_t value, int len); - struct uwire_slave_s *chip; + uWireSlave *chip; } ts; i2c_bus *i2c; int keymap[0x80]; i2c_slave *kbd; - struct tusb_s *usb; + TUSBState *usb; void *retu; void *tahvo; void *nand; @@ -195,13 +195,13 @@ static void n8x0_i2c_setup(struct n800_s *s) } /* Touchscreen and keypad controller */ -static struct mouse_transform_info_s n800_pointercal = { +static MouseTransformInfo n800_pointercal = { .x = 800, .y = 480, .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 }, }; -static struct mouse_transform_info_s n810_pointercal = { +static MouseTransformInfo n810_pointercal = { .x = 800, .y = 480, .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 }, @@ -729,7 +729,7 @@ static void n8x0_cbus_setup(struct n800_s *s) qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0]; qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0]; - struct cbus_s *cbus = cbus_init(dat_out); + CBus *cbus = cbus_init(dat_out); omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk); omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat); @@ -764,7 +764,7 @@ static void n8x0_usb_setup(struct n800_s *s) { qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0]; qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0]; - struct tusb_s *tusb = tusb6010_init(tusb_irq); + TUSBState *tusb = tusb6010_init(tusb_irq); /* Using the NOR interface */ omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS, @@ -681,7 +681,7 @@ struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start); void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler); -struct uwire_slave_s { +struct uWireSlave { uint16_t (*receive)(void *opaque); void (*send)(void *opaque, uint16_t data); void *opaque; @@ -690,7 +690,7 @@ struct omap_uwire_s; struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, qemu_irq *irq, qemu_irq dma, omap_clk clk); void omap_uwire_attach(struct omap_uwire_s *s, - struct uwire_slave_s *slave, int chipselect); + uWireSlave *slave, int chipselect); struct omap_mcspi_s; struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, @@ -703,7 +703,7 @@ struct omap_rtc_s; struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, qemu_irq *irq, omap_clk clk); -struct i2s_codec_s { +struct I2SCodec { void *opaque; /* The CPU can call this if it is generating the clock signal on the @@ -730,7 +730,7 @@ struct i2s_codec_s { struct omap_mcbsp_s; struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base, qemu_irq *irq, qemu_irq *dma, omap_clk clk); -void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave); +void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); struct omap_lpg_s; struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk); diff --git a/hw/omap1.c b/hw/omap1.c index f6c0d9dad8..e6e0b3e3ae 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -2984,13 +2984,13 @@ struct omap_uwire_s { uint16_t control; uint16_t setup[5]; - struct uwire_slave_s *chip[4]; + uWireSlave *chip[4]; }; static void omap_uwire_transfer_start(struct omap_uwire_s *s) { int chipselect = (s->control >> 10) & 3; /* INDEX */ - struct uwire_slave_s *slave = s->chip[chipselect]; + uWireSlave *slave = s->chip[chipselect]; if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ if (s->control & (1 << 12)) /* CS_CMD */ @@ -3132,7 +3132,7 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, } void omap_uwire_attach(struct omap_uwire_s *s, - struct uwire_slave_s *slave, int chipselect) + uWireSlave *slave, int chipselect) { if (chipselect < 0 || chipselect > 3) { fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); @@ -3770,7 +3770,7 @@ struct omap_mcbsp_s { int tx_req; int rx_req; - struct i2s_codec_s *codec; + I2SCodec *codec; QEMUTimer *source_timer; QEMUTimer *sink_timer; }; @@ -4290,7 +4290,7 @@ static void omap_mcbsp_i2s_start(void *opaque, int line, int level) } } -void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave) +void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) { s->codec = slave; slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; diff --git a/hw/omap2.c b/hw/omap2.c index 82efbda88a..1cbbf4977b 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -4068,7 +4068,7 @@ struct omap_gpmc_s { int ecc_cs; int ecc_ptr; uint32_t ecc_cfg; - struct ecc_state_s ecc[9]; + ECCState ecc[9]; }; static void omap_gpmc_int_update(struct omap_gpmc_s *s) diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c index fd557c4c41..81c003cd2b 100644 --- a/hw/omap_mmc.c +++ b/hw/omap_mmc.c @@ -112,7 +112,7 @@ static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, { uint32_t rspstatus, mask; int rsplen, timeout; - struct sd_request_s request; + SDRequest request; uint8_t response[16]; if (init && cmd == 0) { diff --git a/hw/onenand.c b/hw/onenand.c index 4a5c7bd5d3..9803a0723f 100644 --- a/hw/onenand.c +++ b/hw/onenand.c @@ -31,7 +31,7 @@ /* Fixed */ #define BLOCK_SHIFT (PAGE_SHIFT + 6) -struct onenand_s { +typedef struct { uint32_t id; int shift; target_phys_addr_t base; @@ -59,14 +59,14 @@ struct onenand_s { uint16_t intstatus; uint16_t wpstatus; - struct ecc_state_s ecc; + ECCState ecc; int density_mask; int secs; int secs_cur; int blocks; uint8_t *blockwp; -}; +} OneNANDState; enum { ONEN_BUF_BLOCK = 0, @@ -99,7 +99,7 @@ enum { void onenand_base_update(void *opaque, target_phys_addr_t new) { - struct onenand_s *s = (struct onenand_s *) opaque; + OneNANDState *s = (OneNANDState *) opaque; s->base = new; @@ -118,19 +118,19 @@ void onenand_base_update(void *opaque, target_phys_addr_t new) void onenand_base_unmap(void *opaque) { - struct onenand_s *s = (struct onenand_s *) opaque; + OneNANDState *s = (OneNANDState *) opaque; cpu_register_physical_memory(s->base, 0x10000 << s->shift, IO_MEM_UNASSIGNED); } -static void onenand_intr_update(struct onenand_s *s) +static void onenand_intr_update(OneNANDState *s) { qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); } /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */ -static void onenand_reset(struct onenand_s *s, int cold) +static void onenand_reset(OneNANDState *s, int cold) { memset(&s->addr, 0, sizeof(s->addr)); s->command = 0; @@ -160,7 +160,7 @@ static void onenand_reset(struct onenand_s *s, int cold) } } -static inline int onenand_load_main(struct onenand_s *s, int sec, int secn, +static inline int onenand_load_main(OneNANDState *s, int sec, int secn, void *dest) { if (s->bdrv_cur) @@ -173,7 +173,7 @@ static inline int onenand_load_main(struct onenand_s *s, int sec, int secn, return 0; } -static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn, +static inline int onenand_prog_main(OneNANDState *s, int sec, int secn, void *src) { if (s->bdrv_cur) @@ -186,7 +186,7 @@ static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn, return 0; } -static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn, +static inline int onenand_load_spare(OneNANDState *s, int sec, int secn, void *dest) { uint8_t buf[512]; @@ -203,7 +203,7 @@ static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn, return 0; } -static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn, +static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn, void *src) { uint8_t buf[512]; @@ -221,7 +221,7 @@ static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn, return 0; } -static inline int onenand_erase(struct onenand_s *s, int sec, int num) +static inline int onenand_erase(OneNANDState *s, int sec, int num) { /* TODO: optimise */ uint8_t buf[512]; @@ -237,7 +237,7 @@ static inline int onenand_erase(struct onenand_s *s, int sec, int num) return 0; } -static void onenand_command(struct onenand_s *s, int cmd) +static void onenand_command(OneNANDState *s, int cmd) { int b; int sec; @@ -446,7 +446,7 @@ static void onenand_command(struct onenand_s *s, int cmd) static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) { - struct onenand_s *s = (struct onenand_s *) opaque; + OneNANDState *s = (OneNANDState *) opaque; int offset = addr >> s->shift; switch (offset) { @@ -511,7 +511,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) static void onenand_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct onenand_s *s = (struct onenand_s *) opaque; + OneNANDState *s = (OneNANDState *) opaque; int offset = addr >> s->shift; int sec; @@ -618,7 +618,7 @@ static CPUWriteMemoryFunc *onenand_writefn[] = { void *onenand_init(uint32_t id, int regshift, qemu_irq irq) { - struct onenand_s *s = (struct onenand_s *) qemu_mallocz(sizeof(*s)); + OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s)); int bdrv_index = drive_get_index(IF_MTD, 0, 0); uint32_t size = 1 << (24 + ((id >> 12) & 7)); void *ram; @@ -656,7 +656,7 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq) void *onenand_raw_otp(void *opaque) { - struct onenand_s *s = (struct onenand_s *) opaque; + OneNANDState *s = (OneNANDState *) opaque; return s->otp; } @@ -84,7 +84,7 @@ static CPUWriteMemoryFunc *static_writefn[] = { #define PALMTE_MMC2_GPIO 7 #define PALMTE_MMC3_GPIO 11 -static struct mouse_transform_info_s palmte_pointercal = { +static MouseTransformInfo palmte_pointercal = { .x = 320, .y = 320, .a = { -5909, 8, 22465308, 104, 7644, -1219972, 65536 }, @@ -92,7 +92,7 @@ static struct mouse_transform_info_s palmte_pointercal = { static void palmte_microwire_setup(struct omap_mpu_state_s *cpu) { - struct uwire_slave_s *tsc; + uWireSlave *tsc; AudioState *audio = 0; #ifdef HAS_AUDIO diff --git a/hw/pcmcia.h b/hw/pcmcia.h index 290a76f075..7171504fce 100644 --- a/hw/pcmcia.h +++ b/hw/pcmcia.h @@ -2,20 +2,20 @@ #include "qemu-common.h" -struct pcmcia_socket_s { +typedef struct { qemu_irq irq; int attached; const char *slot_string; const char *card_string; -}; +} PCMCIASocket; -void pcmcia_socket_register(struct pcmcia_socket_s *socket); -void pcmcia_socket_unregister(struct pcmcia_socket_s *socket); +void pcmcia_socket_register(PCMCIASocket *socket); +void pcmcia_socket_unregister(PCMCIASocket *socket); void pcmcia_info(Monitor *mon); -struct pcmcia_card_s { +struct PCMCIACardState { void *state; - struct pcmcia_socket_s *slot; + PCMCIASocket *slot; int (*attach)(void *state); int (*detach)(void *state); const uint8_t *cis; @@ -48,4 +48,4 @@ struct pcmcia_card_s { #define CISTPL_ENDMARK 0xff /* dscm1xxxx.c */ -struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv); +PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv); diff --git a/hw/pl181.c b/hw/pl181.c index b0709dc14f..b6a86d3a62 100644 --- a/hw/pl181.c +++ b/hw/pl181.c @@ -135,7 +135,7 @@ static uint32_t pl181_fifo_pop(pl181_state *s) static void pl181_send_command(pl181_state *s) { - struct sd_request_s request; + SDRequest request; uint8_t response[16]; int rlen; @@ -70,40 +70,40 @@ void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs); void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4); /* pxa2xx_gpio.c */ -struct pxa2xx_gpio_info_s; -struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, +typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; +PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base, CPUState *env, qemu_irq *pic, int lines); -qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s); -void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, +qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s); +void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s, int line, qemu_irq handler); -void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler); +void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler); /* pxa2xx_dma.c */ -struct pxa2xx_dma_state_s; -struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base, +typedef struct PXA2xxDMAState PXA2xxDMAState; +PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq); -struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base, +PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq); -void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on); +void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); /* pxa2xx_lcd.c */ -struct pxa2xx_lcdc_s; -struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, +typedef struct PXA2xxLCDState PXA2xxLCDState; +PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq); -void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler); +void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); void pxa2xx_lcdc_oritentation(void *opaque, int angle); /* pxa2xx_mmci.c */ -struct pxa2xx_mmci_s; -struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, +typedef struct PXA2xxMMCIState PXA2xxMMCIState; +PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, BlockDriverState *bd, qemu_irq irq, void *dma); -void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, +void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, qemu_irq coverswitch); /* pxa2xx_pcmcia.c */ -struct pxa2xx_pcmcia_s; -struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base); -int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card); +typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base); +int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); int pxa2xx_pcmcia_dettach(void *opaque); void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); @@ -112,40 +112,40 @@ struct keymap { int column; int row; }; -struct pxa2xx_keypad_s; -struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base, +typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; +PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, qemu_irq irq); -void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map, +void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map, int size); /* pxa2xx.c */ -struct pxa2xx_ssp_s; -void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, +typedef struct PXA2xxSSPState PXA2xxSSPState; +void pxa2xx_ssp_attach(PXA2xxSSPState *port, uint32_t (*readfn)(void *opaque), void (*writefn)(void *opaque, uint32_t value), void *opaque); -struct pxa2xx_i2c_s; -struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, +typedef struct PXA2xxI2CState PXA2xxI2CState; +PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, qemu_irq irq, uint32_t page_size); -i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s); +i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s); -struct pxa2xx_i2s_s; -struct pxa2xx_fir_s; +typedef struct PXA2xxI2SState PXA2xxI2SState; +typedef struct PXA2xxFIrState PXA2xxFIrState; -struct pxa2xx_state_s { +typedef struct { CPUState *env; qemu_irq *pic; qemu_irq reset; - struct pxa2xx_dma_state_s *dma; - struct pxa2xx_gpio_info_s *gpio; - struct pxa2xx_lcdc_s *lcd; - struct pxa2xx_ssp_s **ssp; - struct pxa2xx_i2c_s *i2c[2]; - struct pxa2xx_mmci_s *mmc; - struct pxa2xx_pcmcia_s *pcmcia[2]; - struct pxa2xx_i2s_s *i2s; - struct pxa2xx_fir_s *fir; - struct pxa2xx_keypad_s *kp; + PXA2xxDMAState *dma; + PXA2xxGPIOInfo *gpio; + PXA2xxLCDState *lcd; + PXA2xxSSPState **ssp; + PXA2xxI2CState *i2c[2]; + PXA2xxMMCIState *mmc; + PXA2xxPCMCIAState *pcmcia[2]; + PXA2xxI2SState *i2s; + PXA2xxFIrState *fir; + PXA2xxKeyPadState *kp; /* Power management */ target_phys_addr_t pm_base; @@ -189,11 +189,11 @@ struct pxa2xx_state_s { QEMUTimer *rtc_swal1; QEMUTimer *rtc_swal2; QEMUTimer *rtc_pi; -}; +} PXA2xxState; -struct pxa2xx_i2s_s { +struct PXA2xxI2SState { qemu_irq irq; - struct pxa2xx_dma_state_s *dma; + PXA2xxDMAState *dma; void (*data_req)(void *, int, int); uint32_t control[2]; @@ -215,8 +215,8 @@ struct pxa2xx_i2s_s { # define PA_FMT "0x%08lx" # define REG_FMT "0x" TARGET_FMT_plx -struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision); -struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size); +PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision); +PXA2xxState *pxa255_init(unsigned int sdram_size); /* usb-ohci.c */ void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 53d9b0b205..016716384a 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -89,7 +89,7 @@ static PXASSPDef pxa27x_ssp[] = { static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case PMCR ... PCMD31: @@ -108,7 +108,7 @@ static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case PMCR: @@ -147,7 +147,7 @@ static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = { static void pxa2xx_pm_save(QEMUFile *f, void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; int i; for (i = 0; i < 0x40; i ++) @@ -156,7 +156,7 @@ static void pxa2xx_pm_save(QEMUFile *f, void *opaque) static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; int i; for (i = 0; i < 0x40; i ++) @@ -172,7 +172,7 @@ static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id) static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case CCCR: @@ -193,7 +193,7 @@ static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case CCCR: @@ -228,7 +228,7 @@ static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = { static void pxa2xx_cm_save(QEMUFile *f, void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; int i; for (i = 0; i < 4; i ++) @@ -239,7 +239,7 @@ static void pxa2xx_cm_save(QEMUFile *f, void *opaque) static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; int i; for (i = 0; i < 4; i ++) @@ -252,7 +252,7 @@ static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id) static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (reg) { case 6: /* Clock Configuration register */ @@ -271,7 +271,7 @@ static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, uint32_t value) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; static const char *pwrmode[8] = { "Normal", "Idle", "Deep-idle", "Standby", "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", @@ -364,7 +364,7 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (reg) { case CPPMNC: @@ -389,7 +389,7 @@ static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm) static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm, uint32_t value) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (reg) { case CPPMNC: @@ -482,7 +482,7 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm, static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case MDCNFG ... SA1110: @@ -499,7 +499,7 @@ static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case MDCNFG ... SA1110: @@ -528,7 +528,7 @@ static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = { static void pxa2xx_mm_save(QEMUFile *f, void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; int i; for (i = 0; i < 0x1a; i ++) @@ -537,7 +537,7 @@ static void pxa2xx_mm_save(QEMUFile *f, void *opaque) static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; int i; for (i = 0; i < 0x1a; i ++) @@ -547,7 +547,7 @@ static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id) } /* Synchronous Serial Ports */ -struct pxa2xx_ssp_s { +struct PXA2xxSSPState { qemu_irq irq; int enable; @@ -616,7 +616,7 @@ struct pxa2xx_ssp_s { #define SSSR_BCE (1 << 23) #define SSSR_RW 0x00bc0080 -static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s) +static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) { int level = 0; @@ -632,7 +632,7 @@ static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s) qemu_set_irq(s->irq, !!level); } -static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s) +static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) { s->sssr &= ~(0xf << 12); /* Clear RFL */ s->sssr &= ~(0xf << 8); /* Clear TFL */ @@ -659,7 +659,7 @@ static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s) static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; uint32_t retval; switch (addr) { @@ -705,7 +705,7 @@ static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; switch (addr) { case SSCR0: @@ -796,7 +796,7 @@ static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, } } -void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, +void pxa2xx_ssp_attach(PXA2xxSSPState *port, uint32_t (*readfn)(void *opaque), void (*writefn)(void *opaque, uint32_t value), void *opaque) { @@ -824,7 +824,7 @@ static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = { static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) { - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; int i; qemu_put_be32(f, s->enable); @@ -846,7 +846,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; + PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; int i; s->enable = qemu_get_be32(f); @@ -886,12 +886,12 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ -static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s) +static inline void pxa2xx_rtc_int_update(PXA2xxState *s) { qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553)); } -static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s) +static void pxa2xx_rtc_hzupdate(PXA2xxState *s) { int64_t rt = qemu_get_clock(rt_clock); s->last_rcnr += ((rt - s->last_hz) << 15) / @@ -901,7 +901,7 @@ static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s) s->last_hz = rt; } -static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s) +static void pxa2xx_rtc_swupdate(PXA2xxState *s) { int64_t rt = qemu_get_clock(rt_clock); if (s->rtsr & (1 << 12)) @@ -909,7 +909,7 @@ static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s) s->last_sw = rt; } -static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s) +static void pxa2xx_rtc_piupdate(PXA2xxState *s) { int64_t rt = qemu_get_clock(rt_clock); if (s->rtsr & (1 << 15)) @@ -917,7 +917,7 @@ static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s) s->last_pi = rt; } -static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s, +static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s, uint32_t rtsr) { if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) @@ -962,7 +962,7 @@ static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s, static inline void pxa2xx_rtc_hz_tick(void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; s->rtsr |= (1 << 0); pxa2xx_rtc_alarm_update(s, s->rtsr); pxa2xx_rtc_int_update(s); @@ -970,7 +970,7 @@ static inline void pxa2xx_rtc_hz_tick(void *opaque) static inline void pxa2xx_rtc_rdal1_tick(void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; s->rtsr |= (1 << 4); pxa2xx_rtc_alarm_update(s, s->rtsr); pxa2xx_rtc_int_update(s); @@ -978,7 +978,7 @@ static inline void pxa2xx_rtc_rdal1_tick(void *opaque) static inline void pxa2xx_rtc_rdal2_tick(void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; s->rtsr |= (1 << 6); pxa2xx_rtc_alarm_update(s, s->rtsr); pxa2xx_rtc_int_update(s); @@ -986,7 +986,7 @@ static inline void pxa2xx_rtc_rdal2_tick(void *opaque) static inline void pxa2xx_rtc_swal1_tick(void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; s->rtsr |= (1 << 8); pxa2xx_rtc_alarm_update(s, s->rtsr); pxa2xx_rtc_int_update(s); @@ -994,7 +994,7 @@ static inline void pxa2xx_rtc_swal1_tick(void *opaque) static inline void pxa2xx_rtc_swal2_tick(void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; s->rtsr |= (1 << 10); pxa2xx_rtc_alarm_update(s, s->rtsr); pxa2xx_rtc_int_update(s); @@ -1002,7 +1002,7 @@ static inline void pxa2xx_rtc_swal2_tick(void *opaque) static inline void pxa2xx_rtc_pi_tick(void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; s->rtsr |= (1 << 13); pxa2xx_rtc_piupdate(s); s->last_rtcpicr = 0; @@ -1012,7 +1012,7 @@ static inline void pxa2xx_rtc_pi_tick(void *opaque) static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case RTTR: @@ -1058,7 +1058,7 @@ static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; switch (addr) { case RTTR: @@ -1170,7 +1170,7 @@ static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = { pxa2xx_rtc_write, }; -static void pxa2xx_rtc_init(struct pxa2xx_state_s *s) +static void pxa2xx_rtc_init(PXA2xxState *s) { struct tm tm; int wom; @@ -1201,7 +1201,7 @@ static void pxa2xx_rtc_init(struct pxa2xx_state_s *s) static void pxa2xx_rtc_save(QEMUFile *f, void *opaque) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; pxa2xx_rtc_hzupdate(s); pxa2xx_rtc_piupdate(s); @@ -1229,7 +1229,7 @@ static void pxa2xx_rtc_save(QEMUFile *f, void *opaque) static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; qemu_get_be32s(f, &s->rttr); qemu_get_be32s(f, &s->rtsr); @@ -1256,7 +1256,7 @@ static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id) } /* I2C Interface */ -struct pxa2xx_i2c_s { +struct PXA2xxI2CState { i2c_slave slave; i2c_bus *bus; qemu_irq irq; @@ -1274,7 +1274,7 @@ struct pxa2xx_i2c_s { #define ISR 0x98 /* I2C Status register */ #define ISAR 0xa0 /* I2C Slave Address register */ -static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s) +static void pxa2xx_i2c_update(PXA2xxI2CState *s) { uint16_t level = 0; level |= s->status & s->control & (1 << 10); /* BED */ @@ -1287,7 +1287,7 @@ static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s) /* These are only stubs now. */ static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event) { - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; + PXA2xxI2CState *s = (PXA2xxI2CState *) i2c; switch (event) { case I2C_START_SEND: @@ -1310,7 +1310,7 @@ static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event) static int pxa2xx_i2c_rx(i2c_slave *i2c) { - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; + PXA2xxI2CState *s = (PXA2xxI2CState *) i2c; if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) return 0; @@ -1324,7 +1324,7 @@ static int pxa2xx_i2c_rx(i2c_slave *i2c) static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data) { - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c; + PXA2xxI2CState *s = (PXA2xxI2CState *) i2c; if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) return 1; @@ -1339,7 +1339,7 @@ static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data) static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; addr -= s->offset; switch (addr) { @@ -1367,7 +1367,7 @@ static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; int ack; addr -= s->offset; @@ -1448,7 +1448,7 @@ static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = { static void pxa2xx_i2c_save(QEMUFile *f, void *opaque) { - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; qemu_put_be16s(f, &s->control); qemu_put_be16s(f, &s->status); @@ -1460,7 +1460,7 @@ static void pxa2xx_i2c_save(QEMUFile *f, void *opaque) static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque; + PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; if (version_id != 1) return -EINVAL; @@ -1474,13 +1474,13 @@ static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, +PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, qemu_irq irq, uint32_t region_size) { int iomemtype; /* FIXME: Should the slave device really be on a separate bus? */ - struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) - i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s)); + PXA2xxI2CState *s = (PXA2xxI2CState *) + i2c_slave_init(i2c_init_bus(), 0, sizeof(PXA2xxI2CState)); s->irq = irq; s->slave.event = pxa2xx_i2c_event; @@ -1500,13 +1500,13 @@ struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, return s; } -i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s) +i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s) { return s->bus; } /* PXA Inter-IC Sound Controller */ -static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s) +static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) { i2s->rx_len = 0; i2s->tx_len = 0; @@ -1523,7 +1523,7 @@ static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s) #define SACR_DREC(val) (val & (1 << 3)) #define SACR_DPRL(val) (val & (1 << 4)) -static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s) +static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) { int rfs, tfs; rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && @@ -1562,7 +1562,7 @@ static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s) static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; switch (addr) { case SACR0: @@ -1594,7 +1594,7 @@ static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; uint32_t *sample; switch (addr) { @@ -1660,7 +1660,7 @@ static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = { static void pxa2xx_i2s_save(QEMUFile *f, void *opaque) { - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; qemu_put_be32s(f, &s->control[0]); qemu_put_be32s(f, &s->control[1]); @@ -1676,7 +1676,7 @@ static void pxa2xx_i2s_save(QEMUFile *f, void *opaque) static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; qemu_get_be32s(f, &s->control[0]); qemu_get_be32s(f, &s->control[1]); @@ -1694,7 +1694,7 @@ static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id) static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) { - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; + PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; uint32_t *sample; /* Signal FIFO errors */ @@ -1714,12 +1714,12 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) pxa2xx_i2s_update(s); } -static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base, - qemu_irq irq, struct pxa2xx_dma_state_s *dma) +static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, + qemu_irq irq, PXA2xxDMAState *dma) { int iomemtype; - struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) - qemu_mallocz(sizeof(struct pxa2xx_i2s_s)); + PXA2xxI2SState *s = (PXA2xxI2SState *) + qemu_mallocz(sizeof(PXA2xxI2SState)); s->irq = irq; s->dma = dma; @@ -1738,9 +1738,9 @@ static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base, } /* PXA Fast Infra-red Communications Port */ -struct pxa2xx_fir_s { +struct PXA2xxFIrState { qemu_irq irq; - struct pxa2xx_dma_state_s *dma; + PXA2xxDMAState *dma; int enable; CharDriverState *chr; @@ -1752,7 +1752,7 @@ struct pxa2xx_fir_s { uint8_t rx_fifo[64]; }; -static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s) +static void pxa2xx_fir_reset(PXA2xxFIrState *s) { s->control[0] = 0x00; s->control[1] = 0x00; @@ -1762,7 +1762,7 @@ static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s) s->enable = 0; } -static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s) +static inline void pxa2xx_fir_update(PXA2xxFIrState *s) { static const int tresh[4] = { 8, 16, 32, 0 }; int intr = 0; @@ -1810,7 +1810,7 @@ static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s) static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) { - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; uint8_t ret; switch (addr) { @@ -1848,7 +1848,7 @@ static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; uint8_t ch; switch (addr) { @@ -1903,13 +1903,13 @@ static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = { static int pxa2xx_fir_is_empty(void *opaque) { - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; return (s->rx_len < 64); } static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) { - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; if (!(s->control[0] & (1 << 4))) /* RXE */ return; @@ -1935,7 +1935,7 @@ static void pxa2xx_fir_event(void *opaque, int event) static void pxa2xx_fir_save(QEMUFile *f, void *opaque) { - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; int i; qemu_put_be32(f, s->enable); @@ -1953,7 +1953,7 @@ static void pxa2xx_fir_save(QEMUFile *f, void *opaque) static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; + PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; int i; s->enable = qemu_get_be32(f); @@ -1972,13 +1972,13 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, - qemu_irq irq, struct pxa2xx_dma_state_s *dma, +static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, + qemu_irq irq, PXA2xxDMAState *dma, CharDriverState *chr) { int iomemtype; - struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) - qemu_mallocz(sizeof(struct pxa2xx_fir_s)); + PXA2xxFIrState *s = (PXA2xxFIrState *) + qemu_mallocz(sizeof(PXA2xxFIrState)); s->irq = irq; s->dma = dma; @@ -2001,7 +2001,7 @@ static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, static void pxa2xx_reset(void *opaque, int line, int level) { - struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + PXA2xxState *s = (PXA2xxState *) opaque; if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ cpu_reset(s->env); @@ -2010,13 +2010,13 @@ static void pxa2xx_reset(void *opaque, int line, int level) } /* Initialise a PXA270 integrated chip (ARM based core). */ -struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision) +PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) { - struct pxa2xx_state_s *s; - struct pxa2xx_ssp_s *ssp; + PXA2xxState *s; + PXA2xxSSPState *ssp; int iomemtype, i; int index; - s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s)); + s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState)); if (revision && strncmp(revision, "pxa27", 5)) { fprintf(stderr, "Machine requires a PXA27x processor.\n"); @@ -2094,10 +2094,10 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); for (i = 0; pxa27x_ssp[i].io_base; i ++); - s->ssp = (struct pxa2xx_ssp_s **) - qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i); - ssp = (struct pxa2xx_ssp_s *) - qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); + s->ssp = (PXA2xxSSPState **) + qemu_mallocz(sizeof(PXA2xxSSPState *) * i); + ssp = (PXA2xxSSPState *) + qemu_mallocz(sizeof(PXA2xxSSPState) * i); for (i = 0; pxa27x_ssp[i].io_base; i ++) { target_phys_addr_t ssp_base; s->ssp[i] = &ssp[i]; @@ -2139,14 +2139,14 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision } /* Initialise a PXA255 integrated chip (ARM based core). */ -struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size) +PXA2xxState *pxa255_init(unsigned int sdram_size) { - struct pxa2xx_state_s *s; - struct pxa2xx_ssp_s *ssp; + PXA2xxState *s; + PXA2xxSSPState *ssp; int iomemtype, i; int index; - s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s)); + s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState)); s->env = cpu_init("pxa255"); if (!s->env) { @@ -2216,10 +2216,10 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size) register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); for (i = 0; pxa255_ssp[i].io_base; i ++); - s->ssp = (struct pxa2xx_ssp_s **) - qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i); - ssp = (struct pxa2xx_ssp_s *) - qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); + s->ssp = (PXA2xxSSPState **) + qemu_mallocz(sizeof(PXA2xxSSPState *) * i); + ssp = (PXA2xxSSPState *) + qemu_mallocz(sizeof(PXA2xxSSPState) * i); for (i = 0; pxa255_ssp[i].io_base; i ++) { target_phys_addr_t ssp_base; s->ssp[i] = &ssp[i]; diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c index 2d38cc3993..0b350a2034 100644 --- a/hw/pxa2xx_dma.c +++ b/hw/pxa2xx_dma.c @@ -11,19 +11,19 @@ #include "hw.h" #include "pxa.h" -struct pxa2xx_dma_channel_s { +typedef struct { target_phys_addr_t descr; target_phys_addr_t src; target_phys_addr_t dest; uint32_t cmd; uint32_t state; int request; -}; +} PXA2xxDMAChannel; /* Allow the DMA to be used as a PIC. */ typedef void (*pxa2xx_dma_handler_t)(void *opaque, int irq, int level); -struct pxa2xx_dma_state_s { +struct PXA2xxDMAState { pxa2xx_dma_handler_t handler; qemu_irq irq; @@ -37,7 +37,7 @@ struct pxa2xx_dma_state_s { uint32_t pio; int channels; - struct pxa2xx_dma_channel_s *chan; + PXA2xxDMAChannel *chan; uint8_t *req; @@ -106,7 +106,7 @@ struct pxa2xx_dma_state_s { #define DCSR_NODESCFETCH (1 << 30) #define DCSR_RUN (1 << 31) -static inline void pxa2xx_dma_update(struct pxa2xx_dma_state_s *s, int ch) +static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch) { if (ch >= 0) { if ((s->chan[ch].state & DCSR_STOPIRQEN) && @@ -145,7 +145,7 @@ static inline void pxa2xx_dma_update(struct pxa2xx_dma_state_s *s, int ch) } static inline void pxa2xx_dma_descriptor_fetch( - struct pxa2xx_dma_state_s *s, int ch) + PXA2xxDMAState *s, int ch) { uint32_t desc[4]; target_phys_addr_t daddr = s->chan[ch].descr & ~0xf; @@ -170,14 +170,14 @@ static inline void pxa2xx_dma_descriptor_fetch( s->chan[ch].state |= DCSR_STARTINTR; } -static void pxa2xx_dma_run(struct pxa2xx_dma_state_s *s) +static void pxa2xx_dma_run(PXA2xxDMAState *s) { int c, srcinc, destinc; uint32_t n, size; uint32_t width; uint32_t length; uint8_t buffer[32]; - struct pxa2xx_dma_channel_s *ch; + PXA2xxDMAChannel *ch; if (s->running ++) return; @@ -254,7 +254,7 @@ static void pxa2xx_dma_run(struct pxa2xx_dma_state_s *s) static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; unsigned int channel; switch (offset) { @@ -308,7 +308,7 @@ static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) static void pxa2xx_dma_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; unsigned int channel; switch (offset) { @@ -430,7 +430,7 @@ static CPUWriteMemoryFunc *pxa2xx_dma_writefn[] = { static void pxa2xx_dma_save(QEMUFile *f, void *opaque) { - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; int i; qemu_put_be32(f, s->channels); @@ -456,7 +456,7 @@ static void pxa2xx_dma_save(QEMUFile *f, void *opaque) static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; + PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; int i; if (qemu_get_be32(f) != s->channels) @@ -483,21 +483,21 @@ static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base, +static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base, qemu_irq irq, int channels) { int i, iomemtype; - struct pxa2xx_dma_state_s *s; - s = (struct pxa2xx_dma_state_s *) - qemu_mallocz(sizeof(struct pxa2xx_dma_state_s)); + PXA2xxDMAState *s; + s = (PXA2xxDMAState *) + qemu_mallocz(sizeof(PXA2xxDMAState)); s->channels = channels; - s->chan = qemu_mallocz(sizeof(struct pxa2xx_dma_channel_s) * s->channels); + s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels); s->irq = irq; s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request; s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); - memset(s->chan, 0, sizeof(struct pxa2xx_dma_channel_s) * s->channels); + memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels); for (i = 0; i < s->channels; i ++) s->chan[i].state = DCSR_STOPINTR; @@ -512,19 +512,19 @@ static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base, return s; } -struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base, +PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq) { return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS); } -struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base, +PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq) { return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS); } -void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on) +void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on) { int ch; if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index 9d939cbfa0..9749cb791a 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -12,7 +12,7 @@ #define PXA2XX_GPIO_BANKS 4 -struct pxa2xx_gpio_info_s { +struct PXA2xxGPIOInfo { qemu_irq *pic; int lines; CPUState *cpu_env; @@ -63,7 +63,7 @@ static struct { PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) }; -static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s) +static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) { if (s->status[0] & (1 << 0)) qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]); @@ -88,7 +88,7 @@ static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { static void pxa2xx_gpio_set(void *opaque, int line, int level) { - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; int bank; uint32_t mask; @@ -118,7 +118,7 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level) cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB); } -static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) { +static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { uint32_t level, diff; int i, bit, line; for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { @@ -136,7 +136,7 @@ static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) { static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; uint32_t ret; int bank; if (offset >= 0x200) @@ -188,7 +188,7 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; int bank; if (offset >= 0x200) return; @@ -251,7 +251,7 @@ static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = { static void pxa2xx_gpio_save(QEMUFile *f, void *opaque) { - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; int i; qemu_put_be32(f, s->lines); @@ -272,7 +272,7 @@ static void pxa2xx_gpio_save(QEMUFile *f, void *opaque) static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; + PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; int i; if (qemu_get_be32(f) != s->lines) @@ -294,15 +294,15 @@ static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, +PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base, CPUState *env, qemu_irq *pic, int lines) { int iomemtype; - struct pxa2xx_gpio_info_s *s; + PXA2xxGPIOInfo *s; - s = (struct pxa2xx_gpio_info_s *) - qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s)); - memset(s, 0, sizeof(struct pxa2xx_gpio_info_s)); + s = (PXA2xxGPIOInfo *) + qemu_mallocz(sizeof(PXA2xxGPIOInfo)); + memset(s, 0, sizeof(PXA2xxGPIOInfo)); s->pic = pic; s->lines = lines; s->cpu_env = env; @@ -318,12 +318,12 @@ struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, return s; } -qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s) +qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s) { return s->in; } -void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, +void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s, int line, qemu_irq handler) { if (line >= s->lines) { @@ -338,7 +338,7 @@ void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, * Registers a callback to notify on GPLR reads. This normally * shouldn't be needed but it is used for the hack on Spitz machines. */ -void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler) +void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler) { s->read_notify = handler; } diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c index 965fa354e4..07f8d20a3f 100644 --- a/hw/pxa2xx_keypad.c +++ b/hw/pxa2xx_keypad.c @@ -79,7 +79,7 @@ #define PXAKBD_MAXROW 8 #define PXAKBD_MAXCOL 8 -struct pxa2xx_keypad_s{ +struct PXA2xxKeyPadState { qemu_irq irq; struct keymap *map; @@ -95,7 +95,7 @@ struct pxa2xx_keypad_s{ uint32_t kpkdi; }; -static void pxa27x_keyboard_event (struct pxa2xx_keypad_s *kp, int keycode) +static void pxa27x_keyboard_event (PXA2xxKeyPadState *kp, int keycode) { int row, col,rel; @@ -156,7 +156,7 @@ out: static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque; + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque; uint32_t tmp; switch (offset) { @@ -218,7 +218,7 @@ static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset) static void pxa2xx_keypad_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque; + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque; switch (offset) { case KPC: @@ -271,7 +271,7 @@ static CPUWriteMemoryFunc *pxa2xx_keypad_writefn[] = { static void pxa2xx_keypad_save(QEMUFile *f, void *opaque) { - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque; + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque; qemu_put_be32s(f, &s->kpc); qemu_put_be32s(f, &s->kpdk); @@ -288,7 +288,7 @@ static void pxa2xx_keypad_save(QEMUFile *f, void *opaque) static int pxa2xx_keypad_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_keypad_s *s = (struct pxa2xx_keypad_s *) opaque; + PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque; qemu_get_be32s(f, &s->kpc); qemu_get_be32s(f, &s->kpdk); @@ -304,13 +304,13 @@ static int pxa2xx_keypad_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base, +PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, qemu_irq irq) { int iomemtype; - struct pxa2xx_keypad_s *s; + PXA2xxKeyPadState *s; - s = (struct pxa2xx_keypad_s *) qemu_mallocz(sizeof(struct pxa2xx_keypad_s)); + s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState)); s->irq = irq; iomemtype = cpu_register_io_memory(0, pxa2xx_keypad_readfn, @@ -323,7 +323,7 @@ struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base, return s; } -void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map, +void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map, int size) { if(!map || size < 0x80) { diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c index 4b9f4282a9..12bfc13036 100644 --- a/hw/pxa2xx_lcd.c +++ b/hw/pxa2xx_lcd.c @@ -15,7 +15,7 @@ #include "sysemu.h" #include "framebuffer.h" -struct pxa2xx_lcdc_s { +struct PXA2xxLCDState { qemu_irq irq; int irqlevel; @@ -55,7 +55,7 @@ struct pxa2xx_lcdc_s { int up; uint8_t palette[1024]; uint8_t pbuffer[1024]; - void (*redraw)(struct pxa2xx_lcdc_s *s, target_phys_addr_t addr, + void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr, int *miny, int *maxy); target_phys_addr_t descriptor; @@ -68,12 +68,12 @@ struct pxa2xx_lcdc_s { int orientation; }; -struct __attribute__ ((__packed__)) pxa_frame_descriptor_s { +typedef struct __attribute__ ((__packed__)) { uint32_t fdaddr; uint32_t fsaddr; uint32_t fidr; uint32_t ldcmd; -}; +} PXAFrameDescriptor; #define LCCR0 0x000 /* LCD Controller Control register 0 */ #define LCCR1 0x004 /* LCD Controller Control register 1 */ @@ -177,7 +177,7 @@ struct __attribute__ ((__packed__)) pxa_frame_descriptor_s { #define LDCMD_PAL (1 << 26) /* Route internal interrupt lines to the global IC */ -static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s) +static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s) { int level = 0; level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM); @@ -197,7 +197,7 @@ static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s) } /* Set Branch Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch) +static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch) { int unmasked; if (ch == 0) { @@ -217,7 +217,7 @@ static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch) } /* Set Start Of Frame Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch) +static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch) { int unmasked; if (!(s->dma_ch[ch].command & LDCMD_SOFINT)) @@ -240,7 +240,7 @@ static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch) } /* Set End Of Frame Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch) +static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch) { int unmasked; if (!(s->dma_ch[ch].command & LDCMD_EOFINT)) @@ -263,7 +263,7 @@ static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch) } /* Set Bus Error Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch) +static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch) { s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER; if (s->irqlevel) @@ -273,7 +273,7 @@ static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch) } /* Set Read Status interrupt high and poke associated registers */ -static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s) +static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s) { s->status[0] |= LCSR0_RDST; if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM)) @@ -281,9 +281,9 @@ static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s) } /* Load new Frame Descriptors from DMA */ -static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) +static void pxa2xx_descriptor_load(PXA2xxLCDState *s) { - struct pxa_frame_descriptor_s desc; + PXAFrameDescriptor desc; target_phys_addr_t descptr; int i; @@ -315,7 +315,7 @@ static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int ch; switch (offset) { @@ -409,7 +409,7 @@ static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int ch; switch (offset) { @@ -572,7 +572,7 @@ static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = { }; /* Load new palette for a given DMA channel, convert to internal format */ -static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp) +static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp) { int i, n, format, r, g, b, alpha; uint32_t *dest, *src; @@ -663,7 +663,7 @@ static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp) } } -static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s, +static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s, target_phys_addr_t addr, int *miny, int *maxy) { int src_width, dest_width; @@ -690,7 +690,7 @@ static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s, fn, s->dma_ch[0].palette, miny, maxy); } -static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s, +static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s, target_phys_addr_t addr, int *miny, int *maxy) { int src_width, dest_width; @@ -718,7 +718,7 @@ static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s, miny, maxy); } -static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s) +static void pxa2xx_lcdc_resize(PXA2xxLCDState *s) { int width, height; if (!(s->control[0] & LCCR0_ENB)) @@ -740,7 +740,7 @@ static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s) static void pxa2xx_update_display(void *opaque) { - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; target_phys_addr_t fbptr; int miny, maxy; int ch; @@ -807,7 +807,7 @@ static void pxa2xx_update_display(void *opaque) static void pxa2xx_invalidate_display(void *opaque) { - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; s->invalidated = 1; } @@ -818,7 +818,7 @@ static void pxa2xx_screen_dump(void *opaque, const char *filename) static void pxa2xx_lcdc_orientation(void *opaque, int angle) { - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; if (angle) { s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert; @@ -833,7 +833,7 @@ static void pxa2xx_lcdc_orientation(void *opaque, int angle) static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) { - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int i; qemu_put_be32(f, s->irqlevel); @@ -868,7 +868,7 @@ static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; + PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int i; s->irqlevel = qemu_get_be32(f); @@ -917,12 +917,12 @@ static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) #define BITS 32 #include "pxa2xx_template.h" -struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) +PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) { int iomemtype; - struct pxa2xx_lcdc_s *s; + PXA2xxLCDState *s; - s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s)); + s = (PXA2xxLCDState *) qemu_mallocz(sizeof(PXA2xxLCDState)); s->invalidated = 1; s->irq = irq; @@ -976,7 +976,7 @@ struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) return s; } -void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler) +void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler) { s->vsync_cb = handler; } diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c index 74e36273be..8ce28f7260 100644 --- a/hw/pxa2xx_mmci.c +++ b/hw/pxa2xx_mmci.c @@ -11,7 +11,7 @@ #include "pxa.h" #include "sd.h" -struct pxa2xx_mmci_s { +struct PXA2xxMMCIState { qemu_irq irq; void *dma; @@ -96,22 +96,22 @@ struct pxa2xx_mmci_s { #define PRTBUF_PRT_BUF (1 << 0) /* Route internal interrupt lines to the global IC and DMA */ -static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s) +static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s) { uint32_t mask = s->intmask; if (s->cmdat & CMDAT_DMA_EN) { mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ; - pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma, + pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ)); - pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma, + pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ)); } qemu_set_irq(s->irq, !!(s->intreq & ~mask)); } -static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s) +static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s) { if (!s->active) return; @@ -147,10 +147,10 @@ static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s) pxa2xx_mmci_int_update(s); } -static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s) +static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s) { int rsplen, i; - struct sd_request_s request; + SDRequest request; uint8_t response[16]; s->active = 1; @@ -213,7 +213,7 @@ static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s) static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; uint32_t ret; switch (offset) { @@ -275,7 +275,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) static void pxa2xx_mmci_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; switch (offset) { case MMC_STRPCL: @@ -384,21 +384,21 @@ static void pxa2xx_mmci_write(void *opaque, static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 1; return pxa2xx_mmci_read(opaque, offset); } static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 2; return pxa2xx_mmci_read(opaque, offset); } static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 4; return pxa2xx_mmci_read(opaque, offset); } @@ -412,7 +412,7 @@ static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = { static void pxa2xx_mmci_writeb(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 1; pxa2xx_mmci_write(opaque, offset, value); } @@ -420,7 +420,7 @@ static void pxa2xx_mmci_writeb(void *opaque, static void pxa2xx_mmci_writeh(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 2; pxa2xx_mmci_write(opaque, offset, value); } @@ -428,7 +428,7 @@ static void pxa2xx_mmci_writeh(void *opaque, static void pxa2xx_mmci_writew(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; s->ac_width = 4; pxa2xx_mmci_write(opaque, offset, value); } @@ -441,7 +441,7 @@ static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = { static void pxa2xx_mmci_save(QEMUFile *f, void *opaque) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; int i; qemu_put_be32s(f, &s->status); @@ -475,7 +475,7 @@ static void pxa2xx_mmci_save(QEMUFile *f, void *opaque) static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; + PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; int i; qemu_get_be32s(f, &s->status); @@ -517,13 +517,13 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, +PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, BlockDriverState *bd, qemu_irq irq, void *dma) { int iomemtype; - struct pxa2xx_mmci_s *s; + PXA2xxMMCIState *s; - s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s)); + s = (PXA2xxMMCIState *) qemu_mallocz(sizeof(PXA2xxMMCIState)); s->irq = irq; s->dma = dma; @@ -540,7 +540,7 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, return s; } -void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, +void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, qemu_irq coverswitch) { sd_set_cb(s->card, readonly, coverswitch); diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c index b26c59753d..6e9c956e78 100644 --- a/hw/pxa2xx_pcmcia.c +++ b/hw/pxa2xx_pcmcia.c @@ -11,9 +11,9 @@ #include "pcmcia.h" #include "pxa.h" -struct pxa2xx_pcmcia_s { - struct pcmcia_socket_s slot; - struct pcmcia_card_s *card; +struct PXA2xxPCMCIAState { + PCMCIASocket slot; + PCMCIACardState *card; qemu_irq irq; qemu_irq cd_irq; @@ -22,7 +22,7 @@ struct pxa2xx_pcmcia_s { static uint32_t pxa2xx_pcmcia_common_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (s->slot.attached) { return s->card->common_read(s->card->state, offset); @@ -34,7 +34,7 @@ static uint32_t pxa2xx_pcmcia_common_read(void *opaque, static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (s->slot.attached) { s->card->common_write(s->card->state, offset, value); @@ -44,7 +44,7 @@ static void pxa2xx_pcmcia_common_write(void *opaque, static uint32_t pxa2xx_pcmcia_attr_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (s->slot.attached) { return s->card->attr_read(s->card->state, offset); @@ -56,7 +56,7 @@ static uint32_t pxa2xx_pcmcia_attr_read(void *opaque, static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (s->slot.attached) { s->card->attr_write(s->card->state, offset, value); @@ -66,7 +66,7 @@ static void pxa2xx_pcmcia_attr_write(void *opaque, static uint32_t pxa2xx_pcmcia_io_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (s->slot.attached) { return s->card->io_read(s->card->state, offset); @@ -78,7 +78,7 @@ static uint32_t pxa2xx_pcmcia_io_read(void *opaque, static void pxa2xx_pcmcia_io_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (s->slot.attached) { s->card->io_write(s->card->state, offset, value); @@ -123,20 +123,20 @@ static CPUWriteMemoryFunc *pxa2xx_pcmcia_io_writefn[] = { static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (!s->irq) return; qemu_set_irq(s->irq, level); } -struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base) +PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base) { int iomemtype; - struct pxa2xx_pcmcia_s *s; + PXA2xxPCMCIAState *s; - s = (struct pxa2xx_pcmcia_s *) - qemu_mallocz(sizeof(struct pxa2xx_pcmcia_s)); + s = (PXA2xxPCMCIAState *) + qemu_mallocz(sizeof(PXA2xxPCMCIAState)); /* Socket I/O Memory Space */ iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn, @@ -166,9 +166,9 @@ struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base) } /* Insert a new card into a slot */ -int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card) +int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (s->slot.attached) return -EEXIST; @@ -188,7 +188,7 @@ int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card) /* Eject card from the slot */ int pxa2xx_pcmcia_dettach(void *opaque) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; if (!s->slot.attached) return -ENOENT; @@ -209,7 +209,7 @@ int pxa2xx_pcmcia_dettach(void *opaque) /* Who to notify on card events */ void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq) { - struct pxa2xx_pcmcia_s *s = (struct pxa2xx_pcmcia_s *) opaque; + PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; s->irq = irq; s->cd_irq = cd_irq; } diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index e8a601dbb7..aa17ba37fb 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -30,19 +30,19 @@ #define PXA2XX_PIC_SRCS 40 -struct pxa2xx_pic_state_s { +typedef struct { CPUState *cpu_env; uint32_t int_enabled[2]; uint32_t int_pending[2]; uint32_t is_fiq[2]; uint32_t int_idle; uint32_t priority[PXA2XX_PIC_SRCS]; -}; +} PXA2xxPICState; static void pxa2xx_pic_update(void *opaque) { uint32_t mask[2]; - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; + PXA2xxPICState *s = (PXA2xxPICState *) opaque; if (s->cpu_env->halted) { mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle); @@ -69,7 +69,7 @@ static void pxa2xx_pic_update(void *opaque) * IRQ/FIQ distinction as in PXA Developer Manual. */ static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) { - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; + PXA2xxPICState *s = (PXA2xxPICState *) opaque; int int_set = (irq >= 32); irq &= 31; @@ -81,7 +81,7 @@ static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) pxa2xx_pic_update(opaque); } -static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) { +static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) { int i, int_set, irq; uint32_t bit, mask[2]; uint32_t ichp = 0x003f003f; /* Both IDs invalid */ @@ -115,7 +115,7 @@ static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) { static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset) { - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; + PXA2xxPICState *s = (PXA2xxPICState *) opaque; switch (offset) { case ICIP: /* IRQ Pending register */ @@ -155,7 +155,7 @@ static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset) static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset, uint32_t value) { - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; + PXA2xxPICState *s = (PXA2xxPICState *) opaque; switch (offset) { case ICMR: /* Mask register */ @@ -243,7 +243,7 @@ static CPUWriteMemoryFunc *pxa2xx_pic_writefn[] = { static void pxa2xx_pic_save(QEMUFile *f, void *opaque) { - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; + PXA2xxPICState *s = (PXA2xxPICState *) opaque; int i; for (i = 0; i < 2; i ++) @@ -259,7 +259,7 @@ static void pxa2xx_pic_save(QEMUFile *f, void *opaque) static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) { - struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; + PXA2xxPICState *s = (PXA2xxPICState *) opaque; int i; for (i = 0; i < 2; i ++) @@ -278,12 +278,12 @@ static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) { - struct pxa2xx_pic_state_s *s; + PXA2xxPICState *s; int iomemtype; qemu_irq *qi; - s = (struct pxa2xx_pic_state_s *) - qemu_mallocz(sizeof(struct pxa2xx_pic_state_s)); + s = (PXA2xxPICState *) + qemu_mallocz(sizeof(PXA2xxPICState)); if (!s) return NULL; diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c index 52cf58e2fb..3725dd1ed5 100644 --- a/hw/pxa2xx_timer.c +++ b/hw/pxa2xx_timer.c @@ -59,31 +59,31 @@ static int pxa2xx_timer4_freq[8] = { [5 ... 7] = 0, }; -struct pxa2xx_timer0_s { +typedef struct { uint32_t value; int level; qemu_irq irq; QEMUTimer *qtimer; int num; void *info; -}; +} PXA2xxTimer0; -struct pxa2xx_timer4_s { - struct pxa2xx_timer0_s tm; +typedef struct { + PXA2xxTimer0 tm; int32_t oldclock; int32_t clock; uint64_t lastload; uint32_t freq; uint32_t control; -}; +} PXA2xxTimer4; typedef struct { int32_t clock; int32_t oldclock; uint64_t lastload; uint32_t freq; - struct pxa2xx_timer0_s timer[4]; - struct pxa2xx_timer4_s *tm4; + PXA2xxTimer0 timer[4]; + PXA2xxTimer4 *tm4; uint32_t events; uint32_t irq_enabled; uint32_t reset3; @@ -332,7 +332,7 @@ static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = { static void pxa2xx_timer_tick(void *opaque) { - struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque; + PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque; pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info; if (i->irq_enabled & (1 << t->num)) { @@ -350,7 +350,7 @@ static void pxa2xx_timer_tick(void *opaque) static void pxa2xx_timer_tick4(void *opaque) { - struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque; + PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque; pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info; pxa2xx_timer_tick(&t->tm); @@ -474,8 +474,8 @@ void pxa27x_timer_init(target_phys_addr_t base, pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs); int i; s->freq = PXA27X_FREQ; - s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 * - sizeof(struct pxa2xx_timer4_s)); + s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 * + sizeof(PXA2xxTimer4)); for (i = 0; i < 8; i ++) { s->tm4[i].tm.value = 0; s->tm4[i].tm.irq = irq4; @@ -301,7 +301,7 @@ static void sd_set_sdstatus(SDState *sd) memset(sd->sd_status, 0, 64); } -static int sd_req_crc_validate(struct sd_request_s *req) +static int sd_req_crc_validate(SDRequest *req) { uint8_t buffer[5]; buffer[0] = 0x40 | req->cmd; @@ -580,7 +580,7 @@ static void sd_lock_command(SDState *sd) } static sd_rsp_type_t sd_normal_command(SDState *sd, - struct sd_request_s req) + SDRequest req) { uint32_t rca = 0x0000; @@ -1119,7 +1119,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, } static sd_rsp_type_t sd_app_command(SDState *sd, - struct sd_request_s req) { + SDRequest req) { uint32_t rca; if (sd_cmd_type[req.cmd] == sd_ac || sd_cmd_type[req.cmd] == sd_adtc) @@ -1228,7 +1228,7 @@ static sd_rsp_type_t sd_app_command(SDState *sd, return sd_r0; } -int sd_do_command(SDState *sd, struct sd_request_s *req, +int sd_do_command(SDState *sd, SDRequest *req, uint8_t *response) { uint32_t last_status = sd->card_status; sd_rsp_type_t rtype; @@ -59,16 +59,16 @@ typedef enum { sd_adtc, /* addressed with data transfer */ } sd_cmd_type_t; -struct sd_request_s { +typedef struct { uint8_t cmd; uint32_t arg; uint8_t crc; -}; +} SDRequest; typedef struct SDState SDState; SDState *sd_init(BlockDriverState *bs, int is_spi); -int sd_do_command(SDState *sd, struct sd_request_s *req, +int sd_do_command(SDState *sd, SDRequest *req, uint8_t *response); void sd_write_data(SDState *sd, uint8_t value); uint8_t sd_read_data(SDState *sd); diff --git a/hw/sharpsl.h b/hw/sharpsl.h index 4d5cee98da..c5ccf791f6 100644 --- a/hw/sharpsl.h +++ b/hw/sharpsl.h @@ -10,11 +10,12 @@ fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__) /* zaurus.c */ -struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu, +typedef struct ScoopInfo ScoopInfo; +ScoopInfo *scoop_init(PXA2xxState *cpu, int instance, target_phys_addr_t target_base); void scoop_gpio_set(void *opaque, int line, int level); -qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s); -void scoop_gpio_out_set(struct scoop_info_s *s, int line, +qemu_irq *scoop_gpio_in_get(ScoopInfo *s); +void scoop_gpio_out_set(ScoopInfo *s, int line, qemu_irq handler); #define SL_PXA_PARAM_BASE 0xa0000a00 diff --git a/hw/spitz.c b/hw/spitz.c index c4133fdd3a..3c155a4b35 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -47,15 +47,15 @@ #define FLASHCTL_RYBY (1 << 5) #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) -struct sl_nand_s { - struct nand_flash_s *nand; +typedef struct { + NANDFlashState *nand; uint8_t ctl; - struct ecc_state_s ecc; -}; + ECCState ecc; +} SLNANDState; static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) { - struct sl_nand_s *s = (struct sl_nand_s *) opaque; + SLNANDState *s = (SLNANDState *) opaque; int ryby; switch (addr) { @@ -93,7 +93,7 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) { - struct sl_nand_s *s = (struct sl_nand_s *) opaque; + SLNANDState *s = (SLNANDState *) opaque; if (addr == FLASH_FLASHIO) return ecc_digest(&s->ecc, nand_getio(s->nand)) | @@ -105,7 +105,7 @@ static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) static void sl_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct sl_nand_s *s = (struct sl_nand_s *) opaque; + SLNANDState *s = (SLNANDState *) opaque; switch (addr) { case FLASH_ECCCLRR: @@ -134,7 +134,7 @@ static void sl_writeb(void *opaque, target_phys_addr_t addr, static void sl_save(QEMUFile *f, void *opaque) { - struct sl_nand_s *s = (struct sl_nand_s *) opaque; + SLNANDState *s = (SLNANDState *) opaque; qemu_put_8s(f, &s->ctl); ecc_put(f, &s->ecc); @@ -142,7 +142,7 @@ static void sl_save(QEMUFile *f, void *opaque) static int sl_load(QEMUFile *f, void *opaque, int version_id) { - struct sl_nand_s *s = (struct sl_nand_s *) opaque; + SLNANDState *s = (SLNANDState *) opaque; qemu_get_8s(f, &s->ctl); ecc_get(f, &s->ecc); @@ -155,10 +155,10 @@ enum { FLASH_1024M, }; -static void sl_flash_register(struct pxa2xx_state_s *cpu, int size) +static void sl_flash_register(PXA2xxState *cpu, int size) { int iomemtype; - struct sl_nand_s *s; + SLNANDState *s; CPUReadMemoryFunc *sl_readfn[] = { sl_readb, sl_readb, @@ -170,7 +170,7 @@ static void sl_flash_register(struct pxa2xx_state_s *cpu, int size) sl_writeb, }; - s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s)); + s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState)); s->ctl = 0; if (size == FLASH_128M) s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73); @@ -222,7 +222,7 @@ static const int spitz_gpiomap[5] = { }; static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; -struct spitz_keyboard_s { +typedef struct { qemu_irq sense[SPITZ_KEY_SENSE_NUM]; qemu_irq *strobe; qemu_irq gpiomap[5]; @@ -237,9 +237,9 @@ struct spitz_keyboard_s { uint8_t fifo[16]; int fifopos, fifolen; QEMUTimer *kbdtimer; -}; +} SpitzKeyboardState; -static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s) +static void spitz_keyboard_sense_update(SpitzKeyboardState *s) { int i; uint16_t strobe, sense = 0; @@ -258,7 +258,7 @@ static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s) static void spitz_keyboard_strobe(void *opaque, int line, int level) { - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; if (level) s->strobe_state |= 1 << line; @@ -267,7 +267,7 @@ static void spitz_keyboard_strobe(void *opaque, int line, int level) spitz_keyboard_sense_update(s); } -static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode) +static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode) { int spitz_keycode = s->keymap[keycode & 0x7f]; if (spitz_keycode == -1) @@ -294,7 +294,7 @@ static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode) #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c -static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode) +static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode) { uint16_t code; int mapcode; @@ -386,7 +386,7 @@ static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode) static void spitz_keyboard_tick(void *opaque) { - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; if (s->fifolen) { spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); @@ -398,7 +398,7 @@ static void spitz_keyboard_tick(void *opaque) qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32); } -static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s) +static void spitz_keyboard_pre_map(SpitzKeyboardState *s) { int i; for (i = 0; i < 0x100; i ++) @@ -450,7 +450,7 @@ static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s) static void spitz_keyboard_save(QEMUFile *f, void *opaque) { - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; int i; qemu_put_be16s(f, &s->sense_state); @@ -461,7 +461,7 @@ static void spitz_keyboard_save(QEMUFile *f, void *opaque) static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) { - struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; + SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; int i; qemu_get_be16s(f, &s->sense_state); @@ -480,14 +480,14 @@ static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static void spitz_keyboard_register(struct pxa2xx_state_s *cpu) +static void spitz_keyboard_register(PXA2xxState *cpu) { int i, j; - struct spitz_keyboard_s *s; + SpitzKeyboardState *s; - s = (struct spitz_keyboard_s *) - qemu_mallocz(sizeof(struct spitz_keyboard_s)); - memset(s, 0, sizeof(struct spitz_keyboard_s)); + s = (SpitzKeyboardState *) + qemu_mallocz(sizeof(SpitzKeyboardState)); + memset(s, 0, sizeof(SpitzKeyboardState)); for (i = 0; i < 0x80; i ++) s->keymap[i] = -1; @@ -527,7 +527,7 @@ static void spitz_keyboard_register(struct pxa2xx_state_s *cpu) static int bl_intensity, bl_power; -static void spitz_bl_update(struct pxa2xx_state_s *s) +static void spitz_bl_update(PXA2xxState *s) { if (bl_power && bl_intensity) zaurus_printf("LCD Backlight now at %i/63\n", bl_intensity); @@ -545,13 +545,13 @@ static inline void spitz_bl_bit5(void *opaque, int line, int level) bl_intensity |= 0x20; if (bl_power && prev != bl_intensity) - spitz_bl_update((struct pxa2xx_state_s *) opaque); + spitz_bl_update((PXA2xxState *) opaque); } static inline void spitz_bl_power(void *opaque, int line, int level) { bl_power = !!level; - spitz_bl_update((struct pxa2xx_state_s *) opaque); + spitz_bl_update((PXA2xxState *) opaque); } static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd) @@ -572,7 +572,7 @@ static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd) bl_intensity &= ~0x1f; bl_intensity |= value; if (bl_power) - spitz_bl_update((struct pxa2xx_state_s *) opaque); + spitz_bl_update((PXA2xxState *) opaque); break; case LCDTG_POWERREG0: @@ -591,8 +591,8 @@ static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd) #define SPITZ_GPIO_TP_INT 11 static int lcd_en, ads_en, max_en; -static struct max111x_s *max1111; -static struct ads7846_state_s *ads7846; +static MAX111xState *max1111; +static ADS7846State *ads7846; /* "Demux" the signal based on current chipselect */ static uint32_t corgi_ssp_read(void *opaque) @@ -670,7 +670,7 @@ static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static void spitz_ssp_attach(struct pxa2xx_state_s *cpu) +static void spitz_ssp_attach(PXA2xxState *cpu) { qemu_irq *chipselects; @@ -699,9 +699,9 @@ static void spitz_ssp_attach(struct pxa2xx_state_s *cpu) /* CF Microdrive */ -static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu, int slot) +static void spitz_microdrive_attach(PXA2xxState *cpu, int slot) { - struct pcmcia_card_s *md; + PCMCIACardState *md; int index; BlockDriverState *bs; @@ -734,7 +734,7 @@ static void spitz_wm8750_addr(void *opaque, int line, int level) } #endif -static void spitz_i2c_setup(struct pxa2xx_state_s *cpu) +static void spitz_i2c_setup(PXA2xxState *cpu) { /* Attach the CPU on one end of our I2C bus. */ i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]); @@ -760,7 +760,7 @@ static void spitz_i2c_setup(struct pxa2xx_state_s *cpu) #endif } -static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu) +static void spitz_akita_i2c_setup(PXA2xxState *cpu) { /* Attach a Max7310 to Akita I2C bus. */ i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])), @@ -811,8 +811,8 @@ static void spitz_out_switch(void *opaque, int line, int level) #define SPITZ_SCP2_BACKLIGHT_ON 8 #define SPITZ_SCP2_MIC_BIAS 9 -static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu, - struct scoop_info_s *scp0, struct scoop_info_s *scp1) +static void spitz_scoop_gpio_setup(PXA2xxState *cpu, + ScoopInfo *scp0, ScoopInfo *scp1) { qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8); @@ -843,12 +843,12 @@ static int spitz_hsync; static void spitz_lcd_hsync_handler(void *opaque, int line, int level) { - struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; + PXA2xxState *cpu = (PXA2xxState *) opaque; qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync); spitz_hsync ^= 1; } -static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots) +static void spitz_gpio_setup(PXA2xxState *cpu, int slots) { qemu_irq lcd_hsync; /* @@ -912,8 +912,8 @@ static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model, enum spitz_model_e model, int arm_id) { - struct pxa2xx_state_s *cpu; - struct scoop_info_s *scp0, *scp1 = NULL; + PXA2xxState *cpu; + ScoopInfo *scp0, *scp1 = NULL; if (!cpu_model) cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; diff --git a/hw/ssi-sd.c b/hw/ssi-sd.c index ffb9c4cda7..93d2374958 100644 --- a/hw/ssi-sd.c +++ b/hw/ssi-sd.c @@ -82,7 +82,7 @@ int ssi_sd_xfer(void *opaque, int val) return 0xff; case SSI_SD_CMDARG: if (s->arglen == 4) { - struct sd_request_s request; + SDRequest request; uint8_t longresp[16]; /* FIXME: Check CRC. */ request.cmd = s->cmd; diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c index 56fd1eec92..7803a4c8ac 100644 --- a/hw/tc6393xb.c +++ b/hw/tc6393xb.c @@ -78,7 +78,7 @@ #define NAND_MODE_ECC_READ 0x40 #define NAND_MODE_ECC_RST 0x60 -struct tc6393xb_s { +struct TC6393xbState { qemu_irq irq; qemu_irq *sub_irqs; struct { @@ -118,8 +118,8 @@ struct tc6393xb_s { } nand; int nand_enable; uint32_t nand_phys; - struct nand_flash_s *flash; - struct ecc_state_s ecc; + NANDFlashState *flash; + ECCState ecc; DisplayState *ds; ram_addr_t vram_addr; @@ -130,14 +130,14 @@ struct tc6393xb_s { blanked : 1; }; -qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s) +qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s) { return s->gpio_in; } static void tc6393xb_gpio_set(void *opaque, int line, int level) { -// struct tc6393xb_s *s = opaque; +// TC6393xbState *s = opaque; if (line > TC6393XB_GPIOS) { printf("%s: No GPIO pin %i\n", __FUNCTION__, line); @@ -147,7 +147,7 @@ static void tc6393xb_gpio_set(void *opaque, int line, int level) // FIXME: how does the chip reflect the GPIO input level change? } -void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line, +void tc6393xb_gpio_out_set(TC6393xbState *s, int line, qemu_irq handler) { if (line >= TC6393XB_GPIOS) { @@ -158,7 +158,7 @@ void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line, s->handler[line] = handler; } -static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s) +static void tc6393xb_gpio_handler_update(TC6393xbState *s) { uint32_t level, diff; int bit; @@ -173,20 +173,20 @@ static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s) s->prev_level = level; } -qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s) +qemu_irq tc6393xb_l3v_get(TC6393xbState *s) { return s->l3v; } static void tc6393xb_l3v(void *opaque, int line, int level) { - struct tc6393xb_s *s = opaque; + TC6393xbState *s = opaque; s->blank = !level; fprintf(stderr, "L3V: %d\n", level); } static void tc6393xb_sub_irq(void *opaque, int line, int level) { - struct tc6393xb_s *s = opaque; + TC6393xbState *s = opaque; uint8_t isr = s->scr.ISR; if (level) isr |= 1 << line; @@ -211,7 +211,7 @@ static void tc6393xb_sub_irq(void *opaque, int line, int level) { case SCR_ ##N(1): return s->scr.N[1]; \ case SCR_ ##N(2): return s->scr.N[2] -static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr) +static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr) { switch (addr) { case SCR_REVID: @@ -272,7 +272,7 @@ static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr case SCR_ ##N(1): s->scr.N[1] = value; return; \ case SCR_ ##N(2): s->scr.N[2] = value; return -static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) +static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) { switch (addr) { SCR_REG_B(ISR); @@ -318,12 +318,12 @@ static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, u #undef SCR_REG_L #undef SCR_REG_A -static void tc6393xb_nand_irq(struct tc6393xb_s *s) { +static void tc6393xb_nand_irq(TC6393xbState *s) { qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); } -static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { +static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) { switch (addr) { case NAND_CFG_COMMAND: return s->nand_enable ? 2 : 0; @@ -336,7 +336,7 @@ static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); return 0; } -static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { +static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) { switch (addr) { case NAND_CFG_COMMAND: s->nand_enable = (value & 0x2); @@ -353,7 +353,7 @@ static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t ad (uint32_t) addr, value & 0xff); } -static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { +static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) { switch (addr) { case NAND_DATA + 0: case NAND_DATA + 1: @@ -372,7 +372,7 @@ static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t add fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); return 0; } -static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { +static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) { // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", // (uint32_t) addr, value & 0xff); switch (addr) { @@ -427,7 +427,7 @@ static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, #define BITS 32 #include "tc6393xb_template.h" -static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update) +static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) { switch (ds_get_bits_per_pixel(s->ds)) { case 8: @@ -453,7 +453,7 @@ static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update) dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); } -static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update) +static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) { int i, w; uint8_t *d; @@ -473,7 +473,7 @@ static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update) static void tc6393xb_update_display(void *opaque) { - struct tc6393xb_s *s = opaque; + TC6393xbState *s = opaque; int full_update; if (s->scr_width == 0 || s->scr_height == 0) @@ -496,7 +496,7 @@ static void tc6393xb_update_display(void *opaque) static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { - struct tc6393xb_s *s = opaque; + TC6393xbState *s = opaque; switch (addr >> 8) { case 0: @@ -517,7 +517,7 @@ static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { } static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct tc6393xb_s *s = opaque; + TC6393xbState *s = opaque; switch (addr >> 8) { case 0: @@ -563,10 +563,10 @@ static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t valu tc6393xb_writeb(opaque, addr + 3, value >> 24); } -struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq) +TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq) { int iomemtype; - struct tc6393xb_s *s; + TC6393xbState *s; CPUReadMemoryFunc *tc6393xb_readfn[] = { tc6393xb_readb, tc6393xb_readw, @@ -578,7 +578,7 @@ struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq) tc6393xb_writel, }; - s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s)); + s = (TC6393xbState *) qemu_mallocz(sizeof(TC6393xbState)); s->irq = irq; s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); diff --git a/hw/tc6393xb_template.h b/hw/tc6393xb_template.h index 0f7694b36e..2c5fb674ea 100644 --- a/hw/tc6393xb_template.h +++ b/hw/tc6393xb_template.h @@ -36,7 +36,7 @@ #endif -static void glue(tc6393xb_draw_graphic, BITS)(struct tc6393xb_s *s) +static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s) { int i; int w_display; diff --git a/hw/tmp105.c b/hw/tmp105.c index d6ab2c35b0..0877e126fc 100644 --- a/hw/tmp105.c +++ b/hw/tmp105.c @@ -22,7 +22,7 @@ #include "hw.h" #include "i2c.h" -struct tmp105_s { +typedef struct { i2c_slave i2c; int len; uint8_t buf[2]; @@ -34,14 +34,14 @@ struct tmp105_s { int16_t limit[2]; int faults; int alarm; -}; +} TMP105State; -static void tmp105_interrupt_update(struct tmp105_s *s) +static void tmp105_interrupt_update(TMP105State *s) { qemu_set_irq(s->pin, s->alarm ^ ((~s->config >> 2) & 1)); /* POL */ } -static void tmp105_alarm_update(struct tmp105_s *s) +static void tmp105_alarm_update(TMP105State *s) { if ((s->config >> 0) & 1) { /* SD */ if ((s->config >> 7) & 1) /* OS */ @@ -68,7 +68,7 @@ static void tmp105_alarm_update(struct tmp105_s *s) /* Units are 0.001 centigrades relative to 0 C. */ void tmp105_set(i2c_slave *i2c, int temp) { - struct tmp105_s *s = (struct tmp105_s *) i2c; + TMP105State *s = (TMP105State *) i2c; if (temp >= 128000 || temp < -128000) { fprintf(stderr, "%s: values is out of range (%i.%03i C)\n", @@ -83,7 +83,7 @@ void tmp105_set(i2c_slave *i2c, int temp) static const int tmp105_faultq[4] = { 1, 2, 4, 6 }; -static void tmp105_read(struct tmp105_s *s) +static void tmp105_read(TMP105State *s) { s->len = 0; @@ -115,7 +115,7 @@ static void tmp105_read(struct tmp105_s *s) } } -static void tmp105_write(struct tmp105_s *s) +static void tmp105_write(TMP105State *s) { switch (s->pointer & 3) { case 0: /* Temperature */ @@ -141,7 +141,7 @@ static void tmp105_write(struct tmp105_s *s) static int tmp105_rx(i2c_slave *i2c) { - struct tmp105_s *s = (struct tmp105_s *) i2c; + TMP105State *s = (TMP105State *) i2c; if (s->len < 2) return s->buf[s->len ++]; @@ -151,7 +151,7 @@ static int tmp105_rx(i2c_slave *i2c) static int tmp105_tx(i2c_slave *i2c, uint8_t data) { - struct tmp105_s *s = (struct tmp105_s *) i2c; + TMP105State *s = (TMP105State *) i2c; if (!s->len ++) s->pointer = data; @@ -166,7 +166,7 @@ static int tmp105_tx(i2c_slave *i2c, uint8_t data) static void tmp105_event(i2c_slave *i2c, enum i2c_event event) { - struct tmp105_s *s = (struct tmp105_s *) i2c; + TMP105State *s = (TMP105State *) i2c; if (event == I2C_START_RECV) tmp105_read(s); @@ -176,7 +176,7 @@ static void tmp105_event(i2c_slave *i2c, enum i2c_event event) static void tmp105_save(QEMUFile *f, void *opaque) { - struct tmp105_s *s = (struct tmp105_s *) opaque; + TMP105State *s = (TMP105State *) opaque; qemu_put_byte(f, s->len); qemu_put_8s(f, &s->buf[0]); @@ -195,7 +195,7 @@ static void tmp105_save(QEMUFile *f, void *opaque) static int tmp105_load(QEMUFile *f, void *opaque, int version_id) { - struct tmp105_s *s = (struct tmp105_s *) opaque; + TMP105State *s = (TMP105State *) opaque; s->len = qemu_get_byte(f); qemu_get_8s(f, &s->buf[0]); @@ -216,7 +216,7 @@ static int tmp105_load(QEMUFile *f, void *opaque, int version_id) void tmp105_reset(i2c_slave *i2c) { - struct tmp105_s *s = (struct tmp105_s *) i2c; + TMP105State *s = (TMP105State *) i2c; s->temperature = 0; s->pointer = 0; @@ -229,8 +229,8 @@ void tmp105_reset(i2c_slave *i2c) struct i2c_slave *tmp105_init(i2c_bus *bus, qemu_irq alarm) { - struct tmp105_s *s = (struct tmp105_s *) - i2c_slave_init(bus, 0, sizeof(struct tmp105_s)); + TMP105State *s = (TMP105State *) + i2c_slave_init(bus, 0, sizeof(TMP105State)); s->i2c.event = tmp105_event; s->i2c.recv = tmp105_rx; @@ -45,9 +45,9 @@ #define DAC_CH1 0 #define DAC_CH2 1 -static void tosa_microdrive_attach(struct pxa2xx_state_s *cpu) +static void tosa_microdrive_attach(PXA2xxState *cpu) { - struct pcmcia_card_s *md; + PCMCIACardState *md; int index; BlockDriverState *bs; @@ -83,10 +83,10 @@ static void tosa_out_switch(void *opaque, int line, int level) } -static void tosa_gpio_setup(struct pxa2xx_state_s *cpu, - struct scoop_info_s *scp0, - struct scoop_info_s *scp1, - struct tc6393xb_s *tmio) +static void tosa_gpio_setup(PXA2xxState *cpu, + ScoopInfo *scp0, + ScoopInfo *scp1, + TC6393xbState *tmio) { qemu_irq *outsignals = qemu_allocate_irqs(tosa_out_switch, cpu, 4); /* MMC/SD host */ @@ -178,7 +178,7 @@ static int tosa_dac_recv(i2c_slave *s) return -1; } -static void tosa_tg_init(struct pxa2xx_state_s *cpu) +static void tosa_tg_init(PXA2xxState *cpu) { struct i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]); struct i2c_slave *dac = i2c_slave_init(bus, 0, sizeof(struct tosa_dac_i2c)); @@ -201,9 +201,9 @@ static void tosa_init(ram_addr_t ram_size, int vga_ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - struct pxa2xx_state_s *cpu; - struct tc6393xb_s *tmio; - struct scoop_info_s *scp0, *scp1; + PXA2xxState *cpu; + TC6393xbState *tmio; + ScoopInfo *scp0, *scp1; if (!cpu_model) cpu_model = "pxa255"; diff --git a/hw/tsc2005.c b/hw/tsc2005.c index e8d4a85b5a..2e71b8e794 100644 --- a/hw/tsc2005.c +++ b/hw/tsc2005.c @@ -26,7 +26,7 @@ #define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - (p ? 12 : 10))) -struct tsc2005_state_s { +typedef struct { qemu_irq pint; /* Combination of the nPENIRQ and DAV signals */ QEMUTimer *timer; uint16_t model; @@ -55,7 +55,7 @@ struct tsc2005_state_s { uint16_t aux_thr[2]; int tr[8]; -}; +} TSC2005State; enum { TSC_MODE_XYZ_SCAN = 0x0, @@ -108,7 +108,7 @@ static const uint16_t mode_regs[16] = { #define TEMP1_VAL (1264 << 4) /* +/- 5 at 12-bit */ #define TEMP2_VAL (1531 << 4) /* +/- 5 at 12-bit */ -static uint16_t tsc2005_read(struct tsc2005_state_s *s, int reg) +static uint16_t tsc2005_read(TSC2005State *s, int reg) { uint16_t ret; @@ -178,7 +178,7 @@ static uint16_t tsc2005_read(struct tsc2005_state_s *s, int reg) return 0xffff; } -static void tsc2005_write(struct tsc2005_state_s *s, int reg, uint16_t data) +static void tsc2005_write(TSC2005State *s, int reg, uint16_t data) { switch (reg) { case 0x8: /* AUX high treshold */ @@ -226,7 +226,7 @@ static void tsc2005_write(struct tsc2005_state_s *s, int reg, uint16_t data) } /* This handles most of the chip's logic. */ -static void tsc2005_pin_update(struct tsc2005_state_s *s) +static void tsc2005_pin_update(TSC2005State *s) { int64_t expires; int pin_state; @@ -295,7 +295,7 @@ static void tsc2005_pin_update(struct tsc2005_state_s *s) qemu_mod_timer(s->timer, expires); } -static void tsc2005_reset(struct tsc2005_state_s *s) +static void tsc2005_reset(TSC2005State *s) { s->state = 0; s->pin_func = 0; @@ -321,7 +321,7 @@ static void tsc2005_reset(struct tsc2005_state_s *s) static uint8_t tsc2005_txrx_word(void *opaque, uint8_t value) { - struct tsc2005_state_s *s = opaque; + TSC2005State *s = opaque; uint32_t ret = 0; switch (s->state ++) { @@ -399,7 +399,7 @@ uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len) static void tsc2005_timer_tick(void *opaque) { - struct tsc2005_state_s *s = opaque; + TSC2005State *s = opaque; /* Timer ticked -- a set of conversions has been finished. */ @@ -415,7 +415,7 @@ static void tsc2005_timer_tick(void *opaque) static void tsc2005_touchscreen_event(void *opaque, int x, int y, int z, int buttons_state) { - struct tsc2005_state_s *s = opaque; + TSC2005State *s = opaque; int p = s->pressure; if (buttons_state) { @@ -435,7 +435,7 @@ static void tsc2005_touchscreen_event(void *opaque, static void tsc2005_save(QEMUFile *f, void *opaque) { - struct tsc2005_state_s *s = (struct tsc2005_state_s *) opaque; + TSC2005State *s = (TSC2005State *) opaque; int i; qemu_put_be16(f, s->x); @@ -476,7 +476,7 @@ static void tsc2005_save(QEMUFile *f, void *opaque) static int tsc2005_load(QEMUFile *f, void *opaque, int version_id) { - struct tsc2005_state_s *s = (struct tsc2005_state_s *) opaque; + TSC2005State *s = (TSC2005State *) opaque; int i; s->x = qemu_get_be16(f); @@ -522,10 +522,10 @@ static int tsc2005_load(QEMUFile *f, void *opaque, int version_id) void *tsc2005_init(qemu_irq pintdav) { - struct tsc2005_state_s *s; + TSC2005State *s; - s = (struct tsc2005_state_s *) - qemu_mallocz(sizeof(struct tsc2005_state_s)); + s = (TSC2005State *) + qemu_mallocz(sizeof(TSC2005State)); s->x = 400; s->y = 240; s->pressure = 0; @@ -559,9 +559,9 @@ void *tsc2005_init(qemu_irq pintdav) * from the touchscreen. Assuming 12-bit precision was used during * tslib calibration. */ -void tsc2005_set_transform(void *opaque, struct mouse_transform_info_s *info) +void tsc2005_set_transform(void *opaque, MouseTransformInfo *info) { - struct tsc2005_state_s *s = (struct tsc2005_state_s *) opaque; + TSC2005State *s = (TSC2005State *) opaque; /* This version assumes touchscreen X & Y axis are parallel or * perpendicular to LCD's X & Y axis in some way. */ diff --git a/hw/tsc210x.c b/hw/tsc210x.c index 55e1214128..76e36d61e9 100644 --- a/hw/tsc210x.c +++ b/hw/tsc210x.c @@ -24,7 +24,7 @@ #include "audio/audio.h" #include "qemu-timer.h" #include "console.h" -#include "omap.h" /* For struct i2s_codec_s and struct uwire_slave_s */ +#include "omap.h" /* For I2SCodec and uWireSlave */ #include "devices.h" #define TSC_DATA_REGISTERS_PAGE 0x0 @@ -35,14 +35,14 @@ #define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - resolution[p])) -struct tsc210x_state_s { +typedef struct { qemu_irq pint; qemu_irq kbint; qemu_irq davint; QEMUTimer *timer; QEMUSoundCard card; - struct uwire_slave_s chip; - struct i2s_codec_s codec; + uWireSlave chip; + I2SCodec codec; uint8_t in_fifo[16384]; uint8_t out_fifo[16384]; uint16_t model; @@ -94,7 +94,7 @@ struct tsc210x_state_s { int mode; int intr; } kb; -}; +} TSC210xState; static const int resolution[4] = { 12, 8, 10, 12 }; @@ -153,7 +153,7 @@ static const uint16_t mode_regs[16] = { #define TSC_POWEROFF_DELAY 50 #define TSC_SOFTSTEP_DELAY 50 -static void tsc210x_reset(struct tsc210x_state_s *s) +static void tsc210x_reset(TSC210xState *s) { s->state = 0; s->pin_func = 2; @@ -211,14 +211,14 @@ static void tsc210x_reset(struct tsc210x_state_s *s) qemu_irq_raise(s->kbint); } -struct tsc210x_rate_info_s { +typedef struct { int rate; int dsor; int fsref; -}; +} TSC210xRateInfo; /* { rate, dsor, fsref } */ -static const struct tsc210x_rate_info_s tsc2101_rates[] = { +static const TSC210xRateInfo tsc2101_rates[] = { /* Fsref / 6.0 */ { 7350, 7, 1 }, { 8000, 7, 0 }, @@ -248,7 +248,7 @@ static const struct tsc210x_rate_info_s tsc2101_rates[] = { }; /* { rate, dsor, fsref } */ -static const struct tsc210x_rate_info_s tsc2102_rates[] = { +static const TSC210xRateInfo tsc2102_rates[] = { /* Fsref / 6.0 */ { 7350, 63, 1 }, { 8000, 63, 0 }, @@ -277,7 +277,7 @@ static const struct tsc210x_rate_info_s tsc2102_rates[] = { { 0, 0, 0 }, }; -static inline void tsc210x_out_flush(struct tsc210x_state_s *s, int len) +static inline void tsc210x_out_flush(TSC210xState *s, int len) { uint8_t *data = s->codec.out.fifo + s->codec.out.start; uint8_t *end = data + len; @@ -291,7 +291,7 @@ static inline void tsc210x_out_flush(struct tsc210x_state_s *s, int len) s->codec.out.start = 0; } -static void tsc210x_audio_out_cb(struct tsc210x_state_s *s, int free_b) +static void tsc210x_audio_out_cb(TSC210xState *s, int free_b) { if (s->codec.out.len >= free_b) { tsc210x_out_flush(s, free_b); @@ -302,9 +302,9 @@ static void tsc210x_audio_out_cb(struct tsc210x_state_s *s, int free_b) qemu_irq_raise(s->codec.tx_start); } -static void tsc2102_audio_rate_update(struct tsc210x_state_s *s) +static void tsc2102_audio_rate_update(TSC210xState *s) { - const struct tsc210x_rate_info_s *rate; + const TSC210xRateInfo *rate; s->codec.tx_rate = 0; s->codec.rx_rate = 0; @@ -323,7 +323,7 @@ static void tsc2102_audio_rate_update(struct tsc210x_state_s *s) s->codec.tx_rate = rate->rate; } -static void tsc2102_audio_output_update(struct tsc210x_state_s *s) +static void tsc2102_audio_output_update(TSC210xState *s) { int enable; struct audsettings fmt; @@ -357,7 +357,7 @@ static void tsc2102_audio_output_update(struct tsc210x_state_s *s) } } -static uint16_t tsc2102_data_register_read(struct tsc210x_state_s *s, int reg) +static uint16_t tsc2102_data_register_read(TSC210xState *s, int reg) { switch (reg) { case 0x00: /* X */ @@ -433,7 +433,7 @@ static uint16_t tsc2102_data_register_read(struct tsc210x_state_s *s, int reg) } static uint16_t tsc2102_control_register_read( - struct tsc210x_state_s *s, int reg) + TSC210xState *s, int reg) { switch (reg) { case 0x00: /* TSC ADC */ @@ -483,7 +483,7 @@ static uint16_t tsc2102_control_register_read( } } -static uint16_t tsc2102_audio_register_read(struct tsc210x_state_s *s, int reg) +static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg) { int l_ch, r_ch; uint16_t val; @@ -565,7 +565,7 @@ static uint16_t tsc2102_audio_register_read(struct tsc210x_state_s *s, int reg) } static void tsc2102_data_register_write( - struct tsc210x_state_s *s, int reg, uint16_t value) + TSC210xState *s, int reg, uint16_t value) { switch (reg) { case 0x00: /* X */ @@ -589,7 +589,7 @@ static void tsc2102_data_register_write( } static void tsc2102_control_register_write( - struct tsc210x_state_s *s, int reg, uint16_t value) + TSC210xState *s, int reg, uint16_t value) { switch (reg) { case 0x00: /* TSC ADC */ @@ -673,7 +673,7 @@ static void tsc2102_control_register_write( } static void tsc2102_audio_register_write( - struct tsc210x_state_s *s, int reg, uint16_t value) + TSC210xState *s, int reg, uint16_t value) { switch (reg) { case 0x00: /* Audio Control 1 */ @@ -804,7 +804,7 @@ static void tsc2102_audio_register_write( } /* This handles most of the chip logic. */ -static void tsc210x_pin_update(struct tsc210x_state_s *s) +static void tsc210x_pin_update(TSC210xState *s) { int64_t expires; int pin_state; @@ -873,7 +873,7 @@ static void tsc210x_pin_update(struct tsc210x_state_s *s) qemu_mod_timer(s->timer, expires); } -static uint16_t tsc210x_read(struct tsc210x_state_s *s) +static uint16_t tsc210x_read(TSC210xState *s) { uint16_t ret = 0x0000; @@ -904,7 +904,7 @@ static uint16_t tsc210x_read(struct tsc210x_state_s *s) return ret; } -static void tsc210x_write(struct tsc210x_state_s *s, uint16_t value) +static void tsc210x_write(TSC210xState *s, uint16_t value) { /* * This is a two-state state machine for reading @@ -940,7 +940,7 @@ static void tsc210x_write(struct tsc210x_state_s *s, uint16_t value) uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len) { - struct tsc210x_state_s *s = opaque; + TSC210xState *s = opaque; uint32_t ret = 0; if (len != 16) @@ -959,7 +959,7 @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len) static void tsc210x_timer_tick(void *opaque) { - struct tsc210x_state_s *s = opaque; + TSC210xState *s = opaque; /* Timer ticked -- a set of conversions has been finished. */ @@ -975,7 +975,7 @@ static void tsc210x_timer_tick(void *opaque) static void tsc210x_touchscreen_event(void *opaque, int x, int y, int z, int buttons_state) { - struct tsc210x_state_s *s = opaque; + TSC210xState *s = opaque; int p = s->pressure; if (buttons_state) { @@ -993,7 +993,7 @@ static void tsc210x_touchscreen_event(void *opaque, tsc210x_pin_update(s); } -static void tsc210x_i2s_swallow(struct tsc210x_state_s *s) +static void tsc210x_i2s_swallow(TSC210xState *s) { if (s->dac_voice[0]) tsc210x_out_flush(s, s->codec.out.len); @@ -1001,7 +1001,7 @@ static void tsc210x_i2s_swallow(struct tsc210x_state_s *s) s->codec.out.len = 0; } -static void tsc210x_i2s_set_rate(struct tsc210x_state_s *s, int in, int out) +static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out) { s->i2s_tx_rate = out; s->i2s_rx_rate = in; @@ -1009,7 +1009,7 @@ static void tsc210x_i2s_set_rate(struct tsc210x_state_s *s, int in, int out) static void tsc210x_save(QEMUFile *f, void *opaque) { - struct tsc210x_state_s *s = (struct tsc210x_state_s *) opaque; + TSC210xState *s = (TSC210xState *) opaque; int64_t now = qemu_get_clock(vm_clock); int i; @@ -1055,7 +1055,7 @@ static void tsc210x_save(QEMUFile *f, void *opaque) static int tsc210x_load(QEMUFile *f, void *opaque, int version_id) { - struct tsc210x_state_s *s = (struct tsc210x_state_s *) opaque; + TSC210xState *s = (TSC210xState *) opaque; int64_t now = qemu_get_clock(vm_clock); int i; @@ -1105,13 +1105,13 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio) +uWireSlave *tsc2102_init(qemu_irq pint, AudioState *audio) { - struct tsc210x_state_s *s; + TSC210xState *s; - s = (struct tsc210x_state_s *) - qemu_mallocz(sizeof(struct tsc210x_state_s)); - memset(s, 0, sizeof(struct tsc210x_state_s)); + s = (TSC210xState *) + qemu_mallocz(sizeof(TSC210xState)); + memset(s, 0, sizeof(TSC210xState)); s->x = 160; s->y = 160; s->pressure = 0; @@ -1156,14 +1156,14 @@ struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio) return &s->chip; } -struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, +uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav, AudioState *audio) { - struct tsc210x_state_s *s; + TSC210xState *s; - s = (struct tsc210x_state_s *) - qemu_mallocz(sizeof(struct tsc210x_state_s)); - memset(s, 0, sizeof(struct tsc210x_state_s)); + s = (TSC210xState *) + qemu_mallocz(sizeof(TSC210xState)); + memset(s, 0, sizeof(TSC210xState)); s->x = 400; s->y = 240; s->pressure = 0; @@ -1209,9 +1209,9 @@ struct uwire_slave_s *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, return &s->chip; } -struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip) +I2SCodec *tsc210x_codec(uWireSlave *chip) { - struct tsc210x_state_s *s = (struct tsc210x_state_s *) chip->opaque; + TSC210xState *s = (TSC210xState *) chip->opaque; return &s->codec; } @@ -1221,10 +1221,10 @@ struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip) * from the touchscreen. Assuming 12-bit precision was used during * tslib calibration. */ -void tsc210x_set_transform(struct uwire_slave_s *chip, - struct mouse_transform_info_s *info) +void tsc210x_set_transform(uWireSlave *chip, + MouseTransformInfo *info) { - struct tsc210x_state_s *s = (struct tsc210x_state_s *) chip->opaque; + TSC210xState *s = (TSC210xState *) chip->opaque; #if 0 int64_t ltr[8]; @@ -1283,9 +1283,9 @@ void tsc210x_set_transform(struct uwire_slave_s *chip, #endif } -void tsc210x_key_event(struct uwire_slave_s *chip, int key, int down) +void tsc210x_key_event(uWireSlave *chip, int key, int down) { - struct tsc210x_state_s *s = (struct tsc210x_state_s *) chip->opaque; + TSC210xState *s = (TSC210xState *) chip->opaque; if (down) s->kb.down |= 1 << key; diff --git a/hw/tusb6010.c b/hw/tusb6010.c index 3cf2e6c7ae..f3aa7b1f80 100644 --- a/hw/tusb6010.c +++ b/hw/tusb6010.c @@ -26,10 +26,10 @@ #include "irq.h" #include "devices.h" -struct tusb_s { +struct TUSBState { int iomemtype[2]; qemu_irq irq; - struct musb_s *musb; + MUSBState *musb; QEMUTimer *otg_timer; QEMUTimer *pwr_timer; @@ -235,17 +235,17 @@ struct tusb_s { #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) #define TUSB_PROD_TEST_RESET_VAL 0xa596 -int tusb6010_sync_io(struct tusb_s *s) +int tusb6010_sync_io(TUSBState *s) { return s->iomemtype[0]; } -int tusb6010_async_io(struct tusb_s *s) +int tusb6010_async_io(TUSBState *s) { return s->iomemtype[1]; } -static void tusb_intr_update(struct tusb_s *s) +static void tusb_intr_update(TUSBState *s) { if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY) qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); @@ -253,7 +253,7 @@ static void tusb_intr_update(struct tusb_s *s) qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); } -static void tusb_usbip_intr_update(struct tusb_s *s) +static void tusb_usbip_intr_update(TUSBState *s) { /* TX interrupt in the MUSB */ if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) @@ -272,7 +272,7 @@ static void tusb_usbip_intr_update(struct tusb_s *s) tusb_intr_update(s); } -static void tusb_dma_intr_update(struct tusb_s *s) +static void tusb_dma_intr_update(TUSBState *s) { if (s->dma_intr & ~s->dma_mask) s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; @@ -282,7 +282,7 @@ static void tusb_dma_intr_update(struct tusb_s *s) tusb_intr_update(s); } -static void tusb_gpio_intr_update(struct tusb_s *s) +static void tusb_gpio_intr_update(TUSBState *s) { /* TODO: How is this signalled? */ } @@ -292,7 +292,7 @@ extern CPUWriteMemoryFunc *musb_write[]; static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; switch (addr & 0xfff) { case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): @@ -309,7 +309,7 @@ static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr) static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; switch (addr & 0xfff) { case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): @@ -326,7 +326,7 @@ static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr) static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; int offset = addr & 0xfff; int epnum; uint32_t ret; @@ -451,7 +451,7 @@ static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr) static void tusb_async_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; switch (addr & 0xfff) { case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): @@ -472,7 +472,7 @@ static void tusb_async_writeb(void *opaque, target_phys_addr_t addr, static void tusb_async_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; switch (addr & 0xfff) { case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): @@ -493,7 +493,7 @@ static void tusb_async_writeh(void *opaque, target_phys_addr_t addr, static void tusb_async_writew(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; int offset = addr & 0xfff; int epnum; @@ -664,7 +664,7 @@ static CPUWriteMemoryFunc *tusb_async_writefn[] = { static void tusb_otg_tick(void *opaque) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; s->otg_timer_val = 0; s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; @@ -673,7 +673,7 @@ static void tusb_otg_tick(void *opaque) static void tusb_power_tick(void *opaque) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; if (s->power) { s->intr_ok = ~0; @@ -683,7 +683,7 @@ static void tusb_power_tick(void *opaque) static void tusb_musb_core_intr(void *opaque, int source, int level) { - struct tusb_s *s = (struct tusb_s *) opaque; + TUSBState *s = (TUSBState *) opaque; uint16_t otg_status = s->otg_status; switch (source) { @@ -730,9 +730,9 @@ static void tusb_musb_core_intr(void *opaque, int source, int level) } } -struct tusb_s *tusb6010_init(qemu_irq intr) +TUSBState *tusb6010_init(qemu_irq intr) { - struct tusb_s *s = qemu_mallocz(sizeof(*s)); + TUSBState *s = qemu_mallocz(sizeof(*s)); s->test_reset = TUSB_PROD_TEST_RESET_VAL; s->host_mode = 0; @@ -753,7 +753,7 @@ struct tusb_s *tusb6010_init(qemu_irq intr) return s; } -void tusb6010_power(struct tusb_s *s, int on) +void tusb6010_power(TUSBState *s, int on) { if (!on) s->power = 0; diff --git a/hw/twl92230.c b/hw/twl92230.c index f0e73182ff..35e16af01b 100644 --- a/hw/twl92230.c +++ b/hw/twl92230.c @@ -28,7 +28,7 @@ #define VERBOSE 1 -struct menelaus_s { +typedef struct { i2c_slave i2c; qemu_irq irq; @@ -66,20 +66,20 @@ struct menelaus_s { qemu_irq *in; int pwrbtn_state; qemu_irq pwrbtn; -}; +} MenelausState; -static inline void menelaus_update(struct menelaus_s *s) +static inline void menelaus_update(MenelausState *s) { qemu_set_irq(s->irq, s->status & ~s->mask); } -static inline void menelaus_rtc_start(struct menelaus_s *s) +static inline void menelaus_rtc_start(MenelausState *s) { s->rtc.next =+ qemu_get_clock(rt_clock); qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); } -static inline void menelaus_rtc_stop(struct menelaus_s *s) +static inline void menelaus_rtc_stop(MenelausState *s) { qemu_del_timer(s->rtc.hz_tm); s->rtc.next =- qemu_get_clock(rt_clock); @@ -87,12 +87,12 @@ static inline void menelaus_rtc_stop(struct menelaus_s *s) s->rtc.next = 1; } -static void menelaus_rtc_update(struct menelaus_s *s) +static void menelaus_rtc_update(MenelausState *s) { qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset); } -static void menelaus_alm_update(struct menelaus_s *s) +static void menelaus_alm_update(MenelausState *s) { if ((s->rtc.ctrl & 3) == 3) s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset; @@ -100,7 +100,7 @@ static void menelaus_alm_update(struct menelaus_s *s) static void menelaus_rtc_hz(void *opaque) { - struct menelaus_s *s = (struct menelaus_s *) opaque; + MenelausState *s = (MenelausState *) opaque; s->rtc.next_comp --; s->rtc.alm_sec --; @@ -130,7 +130,7 @@ static void menelaus_rtc_hz(void *opaque) static void menelaus_reset(i2c_slave *i2c) { - struct menelaus_s *s = (struct menelaus_s *) i2c; + MenelausState *s = (MenelausState *) i2c; s->reg = 0x00; s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */ @@ -196,7 +196,7 @@ static inline int from_bcd(uint8_t val) static void menelaus_gpio_set(void *opaque, int line, int level) { - struct menelaus_s *s = (struct menelaus_s *) opaque; + MenelausState *s = (MenelausState *) opaque; /* No interrupt generated */ s->inputs &= ~(1 << line); @@ -205,7 +205,7 @@ static void menelaus_gpio_set(void *opaque, int line, int level) static void menelaus_pwrbtn_set(void *opaque, int line, int level) { - struct menelaus_s *s = (struct menelaus_s *) opaque; + MenelausState *s = (MenelausState *) opaque; if (!s->pwrbtn_state && level) { s->status |= 1 << 11; /* PSHBTN */ @@ -275,7 +275,7 @@ static void menelaus_pwrbtn_set(void *opaque, int line, int level) static uint8_t menelaus_read(void *opaque, uint8_t addr) { - struct menelaus_s *s = (struct menelaus_s *) opaque; + MenelausState *s = (MenelausState *) opaque; int reg = 0; switch (addr) { @@ -421,7 +421,7 @@ static uint8_t menelaus_read(void *opaque, uint8_t addr) static void menelaus_write(void *opaque, uint8_t addr, uint8_t value) { - struct menelaus_s *s = (struct menelaus_s *) opaque; + MenelausState *s = (MenelausState *) opaque; int line; int reg = 0; struct tm tm; @@ -721,7 +721,7 @@ static void menelaus_write(void *opaque, uint8_t addr, uint8_t value) static void menelaus_event(i2c_slave *i2c, enum i2c_event event) { - struct menelaus_s *s = (struct menelaus_s *) i2c; + MenelausState *s = (MenelausState *) i2c; if (event == I2C_START_SEND) s->firstbyte = 1; @@ -729,7 +729,7 @@ static void menelaus_event(i2c_slave *i2c, enum i2c_event event) static int menelaus_tx(i2c_slave *i2c, uint8_t data) { - struct menelaus_s *s = (struct menelaus_s *) i2c; + MenelausState *s = (MenelausState *) i2c; /* Interpret register address byte */ if (s->firstbyte) { s->reg = data; @@ -742,7 +742,7 @@ static int menelaus_tx(i2c_slave *i2c, uint8_t data) static int menelaus_rx(i2c_slave *i2c) { - struct menelaus_s *s = (struct menelaus_s *) i2c; + MenelausState *s = (MenelausState *) i2c; return menelaus_read(s, s->reg ++); } @@ -767,7 +767,7 @@ static void tm_get(QEMUFile *f, struct tm *tm) { static void menelaus_save(QEMUFile *f, void *opaque) { - struct menelaus_s *s = (struct menelaus_s *) opaque; + MenelausState *s = (MenelausState *) opaque; qemu_put_be32(f, s->firstbyte); qemu_put_8s(f, &s->reg); @@ -819,7 +819,7 @@ static void menelaus_save(QEMUFile *f, void *opaque) static int menelaus_load(QEMUFile *f, void *opaque, int version_id) { - struct menelaus_s *s = (struct menelaus_s *) opaque; + MenelausState *s = (MenelausState *) opaque; s->firstbyte = qemu_get_be32(f); qemu_get_8s(f, &s->reg); @@ -877,8 +877,8 @@ static int menelaus_load(QEMUFile *f, void *opaque, int version_id) i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq) { - struct menelaus_s *s = (struct menelaus_s *) - i2c_slave_init(bus, 0, sizeof(struct menelaus_s)); + MenelausState *s = (MenelausState *) + i2c_slave_init(bus, 0, sizeof(MenelausState)); s->i2c.event = menelaus_event; s->i2c.recv = menelaus_rx; @@ -898,14 +898,14 @@ i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq) qemu_irq *twl92230_gpio_in_get(i2c_slave *i2c) { - struct menelaus_s *s = (struct menelaus_s *) i2c; + MenelausState *s = (MenelausState *) i2c; return s->in; } void twl92230_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler) { - struct menelaus_s *s = (struct menelaus_s *) i2c; + MenelausState *s = (MenelausState *) i2c; if (line >= 3 || line < 0) { fprintf(stderr, "%s: No GPO line %i\n", __FUNCTION__, line); diff --git a/hw/usb-musb.c b/hw/usb-musb.c index adc76a22c1..451bc8dbde 100644 --- a/hw/usb-musb.c +++ b/hw/usb-musb.c @@ -251,7 +251,36 @@ static void musb_attach(USBPort *port, USBDevice *dev); -struct musb_s { +typedef struct { + uint16_t faddr[2]; + uint8_t haddr[2]; + uint8_t hport[2]; + uint16_t csr[2]; + uint16_t maxp[2]; + uint16_t rxcount; + uint8_t type[2]; + uint8_t interval[2]; + uint8_t config; + uint8_t fifosize; + int timeout[2]; /* Always in microframes */ + + uint32_t *buf[2]; + int fifolen[2]; + int fifostart[2]; + int fifoaddr[2]; + USBPacket packey[2]; + int status[2]; + int ext_size[2]; + + /* For callbacks' use */ + int epnum; + int interrupt[2]; + MUSBState *musb; + USBCallback *delayed_cb[2]; + QEMUTimer *intv_timer[2]; +} MUSBEndPoint; + +struct MUSBState { qemu_irq *irqs; USBPort port; @@ -272,39 +301,12 @@ struct musb_s { uint32_t buf[0x2000]; - struct musb_ep_s { - uint16_t faddr[2]; - uint8_t haddr[2]; - uint8_t hport[2]; - uint16_t csr[2]; - uint16_t maxp[2]; - uint16_t rxcount; - uint8_t type[2]; - uint8_t interval[2]; - uint8_t config; - uint8_t fifosize; - int timeout[2]; /* Always in microframes */ - - uint32_t *buf[2]; - int fifolen[2]; - int fifostart[2]; - int fifoaddr[2]; - USBPacket packey[2]; - int status[2]; - int ext_size[2]; - - /* For callbacks' use */ - int epnum; - int interrupt[2]; - struct musb_s *musb; - USBCallback *delayed_cb[2]; - QEMUTimer *intv_timer[2]; /* Duplicating the world since 2008!... probably we should have 32 * logical, single endpoints instead. */ - } ep[16]; + MUSBEndPoint ep[16]; } *musb_init(qemu_irq *irqs) { - struct musb_s *s = qemu_mallocz(sizeof(*s)); + MUSBState *s = qemu_mallocz(sizeof(*s)); int i; s->irqs = irqs; @@ -334,7 +336,7 @@ struct musb_s { return s; } -static void musb_vbus_set(struct musb_s *s, int level) +static void musb_vbus_set(MUSBState *s, int level) { if (level) s->devctl |= 3 << MGC_S_DEVCTL_VBUS; @@ -344,7 +346,7 @@ static void musb_vbus_set(struct musb_s *s, int level) qemu_set_irq(s->irqs[musb_set_vbus], level); } -static void musb_intr_set(struct musb_s *s, int line, int level) +static void musb_intr_set(MUSBState *s, int line, int level) { if (!level) { s->intr &= ~(1 << line); @@ -355,7 +357,7 @@ static void musb_intr_set(struct musb_s *s, int line, int level) } } -static void musb_tx_intr_set(struct musb_s *s, int line, int level) +static void musb_tx_intr_set(MUSBState *s, int line, int level) { if (!level) { s->tx_intr &= ~(1 << line); @@ -367,7 +369,7 @@ static void musb_tx_intr_set(struct musb_s *s, int line, int level) } } -static void musb_rx_intr_set(struct musb_s *s, int line, int level) +static void musb_rx_intr_set(MUSBState *s, int line, int level) { if (line) { if (!level) { @@ -382,12 +384,12 @@ static void musb_rx_intr_set(struct musb_s *s, int line, int level) musb_tx_intr_set(s, line, level); } -uint32_t musb_core_intr_get(struct musb_s *s) +uint32_t musb_core_intr_get(MUSBState *s) { return (s->rx_intr << 15) | s->tx_intr; } -void musb_core_intr_clear(struct musb_s *s, uint32_t mask) +void musb_core_intr_clear(MUSBState *s, uint32_t mask) { if (s->rx_intr) { s->rx_intr &= mask >> 15; @@ -402,7 +404,7 @@ void musb_core_intr_clear(struct musb_s *s, uint32_t mask) } } -void musb_set_size(struct musb_s *s, int epnum, int size, int is_tx) +void musb_set_size(MUSBState *s, int epnum, int size, int is_tx) { s->ep[epnum].ext_size[!is_tx] = size; s->ep[epnum].fifostart[0] = 0; @@ -411,7 +413,7 @@ void musb_set_size(struct musb_s *s, int epnum, int size, int is_tx) s->ep[epnum].fifolen[1] = 0; } -static void musb_session_update(struct musb_s *s, int prev_dev, int prev_sess) +static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess) { int detect_prev = prev_dev && prev_sess; int detect = !!s->port.dev && s->session; @@ -448,7 +450,7 @@ static void musb_session_update(struct musb_s *s, int prev_dev, int prev_sess) /* Attach or detach a device on our only port. */ static void musb_attach(USBPort *port, USBDevice *dev) { - struct musb_s *s = (struct musb_s *) port->opaque; + MUSBState *s = (MUSBState *) port->opaque; USBDevice *curr; port = &s->port; @@ -478,14 +480,14 @@ static void musb_attach(USBPort *port, USBDevice *dev) static inline void musb_cb_tick0(void *opaque) { - struct musb_ep_s *ep = (struct musb_ep_s *) opaque; + MUSBEndPoint *ep = (MUSBEndPoint *) opaque; ep->delayed_cb[0](&ep->packey[0], opaque); } static inline void musb_cb_tick1(void *opaque) { - struct musb_ep_s *ep = (struct musb_ep_s *) opaque; + MUSBEndPoint *ep = (MUSBEndPoint *) opaque; ep->delayed_cb[1](&ep->packey[1], opaque); } @@ -494,7 +496,7 @@ static inline void musb_cb_tick1(void *opaque) static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir) { - struct musb_ep_s *ep = (struct musb_ep_s *) opaque; + MUSBEndPoint *ep = (MUSBEndPoint *) opaque; int timeout = 0; if (ep->status[dir] == USB_RET_NAK) @@ -559,7 +561,7 @@ static int musb_timeout(int ttype, int speed, int val) hw_error("bad interval\n"); } -static inline void musb_packet(struct musb_s *s, struct musb_ep_s *ep, +static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep, int epnum, int pid, int len, USBCallback cb, int dir) { int ret; @@ -606,9 +608,9 @@ static void musb_tx_packet_complete(USBPacket *packey, void *opaque) { /* Unfortunately we can't use packey->devep because that's the remote * endpoint number and may be different than our local. */ - struct musb_ep_s *ep = (struct musb_ep_s *) opaque; + MUSBEndPoint *ep = (MUSBEndPoint *) opaque; int epnum = ep->epnum; - struct musb_s *s = ep->musb; + MUSBState *s = ep->musb; ep->fifostart[0] = 0; ep->fifolen[0] = 0; @@ -686,9 +688,9 @@ static void musb_rx_packet_complete(USBPacket *packey, void *opaque) { /* Unfortunately we can't use packey->devep because that's the remote * endpoint number and may be different than our local. */ - struct musb_ep_s *ep = (struct musb_ep_s *) opaque; + MUSBEndPoint *ep = (MUSBEndPoint *) opaque; int epnum = ep->epnum; - struct musb_s *s = ep->musb; + MUSBState *s = ep->musb; ep->fifostart[1] = 0; ep->fifolen[1] = 0; @@ -766,9 +768,9 @@ static void musb_rx_packet_complete(USBPacket *packey, void *opaque) musb_rx_intr_set(s, epnum, 1); } -static void musb_tx_rdy(struct musb_s *s, int epnum) +static void musb_tx_rdy(MUSBState *s, int epnum) { - struct musb_ep_s *ep = s->ep + epnum; + MUSBEndPoint *ep = s->ep + epnum; int pid; int total, valid = 0; @@ -806,9 +808,9 @@ static void musb_tx_rdy(struct musb_s *s, int epnum) total, musb_tx_packet_complete, 0); } -static void musb_rx_req(struct musb_s *s, int epnum) +static void musb_rx_req(MUSBState *s, int epnum) { - struct musb_ep_s *ep = s->ep + epnum; + MUSBEndPoint *ep = s->ep + epnum; int total; /* If we already have a packet, which didn't fit into the @@ -869,7 +871,7 @@ static void musb_rx_req(struct musb_s *s, int epnum) total, musb_rx_packet_complete, 1); } -static void musb_ep_frame_cancel(struct musb_ep_s *ep, int dir) +static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir) { if (ep->intv_timer[dir]) qemu_del_timer(ep->intv_timer[dir]); @@ -878,7 +880,7 @@ static void musb_ep_frame_cancel(struct musb_ep_s *ep, int dir) /* Bus control */ static uint8_t musb_busctl_readb(void *opaque, int ep, int addr) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; switch (addr) { /* For USB2.0 HS hubs only */ @@ -899,7 +901,7 @@ static uint8_t musb_busctl_readb(void *opaque, int ep, int addr) static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; switch (addr) { case MUSB_HDRC_TXHUBADDR: @@ -922,7 +924,7 @@ static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value) static uint16_t musb_busctl_readh(void *opaque, int ep, int addr) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; switch (addr) { case MUSB_HDRC_TXFUNCADDR: @@ -938,7 +940,7 @@ static uint16_t musb_busctl_readh(void *opaque, int ep, int addr) static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; switch (addr) { case MUSB_HDRC_TXFUNCADDR: @@ -957,7 +959,7 @@ static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value) /* Endpoint control */ static uint8_t musb_ep_readb(void *opaque, int ep, int addr) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; switch (addr) { case MUSB_HDRC_TXTYPE: @@ -981,7 +983,7 @@ static uint8_t musb_ep_readb(void *opaque, int ep, int addr) static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; switch (addr) { case MUSB_HDRC_TXTYPE: @@ -1013,7 +1015,7 @@ static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value) static uint16_t musb_ep_readh(void *opaque, int ep, int addr) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; uint16_t ret; switch (addr) { @@ -1043,7 +1045,7 @@ static uint16_t musb_ep_readh(void *opaque, int ep, int addr) static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; switch (addr) { case MUSB_HDRC_TXMAXP: @@ -1141,7 +1143,7 @@ static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value) /* Generic control */ static uint32_t musb_readb(void *opaque, target_phys_addr_t addr) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; int ep, i; uint8_t ret; @@ -1199,7 +1201,7 @@ static uint32_t musb_readb(void *opaque, target_phys_addr_t addr) static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; int ep; switch (addr) { @@ -1280,7 +1282,7 @@ static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) static uint32_t musb_readh(void *opaque, target_phys_addr_t addr) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; int ep, i; uint16_t ret; @@ -1330,7 +1332,7 @@ static uint32_t musb_readh(void *opaque, target_phys_addr_t addr) static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct musb_s *s = (struct musb_s *) opaque; + MUSBState *s = (MUSBState *) opaque; int ep; switch (addr) { @@ -1380,8 +1382,8 @@ static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) static uint32_t musb_readw(void *opaque, target_phys_addr_t addr) { - struct musb_s *s = (struct musb_s *) opaque; - struct musb_ep_s *ep; + MUSBState *s = (MUSBState *) opaque; + MUSBEndPoint *ep; int epnum; switch (addr) { @@ -1409,8 +1411,8 @@ static uint32_t musb_readw(void *opaque, target_phys_addr_t addr) static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct musb_s *s = (struct musb_s *) opaque; - struct musb_ep_s *ep; + MUSBState *s = (MUSBState *) opaque; + MUSBEndPoint *ep; int epnum; switch (addr) { @@ -292,8 +292,8 @@ enum musb_irq_source_e { __musb_irq_max, }; -struct musb_s; -struct musb_s *musb_init(qemu_irq *irqs); -uint32_t musb_core_intr_get(struct musb_s *s); -void musb_core_intr_clear(struct musb_s *s, uint32_t mask); -void musb_set_size(struct musb_s *s, int epnum, int size, int is_tx); +typedef struct MUSBState MUSBState; +MUSBState *musb_init(qemu_irq *irqs); +uint32_t musb_core_intr_get(MUSBState *s); +void musb_core_intr_clear(MUSBState *s, uint32_t mask); +void musb_set_size(MUSBState *s, int epnum, int size, int is_tx); diff --git a/hw/wm8750.c b/hw/wm8750.c index 02d5f5e5be..7086a79988 100644 --- a/hw/wm8750.c +++ b/hw/wm8750.c @@ -16,8 +16,14 @@ #define CODEC "wm8750" -struct wm_rate_s; -struct wm8750_s { +typedef struct { + int adc; + int adc_hz; + int dac; + int dac_hz; +} WMRate; + +typedef struct { i2c_slave i2c; uint8_t i2c_data[2]; int i2c_len; @@ -39,9 +45,9 @@ struct wm8750_s { uint8_t diff[2], pol, ds, monomix[2], alc, mute; uint8_t path[4], mpath[2], power, format; - const struct wm_rate_s *rate; + const WMRate *rate; int adc_hz, dac_hz, ext_adc_hz, ext_dac_hz, master; -}; +} WM8750State; /* pow(10.0, -i / 20.0) * 255, i = 0..42 */ static const uint8_t wm8750_vol_db_table[] = { @@ -53,7 +59,7 @@ static const uint8_t wm8750_vol_db_table[] = { #define WM8750_OUTVOL_TRANSFORM(x) wm8750_vol_db_table[(0x7f - x) / 3] #define WM8750_INVOL_TRANSFORM(x) (x << 2) -static inline void wm8750_in_load(struct wm8750_s *s) +static inline void wm8750_in_load(WM8750State *s) { int acquired; if (s->idx_in + s->req_in <= sizeof(s->data_in)) @@ -63,7 +69,7 @@ static inline void wm8750_in_load(struct wm8750_s *s) sizeof(s->data_in) - s->idx_in); } -static inline void wm8750_out_flush(struct wm8750_s *s) +static inline void wm8750_out_flush(WM8750State *s) { int sent = 0; while (sent < s->idx_out) @@ -74,14 +80,14 @@ static inline void wm8750_out_flush(struct wm8750_s *s) static void wm8750_audio_in_cb(void *opaque, int avail_b) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; s->req_in = avail_b; s->data_req(s->opaque, s->req_out >> 2, avail_b >> 2); } static void wm8750_audio_out_cb(void *opaque, int free_b) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; if (s->idx_out >= free_b) { s->idx_out = free_b; @@ -93,14 +99,7 @@ static void wm8750_audio_out_cb(void *opaque, int free_b) s->data_req(s->opaque, s->req_out >> 2, s->req_in >> 2); } -struct wm_rate_s { - int adc; - int adc_hz; - int dac; - int dac_hz; -}; - -static const struct wm_rate_s wm_rate_table[] = { +static const WMRate wm_rate_table[] = { { 256, 48000, 256, 48000 }, /* SR: 00000 */ { 384, 48000, 384, 48000 }, /* SR: 00001 */ { 256, 48000, 1536, 8000 }, /* SR: 00010 */ @@ -135,7 +134,7 @@ static const struct wm_rate_s wm_rate_table[] = { { 192, 88200, 192, 88200 }, /* SR: 11111 */ }; -static void wm8750_vol_update(struct wm8750_s *s) +static void wm8750_vol_update(WM8750State *s) { /* FIXME: multiply all volumes by s->invol[2], s->invol[3] */ @@ -167,7 +166,7 @@ static void wm8750_vol_update(struct wm8750_s *s) s->outmute[1] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[6])); } -static void wm8750_set_format(struct wm8750_s *s) +static void wm8750_set_format(WM8750State *s) { int i; struct audsettings in_fmt; @@ -239,7 +238,7 @@ static void wm8750_set_format(struct wm8750_s *s) AUD_set_active_out(*s->out[0], 1); } -static void wm8750_clk_update(struct wm8750_s *s, int ext) +static void wm8750_clk_update(WM8750State *s, int ext) { if (s->master || !s->ext_dac_hz) s->dac_hz = s->rate->dac_hz; @@ -262,7 +261,7 @@ static void wm8750_clk_update(struct wm8750_s *s, int ext) void wm8750_reset(i2c_slave *i2c) { - struct wm8750_s *s = (struct wm8750_s *) i2c; + WM8750State *s = (WM8750State *) i2c; s->rate = &wm_rate_table[0]; s->enable = 0; wm8750_clk_update(s, 1); @@ -305,7 +304,7 @@ void wm8750_reset(i2c_slave *i2c) static void wm8750_event(i2c_slave *i2c, enum i2c_event event) { - struct wm8750_s *s = (struct wm8750_s *) i2c; + WM8750State *s = (WM8750State *) i2c; switch (event) { case I2C_START_SEND: @@ -362,7 +361,7 @@ static void wm8750_event(i2c_slave *i2c, enum i2c_event event) static int wm8750_tx(i2c_slave *i2c, uint8_t data) { - struct wm8750_s *s = (struct wm8750_s *) i2c; + WM8750State *s = (WM8750State *) i2c; uint8_t cmd; uint16_t value; @@ -567,7 +566,7 @@ static int wm8750_rx(i2c_slave *i2c) static void wm8750_save(QEMUFile *f, void *opaque) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; int i; qemu_put_8s(f, &s->i2c_data[0]); qemu_put_8s(f, &s->i2c_data[1]); @@ -607,7 +606,7 @@ static void wm8750_save(QEMUFile *f, void *opaque) static int wm8750_load(QEMUFile *f, void *opaque, int version_id) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; int i; qemu_get_8s(f, &s->i2c_data[0]); qemu_get_8s(f, &s->i2c_data[1]); @@ -648,8 +647,8 @@ static int wm8750_load(QEMUFile *f, void *opaque, int version_id) i2c_slave *wm8750_init(i2c_bus *bus, AudioState *audio) { - struct wm8750_s *s = (struct wm8750_s *) - i2c_slave_init(bus, 0, sizeof(struct wm8750_s)); + WM8750State *s = (WM8750State *) + i2c_slave_init(bus, 0, sizeof(WM8750State)); s->i2c.event = wm8750_event; s->i2c.recv = wm8750_rx; s->i2c.send = wm8750_tx; @@ -665,7 +664,7 @@ i2c_slave *wm8750_init(i2c_bus *bus, AudioState *audio) #if 0 static void wm8750_fini(i2c_slave *i2c) { - struct wm8750_s *s = (struct wm8750_s *) i2c; + WM8750State *s = (WM8750State *) i2c; wm8750_reset(&s->i2c); AUD_remove_card(&s->card); qemu_free(s); @@ -675,14 +674,14 @@ static void wm8750_fini(i2c_slave *i2c) void wm8750_data_req_set(i2c_slave *i2c, void (*data_req)(void *, int, int), void *opaque) { - struct wm8750_s *s = (struct wm8750_s *) i2c; + WM8750State *s = (WM8750State *) i2c; s->data_req = data_req; s->opaque = opaque; } void wm8750_dac_dat(void *opaque, uint32_t sample) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; *(uint32_t *) &s->data_out[s->idx_out] = sample; s->req_out -= 4; @@ -693,7 +692,7 @@ void wm8750_dac_dat(void *opaque, uint32_t sample) void *wm8750_dac_buffer(void *opaque, int samples) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; /* XXX: Should check if there are <i>samples</i> free samples available */ void *ret = s->data_out + s->idx_out; @@ -704,14 +703,14 @@ void *wm8750_dac_buffer(void *opaque, int samples) void wm8750_dac_commit(void *opaque) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; wm8750_out_flush(s); } uint32_t wm8750_adc_dat(void *opaque) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; uint32_t *data; if (s->idx_in >= sizeof(s->data_in)) @@ -725,7 +724,7 @@ uint32_t wm8750_adc_dat(void *opaque) void wm8750_set_bclk_in(void *opaque, int new_hz) { - struct wm8750_s *s = (struct wm8750_s *) opaque; + WM8750State *s = (WM8750State *) opaque; s->ext_adc_hz = new_hz; s->ext_dac_hz = new_hz; diff --git a/hw/zaurus.c b/hw/zaurus.c index 482834fb7b..56e150d51c 100644 --- a/hw/zaurus.c +++ b/hw/zaurus.c @@ -29,7 +29,7 @@ /* SCOOP devices */ -struct scoop_info_s { +struct ScoopInfo { qemu_irq handler[16]; qemu_irq *in; uint16_t status; @@ -58,7 +58,7 @@ struct scoop_info_s { #define SCOOP_GPWR 0x24 #define SCOOP_GPRR 0x28 -static inline void scoop_gpio_handler_update(struct scoop_info_s *s) { +static inline void scoop_gpio_handler_update(ScoopInfo *s) { uint32_t level, diff; int bit; level = s->gpio_level & s->gpio_dir; @@ -73,7 +73,7 @@ static inline void scoop_gpio_handler_update(struct scoop_info_s *s) { static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) { - struct scoop_info_s *s = (struct scoop_info_s *) opaque; + ScoopInfo *s = (ScoopInfo *) opaque; switch (addr) { case SCOOP_MCR: @@ -106,7 +106,7 @@ static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { - struct scoop_info_s *s = (struct scoop_info_s *) opaque; + ScoopInfo *s = (ScoopInfo *) opaque; value &= 0xffff; switch (addr) { @@ -160,7 +160,7 @@ static CPUWriteMemoryFunc *scoop_writefn[] = { void scoop_gpio_set(void *opaque, int line, int level) { - struct scoop_info_s *s = (struct scoop_info_s *) s; + ScoopInfo *s = (ScoopInfo *) s; if (level) s->gpio_level |= (1 << line); @@ -168,12 +168,12 @@ void scoop_gpio_set(void *opaque, int line, int level) s->gpio_level &= ~(1 << line); } -qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s) +qemu_irq *scoop_gpio_in_get(ScoopInfo *s) { return s->in; } -void scoop_gpio_out_set(struct scoop_info_s *s, int line, +void scoop_gpio_out_set(ScoopInfo *s, int line, qemu_irq handler) { if (line >= 16) { fprintf(stderr, "No GPIO pin %i\n", line); @@ -185,7 +185,7 @@ void scoop_gpio_out_set(struct scoop_info_s *s, int line, static void scoop_save(QEMUFile *f, void *opaque) { - struct scoop_info_s *s = (struct scoop_info_s *) opaque; + ScoopInfo *s = (ScoopInfo *) opaque; qemu_put_be16s(f, &s->status); qemu_put_be16s(f, &s->power); qemu_put_be32s(f, &s->gpio_level); @@ -202,7 +202,7 @@ static void scoop_save(QEMUFile *f, void *opaque) static int scoop_load(QEMUFile *f, void *opaque, int version_id) { uint16_t dummy; - struct scoop_info_s *s = (struct scoop_info_s *) opaque; + ScoopInfo *s = (ScoopInfo *) opaque; qemu_get_be16s(f, &s->status); qemu_get_be16s(f, &s->power); qemu_get_be32s(f, &s->gpio_level); @@ -220,15 +220,15 @@ static int scoop_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu, +ScoopInfo *scoop_init(PXA2xxState *cpu, int instance, target_phys_addr_t target_base) { int iomemtype; - struct scoop_info_s *s; + ScoopInfo *s; - s = (struct scoop_info_s *) - qemu_mallocz(sizeof(struct scoop_info_s)); - memset(s, 0, sizeof(struct scoop_info_s)); + s = (ScoopInfo *) + qemu_mallocz(sizeof(ScoopInfo)); + memset(s, 0, sizeof(ScoopInfo)); s->status = 0x02; s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16); |