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-rw-r--r--hw/acpi/piix4.c12
-rw-r--r--hw/audio/intel-hda.c40
-rw-r--r--hw/char/serial.c128
-rw-r--r--hw/dma/xilinx_axidma.c3
-rw-r--r--hw/i386/pc.c5
-rw-r--r--hw/i386/pc_piix.c18
-rw-r--r--hw/i386/pc_q35.c16
-rw-r--r--hw/i386/smbios.c57
-rw-r--r--hw/ide/core.c1
-rw-r--r--hw/intc/xilinx_intc.c6
-rw-r--r--hw/misc/ivshmem.c1
-rw-r--r--hw/net/vmxnet3.c2
-rw-r--r--hw/net/xilinx_axienet.c2
-rw-r--r--hw/ppc/spapr_rtas.c28
-rw-r--r--hw/s390x/css.c2
-rw-r--r--hw/s390x/virtio-ccw.c8
-rw-r--r--hw/scsi/vmw_pvscsi.c2
-rw-r--r--hw/xen/xen_pt_config_init.c4
18 files changed, 174 insertions, 161 deletions
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index e6525ac3ba..756df3bee2 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
PIIX4PMState *s = opaque;
uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
- PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
+ PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
return val;
}
@@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
acpi_gpe_ioport_writeb(&s->ar, addr, val);
pm_update_sci(s);
- PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
+ PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
}
static const MemoryRegionOps piix4_gpe_ops = {
@@ -553,15 +553,15 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
/* Manufacture an "up" value to cause a device check on any hotplug
* slot with a device. Extra device checks are harmless. */
val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
- PIIX4_DPRINTF("pci_up_read %x\n", val);
+ PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val);
break;
case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
val = s->pci0_status.down;
- PIIX4_DPRINTF("pci_down_read %x\n", val);
+ PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val);
break;
case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
/* No feature defined yet */
- PIIX4_DPRINTF("pci_features_read %x\n", val);
+ PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val);
break;
case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
val = s->pci0_hotplug_enable;
@@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data,
switch (addr) {
case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
acpi_piix_eject_slot(opaque, (uint32_t)data);
- PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n",
+ PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
addr, data);
break;
default:
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index 1016af0204..3ac90d510d 100644
--- a/hw/audio/intel-hda.c
+++ b/hw/audio/intel-hda.c
@@ -189,6 +189,11 @@ struct IntelHDAState {
uint32_t msi;
};
+#define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
+
+#define INTEL_HDA(obj) \
+ OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
+
struct IntelHDAReg {
const char *name; /* register name */
uint32_t size; /* size in bytes */
@@ -498,7 +503,7 @@ static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool runn
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
{
if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
- intel_hda_reset(&d->pci.qdev);
+ intel_hda_reset(DEVICE(d));
}
}
@@ -1102,7 +1107,7 @@ static const MemoryRegionOps intel_hda_mmio_ops = {
static void intel_hda_reset(DeviceState *dev)
{
BusChild *kid;
- IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
+ IntelHDAState *d = INTEL_HDA(dev);
HDACodecDevice *cdev;
intel_hda_regs_reset(d);
@@ -1120,7 +1125,7 @@ static void intel_hda_reset(DeviceState *dev)
static int intel_hda_init(PCIDevice *pci)
{
- IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
+ IntelHDAState *d = INTEL_HDA(pci);
uint8_t *conf = d->pci.config;
d->name = object_get_typename(OBJECT(d));
@@ -1137,7 +1142,7 @@ static int intel_hda_init(PCIDevice *pci)
msi_init(&d->pci, 0x50, 1, true, false);
}
- hda_codec_bus_init(&d->pci.qdev, &d->codecs,
+ hda_codec_bus_init(DEVICE(pci), &d->codecs,
intel_hda_response, intel_hda_xfer);
return 0;
@@ -1145,7 +1150,7 @@ static int intel_hda_init(PCIDevice *pci)
static void intel_hda_exit(PCIDevice *pci)
{
- IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
+ IntelHDAState *d = INTEL_HDA(pci);
msi_uninit(&d->pci);
memory_region_destroy(&d->mmio);
@@ -1232,7 +1237,7 @@ static Property intel_hda_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static void intel_hda_class_init_common(ObjectClass *klass)
+static void intel_hda_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -1251,7 +1256,6 @@ static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- intel_hda_class_init_common(klass);
k->device_id = 0x2668;
k->revision = 1;
dc->desc = "Intel HD Audio Controller (ich6)";
@@ -1262,23 +1266,28 @@ static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- intel_hda_class_init_common(klass);
k->device_id = 0x293e;
k->revision = 3;
dc->desc = "Intel HD Audio Controller (ich9)";
}
-static const TypeInfo intel_hda_info_ich6 = {
- .name = "intel-hda",
+static const TypeInfo intel_hda_info = {
+ .name = TYPE_INTEL_HDA_GENERIC,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(IntelHDAState),
+ .class_init = intel_hda_class_init,
+ .abstract = true,
+};
+
+static const TypeInfo intel_hda_info_ich6 = {
+ .name = "intel-hda",
+ .parent = TYPE_INTEL_HDA_GENERIC,
.class_init = intel_hda_class_init_ich6,
};
static const TypeInfo intel_hda_info_ich9 = {
.name = "ich9-intel-hda",
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(IntelHDAState),
+ .parent = TYPE_INTEL_HDA_GENERIC,
.class_init = intel_hda_class_init_ich9,
};
@@ -1306,12 +1315,12 @@ static const TypeInfo hda_codec_device_type_info = {
*/
static int intel_hda_and_codec_init(PCIBus *bus)
{
- PCIDevice *controller;
+ DeviceState *controller;
BusState *hdabus;
DeviceState *codec;
- controller = pci_create_simple(bus, -1, "intel-hda");
- hdabus = QLIST_FIRST(&controller->qdev.child_bus);
+ controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
+ hdabus = QLIST_FIRST(&controller->child_bus);
codec = qdev_create(hdabus, "hda-duplex");
qdev_init_nofail(codec);
return 0;
@@ -1320,6 +1329,7 @@ static int intel_hda_and_codec_init(PCIBus *bus)
static void intel_hda_register_types(void)
{
type_register_static(&hda_codec_bus_info);
+ type_register_static(&intel_hda_info);
type_register_static(&intel_hda_info_ich6);
type_register_static(&intel_hda_info_ich9);
type_register_static(&hda_codec_device_type_info);
diff --git a/hw/char/serial.c b/hw/char/serial.c
index f2701e8c54..b537e426b0 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -92,8 +92,6 @@
#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
#define UART_FCR_FE 0x01 /* FIFO Enable */
-#define XMIT_FIFO 0
-#define RECV_FIFO 1
#define MAX_XMIT_RETRY 4
#ifdef DEBUG_SERIAL
@@ -106,50 +104,14 @@ do {} while (0)
static void serial_receive1(void *opaque, const uint8_t *buf, int size);
-static void fifo_clear(SerialState *s, int fifo)
+static inline void recv_fifo_put(SerialState *s, uint8_t chr)
{
- SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
- memset(f->data, 0, UART_FIFO_LENGTH);
- f->count = 0;
- f->head = 0;
- f->tail = 0;
-}
-
-static int fifo_put(SerialState *s, int fifo, uint8_t chr)
-{
- SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
-
/* Receive overruns do not overwrite FIFO contents. */
- if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
-
- f->data[f->head++] = chr;
-
- if (f->head == UART_FIFO_LENGTH)
- f->head = 0;
- }
-
- if (f->count < UART_FIFO_LENGTH)
- f->count++;
- else if (fifo == RECV_FIFO)
+ if (!fifo8_is_full(&s->recv_fifo)) {
+ fifo8_push(&s->recv_fifo, chr);
+ } else {
s->lsr |= UART_LSR_OE;
-
- return 1;
-}
-
-static uint8_t fifo_get(SerialState *s, int fifo)
-{
- SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
- uint8_t c;
-
- if(f->count == 0)
- return 0;
-
- c = f->data[f->tail++];
- if (f->tail == UART_FIFO_LENGTH)
- f->tail = 0;
- f->count--;
-
- return c;
+ }
}
static void serial_update_irq(SerialState *s)
@@ -165,7 +127,7 @@ static void serial_update_irq(SerialState *s)
tmp_iir = UART_IIR_CTI;
} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
(!(s->fcr & UART_FCR_FE) ||
- s->recv_fifo.count >= s->recv_fifo.itl)) {
+ s->recv_fifo.num >= s->recv_fifo_itl)) {
tmp_iir = UART_IIR_RDI;
} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
tmp_iir = UART_IIR_THRI;
@@ -262,9 +224,11 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
if (s->tsr_retry <= 0) {
if (s->fcr & UART_FCR_FE) {
- s->tsr = fifo_get(s,XMIT_FIFO);
- if (!s->xmit_fifo.count)
+ s->tsr = fifo8_is_full(&s->xmit_fifo) ?
+ 0 : fifo8_pop(&s->xmit_fifo);
+ if (!s->xmit_fifo.num) {
s->lsr |= UART_LSR_THRE;
+ }
} else if ((s->lsr & UART_LSR_THRE)) {
return FALSE;
} else {
@@ -316,16 +280,16 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
} else {
s->thr = (uint8_t) val;
if(s->fcr & UART_FCR_FE) {
- fifo_put(s, XMIT_FIFO, s->thr);
- s->thr_ipending = 0;
+ /* xmit overruns overwrite data, so make space if needed */
+ if (fifo8_is_full(&s->xmit_fifo)) {
+ fifo8_pop(&s->xmit_fifo);
+ }
+ fifo8_push(&s->xmit_fifo, s->thr);
s->lsr &= ~UART_LSR_TEMT;
- s->lsr &= ~UART_LSR_THRE;
- serial_update_irq(s);
- } else {
- s->thr_ipending = 0;
- s->lsr &= ~UART_LSR_THRE;
- serial_update_irq(s);
}
+ s->thr_ipending = 0;
+ s->lsr &= ~UART_LSR_THRE;
+ serial_update_irq(s);
serial_xmit(NULL, G_IO_OUT, s);
}
break;
@@ -367,28 +331,28 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
if (val & UART_FCR_RFR) {
qemu_del_timer(s->fifo_timeout_timer);
s->timeout_ipending=0;
- fifo_clear(s,RECV_FIFO);
+ fifo8_reset(&s->recv_fifo);
}
if (val & UART_FCR_XFR) {
- fifo_clear(s,XMIT_FIFO);
+ fifo8_reset(&s->xmit_fifo);
}
if (val & UART_FCR_FE) {
s->iir |= UART_IIR_FE;
- /* Set RECV_FIFO trigger Level */
+ /* Set recv_fifo trigger Level */
switch (val & 0xC0) {
case UART_FCR_ITL_1:
- s->recv_fifo.itl = 1;
+ s->recv_fifo_itl = 1;
break;
case UART_FCR_ITL_2:
- s->recv_fifo.itl = 4;
+ s->recv_fifo_itl = 4;
break;
case UART_FCR_ITL_3:
- s->recv_fifo.itl = 8;
+ s->recv_fifo_itl = 8;
break;
case UART_FCR_ITL_4:
- s->recv_fifo.itl = 14;
+ s->recv_fifo_itl = 14;
break;
}
} else
@@ -460,11 +424,13 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
ret = s->divider & 0xff;
} else {
if(s->fcr & UART_FCR_FE) {
- ret = fifo_get(s,RECV_FIFO);
- if (s->recv_fifo.count == 0)
+ ret = fifo8_is_full(&s->recv_fifo) ?
+ 0 : fifo8_pop(&s->recv_fifo);
+ if (s->recv_fifo.num == 0) {
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
- else
+ } else {
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
+ }
s->timeout_ipending = 0;
} else {
ret = s->rbr;
@@ -534,15 +500,21 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
static int serial_can_receive(SerialState *s)
{
if(s->fcr & UART_FCR_FE) {
- if(s->recv_fifo.count < UART_FIFO_LENGTH)
- /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
- advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
- effectively overriding the ITL that the guest has set. */
- return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
- else
- return 0;
+ if (s->recv_fifo.num < UART_FIFO_LENGTH) {
+ /*
+ * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
+ * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
+ * effect will be to almost always fill the fifo completely before
+ * the guest has a chance to respond, effectively overriding the ITL
+ * that the guest has set.
+ */
+ return (s->recv_fifo.num <= s->recv_fifo_itl) ?
+ s->recv_fifo_itl - s->recv_fifo.num : 1;
+ } else {
+ return 0;
+ }
} else {
- return !(s->lsr & UART_LSR_DR);
+ return !(s->lsr & UART_LSR_DR);
}
}
@@ -550,7 +522,7 @@ static void serial_receive_break(SerialState *s)
{
s->rbr = 0;
/* When the LSR_DR is set a null byte is pushed into the fifo */
- fifo_put(s, RECV_FIFO, '\0');
+ recv_fifo_put(s, '\0');
s->lsr |= UART_LSR_BI | UART_LSR_DR;
serial_update_irq(s);
}
@@ -558,7 +530,7 @@ static void serial_receive_break(SerialState *s)
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
static void fifo_timeout_int (void *opaque) {
SerialState *s = opaque;
- if (s->recv_fifo.count) {
+ if (s->recv_fifo.num) {
s->timeout_ipending = 1;
serial_update_irq(s);
}
@@ -580,7 +552,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size)
if(s->fcr & UART_FCR_FE) {
int i;
for (i = 0; i < size; i++) {
- fifo_put(s, RECV_FIFO, buf[i]);
+ recv_fifo_put(s, buf[i]);
}
s->lsr |= UART_LSR_DR;
/* call the timeout receive callback in 4 char transmit time */
@@ -660,8 +632,8 @@ static void serial_reset(void *opaque)
s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
s->poll_msl = 0;
- fifo_clear(s,RECV_FIFO);
- fifo_clear(s,XMIT_FIFO);
+ fifo8_reset(&s->recv_fifo);
+ fifo8_reset(&s->xmit_fifo);
s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
@@ -684,6 +656,8 @@ void serial_realize_core(SerialState *s, Error **errp)
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
serial_event, s);
+ fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
+ fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
}
void serial_exit_core(SerialState *s)
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index 3a3ef8aff3..50054cf851 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -514,8 +514,9 @@ static void axidma_write(void *opaque, hwaddr addr,
break;
}
if (sid == 1 && d->notify) {
- d->notify(d->notify_opaque);
+ StreamCanPushNotifyFn notifytmp = d->notify;
d->notify = NULL;
+ notifytmp(d->notify_opaque);
}
stream_update_irq(s);
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0ad062c093..e0fbb860ed 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -934,6 +934,11 @@ void pc_hot_add_cpu(const int64_t id, Error **errp)
DeviceState *icc_bridge;
int64_t apic_id = x86_cpu_apic_id_from_index(id);
+ if (id < 0) {
+ error_setg(errp, "Invalid CPU id: %" PRIi64, id);
+ return;
+ }
+
if (cpu_exists(apic_id)) {
error_setg(errp, "Unable to add CPU: %" PRIi64
", it already exists", id);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index af1e9afb04..97362f2c26 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -327,8 +327,8 @@ static void pc_xen_hvm_init(QEMUMachineInitArgs *args)
}
#endif
-static QEMUMachine pc_i440fx_machine_v1_5 = {
- .name = "pc-i440fx-1.5",
+static QEMUMachine pc_i440fx_machine_v1_6 = {
+ .name = "pc-i440fx-1.6",
.alias = "pc",
.desc = "Standard PC (i440FX + PIIX, 1996)",
.init = pc_init_pci,
@@ -338,6 +338,19 @@ static QEMUMachine pc_i440fx_machine_v1_5 = {
DEFAULT_MACHINE_OPTIONS,
};
+static QEMUMachine pc_i440fx_machine_v1_5 = {
+ .name = "pc-i440fx-1.5",
+ .desc = "Standard PC (i440FX + PIIX, 1996)",
+ .init = pc_init_pci,
+ .hot_add_cpu = pc_hot_add_cpu,
+ .max_cpus = 255,
+ .compat_props = (GlobalProperty[]) {
+ PC_COMPAT_1_5,
+ { /* end of list */ }
+ },
+ DEFAULT_MACHINE_OPTIONS,
+};
+
static QEMUMachine pc_i440fx_machine_v1_4 = {
.name = "pc-i440fx-1.4",
.desc = "Standard PC (i440FX + PIIX, 1996)",
@@ -735,6 +748,7 @@ static QEMUMachine xenfv_machine = {
static void pc_machine_init(void)
{
+ qemu_register_machine(&pc_i440fx_machine_v1_6);
qemu_register_machine(&pc_i440fx_machine_v1_5);
qemu_register_machine(&pc_i440fx_machine_v1_4);
qemu_register_machine(&pc_machine_v1_3);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 7888dfe03f..bb0ce6ae6b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -215,13 +215,26 @@ static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
pc_q35_init(args);
}
+static QEMUMachine pc_q35_machine_v1_6 = {
+ .name = "pc-q35-1.6",
+ .alias = "q35",
+ .desc = "Standard PC (Q35 + ICH9, 2009)",
+ .init = pc_q35_init,
+ .hot_add_cpu = pc_hot_add_cpu,
+ .max_cpus = 255,
+ DEFAULT_MACHINE_OPTIONS,
+};
+
static QEMUMachine pc_q35_machine_v1_5 = {
.name = "pc-q35-1.5",
- .alias = "q35",
.desc = "Standard PC (Q35 + ICH9, 2009)",
.init = pc_q35_init,
.hot_add_cpu = pc_hot_add_cpu,
.max_cpus = 255,
+ .compat_props = (GlobalProperty[]) {
+ PC_COMPAT_1_5,
+ { /* end of list */ }
+ },
DEFAULT_MACHINE_OPTIONS,
};
@@ -239,6 +252,7 @@ static QEMUMachine pc_q35_machine_v1_4 = {
static void pc_q35_machine_init(void)
{
+ qemu_register_machine(&pc_q35_machine_v1_6);
qemu_register_machine(&pc_q35_machine_v1_5);
qemu_register_machine(&pc_q35_machine_v1_4);
}
diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c
index c00bb2fad8..e708cb8919 100644
--- a/hw/i386/smbios.c
+++ b/hw/i386/smbios.c
@@ -13,6 +13,7 @@
* GNU GPL, version 2 or (at your option) any later version.
*/
+#include "qemu/error-report.h"
#include "sysemu/sysemu.h"
#include "hw/i386/smbios.h"
#include "hw/loader.h"
@@ -48,8 +49,7 @@ static int smbios_type4_count = 0;
static void smbios_validate_table(void)
{
if (smbios_type4_count && smbios_type4_count != smp_cpus) {
- fprintf(stderr,
- "Number of SMBIOS Type 4 tables must match cpu count.\n");
+ error_report("Number of SMBIOS Type 4 tables must match cpu count");
exit(1);
}
}
@@ -82,16 +82,16 @@ static void smbios_check_collision(int type, int entry)
if (entry == SMBIOS_TABLE_ENTRY && header->type == SMBIOS_FIELD_ENTRY) {
struct smbios_field *field = (void *)header;
if (type == field->type) {
- fprintf(stderr, "SMBIOS type %d field already defined, "
- "cannot add table\n", type);
+ error_report("SMBIOS type %d field already defined, "
+ "cannot add table", type);
exit(1);
}
} else if (entry == SMBIOS_FIELD_ENTRY &&
header->type == SMBIOS_TABLE_ENTRY) {
struct smbios_structure_header *table = (void *)(header + 1);
if (type == table->type) {
- fprintf(stderr, "SMBIOS type %d table already defined, "
- "cannot add field\n", type);
+ error_report("SMBIOS type %d table already defined, "
+ "cannot add field", type);
exit(1);
}
}
@@ -99,7 +99,7 @@ static void smbios_check_collision(int type, int entry)
}
}
-void smbios_add_field(int type, int offset, int len, void *data)
+void smbios_add_field(int type, int offset, const void *data, size_t len)
{
struct smbios_field *field;
@@ -127,24 +127,29 @@ void smbios_add_field(int type, int offset, int len, void *data)
static void smbios_build_type_0_fields(const char *t)
{
char buf[1024];
+ unsigned char major, minor;
if (get_param_value(buf, sizeof(buf), "vendor", t))
smbios_add_field(0, offsetof(struct smbios_type_0, vendor_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "version", t))
smbios_add_field(0, offsetof(struct smbios_type_0, bios_version_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "date", t))
smbios_add_field(0, offsetof(struct smbios_type_0,
bios_release_date_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "release", t)) {
- int major, minor;
- sscanf(buf, "%d.%d", &major, &minor);
+ if (sscanf(buf, "%hhu.%hhu", &major, &minor) != 2) {
+ error_report("Invalid release");
+ exit(1);
+ }
smbios_add_field(0, offsetof(struct smbios_type_0,
- system_bios_major_release), 1, &major);
+ system_bios_major_release),
+ &major, 1);
smbios_add_field(0, offsetof(struct smbios_type_0,
- system_bios_minor_release), 1, &minor);
+ system_bios_minor_release),
+ &minor, 1);
}
}
@@ -154,28 +159,28 @@ static void smbios_build_type_1_fields(const char *t)
if (get_param_value(buf, sizeof(buf), "manufacturer", t))
smbios_add_field(1, offsetof(struct smbios_type_1, manufacturer_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "product", t))
smbios_add_field(1, offsetof(struct smbios_type_1, product_name_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "version", t))
smbios_add_field(1, offsetof(struct smbios_type_1, version_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "serial", t))
smbios_add_field(1, offsetof(struct smbios_type_1, serial_number_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "uuid", t)) {
if (qemu_uuid_parse(buf, qemu_uuid) != 0) {
- fprintf(stderr, "Invalid SMBIOS UUID string\n");
+ error_report("Invalid UUID");
exit(1);
}
}
if (get_param_value(buf, sizeof(buf), "sku", t))
smbios_add_field(1, offsetof(struct smbios_type_1, sku_number_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
if (get_param_value(buf, sizeof(buf), "family", t))
smbios_add_field(1, offsetof(struct smbios_type_1, family_str),
- strlen(buf) + 1, buf);
+ buf, strlen(buf) + 1);
}
int smbios_entry_add(const char *t)
@@ -188,7 +193,7 @@ int smbios_entry_add(const char *t)
int size = get_image_size(buf);
if (size == -1 || size < sizeof(struct smbios_structure_header)) {
- fprintf(stderr, "Cannot read smbios file %s\n", buf);
+ error_report("Cannot read SMBIOS file %s", buf);
exit(1);
}
@@ -204,7 +209,7 @@ int smbios_entry_add(const char *t)
table->header.length = cpu_to_le16(sizeof(*table) + size);
if (load_image(buf, table->data) != size) {
- fprintf(stderr, "Failed to load smbios file %s", buf);
+ error_report("Failed to load SMBIOS file %s", buf);
exit(1);
}
@@ -230,12 +235,12 @@ int smbios_entry_add(const char *t)
smbios_build_type_1_fields(t);
return 0;
default:
- fprintf(stderr, "Don't know how to build fields for SMBIOS type "
- "%ld\n", type);
+ error_report("Don't know how to build fields for SMBIOS type %ld",
+ type);
exit(1);
}
}
- fprintf(stderr, "smbios: must specify type= or file=\n");
+ error_report("Must specify type= or file=");
return -1;
}
diff --git a/hw/ide/core.c b/hw/ide/core.c
index c7a80413be..9926d9202b 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -814,6 +814,7 @@ void ide_flush_cache(IDEState *s)
return;
}
+ s->status |= BUSY_STAT;
bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
bdrv_aio_flush(s->bs, ide_flush_cb, s);
}
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index b106e724ab..5df7008e2f 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -66,11 +66,7 @@ static void update_irq(struct xlx_pic *p)
i = ~0;
p->regs[R_IVR] = i;
- if ((p->regs[R_MER] & 1) && p->regs[R_IPR]) {
- qemu_irq_raise(p->parent_irq);
- } else {
- qemu_irq_lower(p->parent_irq);
- }
+ qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
}
static uint64_t
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index a19a6d6d8c..5658f733f4 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -735,6 +735,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
if (s->shmobj == NULL) {
fprintf(stderr, "Must specify 'chardev' or 'shm' to ivshmem\n");
+ exit(1);
}
IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj);
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 5f483e7f1e..4c575e55a7 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -1892,7 +1892,7 @@ static void vmxnet3_net_uninit(VMXNET3State *s)
vmxnet_tx_pkt_reset(s->tx_pkt);
vmxnet_tx_pkt_uninit(s->tx_pkt);
vmxnet_rx_pkt_uninit(s->rx_pkt);
- qemu_del_net_client(qemu_get_queue(s->nic));
+ qemu_del_nic(s->nic);
}
static void vmxnet3_net_init(VMXNET3State *s)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 8989e95297..2ca1511c06 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -575,7 +575,7 @@ static void enet_write(void *opaque, hwaddr addr,
break;
case R_MC:
- value &= ((1 < 7) - 1);
+ value &= ((1 << 7) - 1);
/* Enable the MII. */
if (value & MC_EN) {
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 8ecaa5f8ec..f4bd3c9d86 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -130,7 +130,6 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr,
uint32_t nret, target_ulong rets)
{
target_ulong id;
- CPUPPCState *env;
CPUState *cpu;
if (nargs != 1 || nret != 2) {
@@ -139,12 +138,8 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr,
}
id = rtas_ld(args, 0);
- for (env = first_cpu; env; env = env->next_cpu) {
- cpu = CPU(ppc_env_get_cpu(env));
- if (cpu->cpu_index != id) {
- continue;
- }
-
+ cpu = qemu_get_cpu(id);
+ if (cpu != NULL) {
if (cpu->halted) {
rtas_st(rets, 1, 0);
} else {
@@ -165,8 +160,7 @@ static void rtas_start_cpu(sPAPREnvironment *spapr,
uint32_t nret, target_ulong rets)
{
target_ulong id, start, r3;
- CPUState *cpu;
- CPUPPCState *env;
+ CPUState *cs;
if (nargs != 3 || nret != 1) {
rtas_st(rets, 0, -3);
@@ -177,14 +171,12 @@ static void rtas_start_cpu(sPAPREnvironment *spapr,
start = rtas_ld(args, 1);
r3 = rtas_ld(args, 2);
- for (env = first_cpu; env; env = env->next_cpu) {
- cpu = CPU(ppc_env_get_cpu(env));
-
- if (cpu->cpu_index != id) {
- continue;
- }
+ cs = qemu_get_cpu(id);
+ if (cs != NULL) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
- if (!cpu->halted) {
+ if (!cs->halted) {
rtas_st(rets, 0, -1);
return;
}
@@ -197,9 +189,9 @@ static void rtas_start_cpu(sPAPREnvironment *spapr,
env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
env->nip = start;
env->gpr[3] = r3;
- cpu->halted = 0;
+ cs->halted = 0;
- qemu_cpu_kick(cpu);
+ qemu_cpu_kick(cs);
rtas_st(rets, 0, 0);
return;
diff --git a/hw/s390x/css.c b/hw/s390x/css.c
index e526a1c86c..f82abfe029 100644
--- a/hw/s390x/css.c
+++ b/hw/s390x/css.c
@@ -777,7 +777,7 @@ int css_do_tsch(SubchDev *sch, IRB *target_irb)
(p->chars & PMCW_CHARS_MASK_CSENSE)) {
irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data));
- irb.esw[1] = 0x02000000 | (sizeof(sch->sense_data) << 8);
+ irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8);
}
}
/* Store the irb to the guest. */
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 5f5e267558..44f5772bb2 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -328,10 +328,10 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EINVAL;
break;
}
- indicators = ldq_phys(ccw.cda);
- if (!indicators) {
+ if (!ccw.cda) {
ret = -EFAULT;
} else {
+ indicators = ldq_phys(ccw.cda);
dev->indicators = indicators;
sch->curr_status.scsw.count = ccw.count - sizeof(indicators);
ret = 0;
@@ -348,10 +348,10 @@ static int virtio_ccw_cb(SubchDev *sch, CCW1 ccw)
ret = -EINVAL;
break;
}
- indicators = ldq_phys(ccw.cda);
- if (!indicators) {
+ if (!ccw.cda) {
ret = -EFAULT;
} else {
+ indicators = ldq_phys(ccw.cda);
dev->indicators2 = indicators;
sch->curr_status.scsw.count = ccw.count - sizeof(indicators);
ret = 0;
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 48d12f42dd..446f72374b 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -389,7 +389,7 @@ pvscsi_process_completion_queue(void *opaque)
QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
g_free(pvscsi_req);
- has_completed++;
+ has_completed = true;
}
if (has_completed) {
diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
index 01872db5b7..8ccc2e4b9c 100644
--- a/hw/xen/xen_pt_config_init.c
+++ b/hw/xen/xen_pt_config_init.c
@@ -1777,12 +1777,12 @@ static int xen_pt_config_reg_init(XenPCIPassthroughState *s,
rc = reg->init(s, reg_entry->reg,
reg_grp->base_offset + reg->offset, &data);
if (rc < 0) {
- free(reg_entry);
+ g_free(reg_entry);
return rc;
}
if (data == XEN_PT_INVALID_REG) {
/* free unused BAR register entry */
- free(reg_entry);
+ g_free(reg_entry);
return 0;
}
/* set register value */
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-19 06:31:59 +0000