aboutsummaryrefslogtreecommitdiff
path: root/hw/timer
diff options
context:
space:
mode:
Diffstat (limited to 'hw/timer')
-rw-r--r--hw/timer/arm_mptimer.c12
-rw-r--r--hw/timer/arm_timer.c1
-rw-r--r--hw/timer/cadence_ttc.c6
-rw-r--r--hw/timer/etraxfs_timer.c2
-rw-r--r--hw/timer/exynos4210_mct.c3
-rw-r--r--hw/timer/exynos4210_pwm.c1
-rw-r--r--hw/timer/grlib_gptimer.c2
-rw-r--r--hw/timer/hpet.c20
-rw-r--r--hw/timer/i8254.c26
-rw-r--r--hw/timer/i8254_common.c4
-rw-r--r--hw/timer/imx_epit.c1
-rw-r--r--hw/timer/imx_gpt.c1
-rw-r--r--hw/timer/lm32_timer.c1
-rw-r--r--hw/timer/m48t59.c18
-rw-r--r--hw/timer/mc146818rtc.c50
-rw-r--r--hw/timer/omap_gptimer.c24
-rw-r--r--hw/timer/omap_synctimer.c2
-rw-r--r--hw/timer/pl031.c19
-rw-r--r--hw/timer/puv3_ost.c1
-rw-r--r--hw/timer/pxa2xx_timer.c34
-rw-r--r--hw/timer/sh_timer.c1
-rw-r--r--hw/timer/slavio_timer.c1
-rw-r--r--hw/timer/tusb6010.c12
-rw-r--r--hw/timer/twl92230.c14
-rw-r--r--hw/timer/xilinx_timer.c1
25 files changed, 136 insertions, 121 deletions
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index 92773155d2..8020c9f4b5 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -81,10 +81,10 @@ static void timerblock_reload(TimerBlock *tb, int restart)
return;
}
if (restart) {
- tb->tick = qemu_get_clock_ns(vm_clock);
+ tb->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
tb->tick += (int64_t)tb->count * timerblock_scale(tb);
- qemu_mod_timer(tb->timer, tb->tick);
+ timer_mod(tb->timer, tb->tick);
}
static void timerblock_tick(void *opaque)
@@ -113,7 +113,7 @@ static uint64_t timerblock_read(void *opaque, hwaddr addr,
return 0;
}
/* Slow and ugly, but hopefully won't happen too often. */
- val = tb->tick - qemu_get_clock_ns(vm_clock);
+ val = tb->tick - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
val /= timerblock_scale(tb);
if (val < 0) {
val = 0;
@@ -140,7 +140,7 @@ static void timerblock_write(void *opaque, hwaddr addr,
case 4: /* Counter. */
if ((tb->control & 1) && tb->count) {
/* Cancel the previous timer. */
- qemu_del_timer(tb->timer);
+ timer_del(tb->timer);
}
tb->count = value;
if (tb->control & 1) {
@@ -211,7 +211,7 @@ static void timerblock_reset(TimerBlock *tb)
tb->status = 0;
tb->tick = 0;
if (tb->timer) {
- qemu_del_timer(tb->timer);
+ timer_del(tb->timer);
}
}
@@ -248,7 +248,7 @@ static int arm_mptimer_init(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < s->num_cpu; i++) {
TimerBlock *tb = &s->timerblock[i];
- tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
+ tb->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, timerblock_tick, tb);
sysbus_init_irq(dev, &tb->irq);
memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
"arm_mptimer_timerblock", 0x20);
diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c
index acfea59779..a47afde23a 100644
--- a/hw/timer/arm_timer.c
+++ b/hw/timer/arm_timer.c
@@ -12,6 +12,7 @@
#include "qemu-common.h"
#include "hw/qdev.h"
#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
/* Common timer implementation. */
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
index 888f9ce000..a279bced78 100644
--- a/hw/timer/cadence_ttc.c
+++ b/hw/timer/cadence_ttc.c
@@ -172,7 +172,7 @@ static void cadence_timer_run(CadenceTimerState *s)
event_interval = next_value - (int64_t)s->reg_value;
event_interval = (event_interval < 0) ? -event_interval : event_interval;
- qemu_mod_timer(s->timer, s->cpu_time +
+ timer_mod(s->timer, s->cpu_time +
cadence_timer_get_ns(s, event_interval));
}
@@ -184,7 +184,7 @@ static void cadence_timer_sync(CadenceTimerState *s)
(int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
uint64_t old_time = s->cpu_time;
- s->cpu_time = qemu_get_clock_ns(vm_clock);
+ s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
DB_PRINT("cpu time: %lld ns\n", (long long)old_time);
if (!s->cpu_time_valid || old_time == s->cpu_time) {
@@ -401,7 +401,7 @@ static void cadence_timer_init(uint32_t freq, CadenceTimerState *s)
cadence_timer_reset(s);
- s->timer = qemu_new_timer_ns(vm_clock, cadence_timer_tick, s);
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s);
}
static int cadence_ttc_init(SysBusDevice *dev)
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
index a38d9e4eb6..aee4990eb1 100644
--- a/hw/timer/etraxfs_timer.c
+++ b/hw/timer/etraxfs_timer.c
@@ -93,7 +93,7 @@ timer_read(void *opaque, hwaddr addr, unsigned int size)
r = ptimer_get_count(t->ptimer_t1);
break;
case R_TIME:
- r = qemu_get_clock_ns(vm_clock) / 10;
+ r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
break;
case RW_INTR_MASK:
r = t->rw_intr_mask;
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index a8009a4316..86f4fcd3e8 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -54,6 +54,7 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
+#include "qemu/main-loop.h"
#include "qemu-common.h"
#include "hw/ptimer.h"
@@ -905,7 +906,7 @@ static void exynos4210_ltick_event(void *opaque)
/* raise interrupt if enabled */
if (s->reg.int_enb & L_INT_INTENB_ICNTEIE) {
#ifdef DEBUG_MCT
- time2[s->id] = qemu_get_clock_ns(vm_clock);
+ time2[s->id] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
DPRINTF("local timer[%d] IRQ: %llx\n", s->id,
time2[s->id] - time1[s->id]);
time1[s->id] = time2[s->id];
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
index a52f0f6c6b..1aa8f4d07a 100644
--- a/hw/timer/exynos4210_pwm.c
+++ b/hw/timer/exynos4210_pwm.c
@@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qemu-common.h"
+#include "qemu/main-loop.h"
#include "hw/ptimer.h"
#include "hw/arm/exynos4210.h"
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
index 7c1055a99c..74c16d6c90 100644
--- a/hw/timer/grlib_gptimer.c
+++ b/hw/timer/grlib_gptimer.c
@@ -25,6 +25,8 @@
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
+#include "qemu/timer.h"
+#include "qemu/main-loop.h"
#include "trace.h"
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 648b38362d..fcd22aea59 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -152,7 +152,7 @@ static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
static uint64_t hpet_get_ticks(HPETState *s)
{
- return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
+ return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset);
}
/*
@@ -233,7 +233,7 @@ static int hpet_post_load(void *opaque, int version_id)
HPETState *s = opaque;
/* Recalculate the offset between the main counter and guest time */
- s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
+ s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
/* Push number of timers into capability returned via HPET_ID */
s->capability &= ~HPET_ID_NUM_TIM_MASK;
@@ -332,12 +332,12 @@ static void hpet_timer(void *opaque)
}
}
diff = hpet_calculate_diff(t, cur_tick);
- qemu_mod_timer(t->qemu_timer,
- qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
+ timer_mod(t->qemu_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
if (t->wrap_flag) {
diff = hpet_calculate_diff(t, cur_tick);
- qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
+ timer_mod(t->qemu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(int64_t)ticks_to_ns(diff));
t->wrap_flag = 0;
}
@@ -365,13 +365,13 @@ static void hpet_set_timer(HPETTimer *t)
t->wrap_flag = 1;
}
}
- qemu_mod_timer(t->qemu_timer,
- qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
+ timer_mod(t->qemu_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
}
static void hpet_del_timer(HPETTimer *t)
{
- qemu_del_timer(t->qemu_timer);
+ timer_del(t->qemu_timer);
update_irq(t, 0);
}
@@ -567,7 +567,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
/* Enable main counter and interrupt generation. */
s->hpet_offset =
- ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
+ ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
for (i = 0; i < s->num_timers; i++) {
if ((&s->timer[i])->cmp != ~0ULL) {
hpet_set_timer(&s->timer[i]);
@@ -726,7 +726,7 @@ static void hpet_realize(DeviceState *dev, Error **errp)
}
for (i = 0; i < HPET_MAX_TIMERS; i++) {
timer = &s->timer[i];
- timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
+ timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
timer->tn = i;
timer->state = s;
}
diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c
index cd5214064f..cdbf481951 100644
--- a/hw/timer/i8254.c
+++ b/hw/timer/i8254.c
@@ -51,7 +51,7 @@ static int pit_get_count(PITChannelState *s)
uint64_t d;
int counter;
- d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
+ d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ,
get_ticks_per_sec());
switch(s->mode) {
case 0:
@@ -85,7 +85,7 @@ static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
case 5:
if (sc->gate < val) {
/* restart counting on rising edge */
- sc->count_load_time = qemu_get_clock_ns(vm_clock);
+ sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pit_irq_timer_update(sc, sc->count_load_time);
}
break;
@@ -93,7 +93,7 @@ static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
case 3:
if (sc->gate < val) {
/* restart counting on rising edge */
- sc->count_load_time = qemu_get_clock_ns(vm_clock);
+ sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pit_irq_timer_update(sc, sc->count_load_time);
}
/* XXX: disable/enable counting */
@@ -106,7 +106,7 @@ static inline void pit_load_count(PITChannelState *s, int val)
{
if (val == 0)
val = 0x10000;
- s->count_load_time = qemu_get_clock_ns(vm_clock);
+ s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->count = val;
pit_irq_timer_update(s, s->count_load_time);
}
@@ -143,7 +143,7 @@ static void pit_ioport_write(void *opaque, hwaddr addr,
/* XXX: add BCD and null count */
s->status =
(pit_get_out(s,
- qemu_get_clock_ns(vm_clock)) << 7) |
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) |
(s->rw_mode << 4) |
(s->mode << 1) |
s->bcd;
@@ -260,9 +260,9 @@ static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
#endif
s->next_transition_time = expire_time;
if (expire_time != -1)
- qemu_mod_timer(s->irq_timer, expire_time);
+ timer_mod(s->irq_timer, expire_time);
else
- qemu_del_timer(s->irq_timer);
+ timer_del(s->irq_timer);
}
static void pit_irq_timer(void *opaque)
@@ -281,7 +281,7 @@ static void pit_reset(DeviceState *dev)
s = &pit->channels[0];
if (!s->irq_disabled) {
- qemu_mod_timer(s->irq_timer, s->next_transition_time);
+ timer_mod(s->irq_timer, s->next_transition_time);
}
}
@@ -294,10 +294,10 @@ static void pit_irq_control(void *opaque, int n, int enable)
if (enable) {
s->irq_disabled = 0;
- pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock));
+ pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
} else {
s->irq_disabled = 1;
- qemu_del_timer(s->irq_timer);
+ timer_del(s->irq_timer);
}
}
@@ -316,9 +316,9 @@ static void pit_post_load(PITCommonState *s)
PITChannelState *sc = &s->channels[0];
if (sc->next_transition_time != -1) {
- qemu_mod_timer(sc->irq_timer, sc->next_transition_time);
+ timer_mod(sc->irq_timer, sc->next_transition_time);
} else {
- qemu_del_timer(sc->irq_timer);
+ timer_del(sc->irq_timer);
}
}
@@ -330,7 +330,7 @@ static void pit_realizefn(DeviceState *dev, Error **err)
s = &pit->channels[0];
/* the timer 0 is connected to an IRQ */
- s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
+ s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s);
qdev_init_gpio_out(dev, &s->irq, 1);
memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops,
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index 4e5bf0b63c..e8fb971488 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -136,7 +136,7 @@ void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
info->gate = sc->gate;
info->mode = sc->mode;
info->initial_count = sc->count;
- info->out = pit_get_out(sc, qemu_get_clock_ns(vm_clock));
+ info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
@@ -157,7 +157,7 @@ void pit_reset_common(PITCommonState *pit)
s = &pit->channels[i];
s->mode = 3;
s->gate = (i != 2);
- s->count_load_time = qemu_get_clock_ns(vm_clock);
+ s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->count = 0x10000;
if (i == 0 && !s->irq_disabled) {
s->next_transition_time =
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index dc73d6525d..0dbe15c99b 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -18,6 +18,7 @@
#include "hw/ptimer.h"
#include "hw/sysbus.h"
#include "hw/arm/imx.h"
+#include "qemu/main-loop.h"
#define TYPE_IMX_EPIT "imx.epit"
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 87db0e195c..f2d1975e70 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -18,6 +18,7 @@
#include "hw/ptimer.h"
#include "hw/sysbus.h"
#include "hw/arm/imx.h"
+#include "qemu/main-loop.h"
#define TYPE_IMX_GPT "imx.gpt"
diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c
index 986e6a19d2..8ed138cc0e 100644
--- a/hw/timer/lm32_timer.c
+++ b/hw/timer/lm32_timer.c
@@ -27,6 +27,7 @@
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
#define DEFAULT_FREQUENCY (50*1000000)
diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
index 0cc9e5b5ee..d3d78ec5a8 100644
--- a/hw/timer/m48t59.c
+++ b/hw/timer/m48t59.c
@@ -137,7 +137,7 @@ static void alarm_cb (void *opaque)
/* Repeat once a second */
next_time = 1;
}
- qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) +
+ timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
next_time * 1000);
qemu_set_irq(NVRAM->IRQ, 0);
}
@@ -146,10 +146,10 @@ static void set_alarm(M48t59State *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
- qemu_del_timer(NVRAM->alrm_timer);
+ timer_del(NVRAM->alrm_timer);
diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
if (diff > 0)
- qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
+ timer_mod(NVRAM->alrm_timer, diff * 1000);
}
}
@@ -188,10 +188,10 @@ static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
NVRAM->buffer[0x1FF0] &= ~0x80;
if (NVRAM->wd_timer != NULL) {
- qemu_del_timer(NVRAM->wd_timer);
+ timer_del(NVRAM->wd_timer);
if (value != 0) {
interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
- qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
+ timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
((interval * 1000) >> 4));
}
}
@@ -609,10 +609,10 @@ static void m48t59_reset_common(M48t59State *NVRAM)
NVRAM->addr = 0;
NVRAM->lock = 0;
if (NVRAM->alrm_timer != NULL)
- qemu_del_timer(NVRAM->alrm_timer);
+ timer_del(NVRAM->alrm_timer);
if (NVRAM->wd_timer != NULL)
- qemu_del_timer(NVRAM->wd_timer);
+ timer_del(NVRAM->wd_timer);
}
static void m48t59_reset_isa(DeviceState *d)
@@ -700,8 +700,8 @@ static void m48t59_realize_common(M48t59State *s, Error **errp)
{
s->buffer = g_malloc0(s->size);
if (s->model == 59) {
- s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);
- s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
+ s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
+ s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
}
qemu_get_timedate(&s->alarm, 0);
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 3c3baaccfa..7230a6e4fa 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -102,7 +102,7 @@ static inline bool rtc_running(RTCState *s)
static uint64_t get_guest_rtc_ns(RTCState *s)
{
uint64_t guest_rtc;
- uint64_t guest_clock = qemu_get_clock_ns(rtc_clock);
+ uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
guest_rtc = s->base_rtc * NSEC_PER_SEC
+ guest_clock - s->last_update + s->offset;
@@ -113,13 +113,13 @@ static uint64_t get_guest_rtc_ns(RTCState *s)
static void rtc_coalesced_timer_update(RTCState *s)
{
if (s->irq_coalesced == 0) {
- qemu_del_timer(s->coalesced_timer);
+ timer_del(s->coalesced_timer);
} else {
/* divide each RTC interval to 2 - 8 smaller intervals */
int c = MIN(s->irq_coalesced, 7) + 1;
- int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
+ int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
- qemu_mod_timer(s->coalesced_timer, next_clock);
+ timer_mod(s->coalesced_timer, next_clock);
}
}
@@ -169,12 +169,12 @@ static void periodic_timer_update(RTCState *s, int64_t current_time)
next_irq_clock = (cur_clock & ~(period - 1)) + period;
s->next_periodic_time =
muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
- qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
+ timer_mod(s->periodic_timer, s->next_periodic_time);
} else {
#ifdef TARGET_I386
s->irq_coalesced = 0;
#endif
- qemu_del_timer(s->periodic_timer);
+ timer_del(s->periodic_timer);
}
}
@@ -222,23 +222,23 @@ static void check_update_timer(RTCState *s)
* from occurring, because the time of day is not updated.
*/
if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
- qemu_del_timer(s->update_timer);
+ timer_del(s->update_timer);
return;
}
if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
- qemu_del_timer(s->update_timer);
+ timer_del(s->update_timer);
return;
}
if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
(s->cmos_data[RTC_REG_C] & REG_C_AF)) {
- qemu_del_timer(s->update_timer);
+ timer_del(s->update_timer);
return;
}
guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
/* if UF is clear, reprogram to next second */
- next_update_time = qemu_get_clock_ns(rtc_clock)
+ next_update_time = qemu_clock_get_ns(rtc_clock)
+ NSEC_PER_SEC - guest_nsec;
/* Compute time of next alarm. One second is already accounted
@@ -252,8 +252,8 @@ static void check_update_timer(RTCState *s)
* the alarm time. */
next_update_time = s->next_alarm_time;
}
- if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
- qemu_mod_timer(s->update_timer, next_update_time);
+ if (next_update_time != timer_expire_time_ns(s->update_timer)) {
+ timer_mod(s->update_timer, next_update_time);
}
}
@@ -371,7 +371,7 @@ static void rtc_update_timer(void *opaque)
rtc_update_time(s);
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
- if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
+ if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
irqs |= REG_C_AF;
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
@@ -445,7 +445,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr,
/* UIP bit is read only */
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
(s->cmos_data[RTC_REG_A] & REG_A_UIP);
- periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
+ periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
check_update_timer(s);
break;
case RTC_REG_B:
@@ -475,7 +475,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr,
qemu_irq_lower(s->irq);
}
s->cmos_data[RTC_REG_B] = data;
- periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
+ periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
check_update_timer(s);
break;
case RTC_REG_C:
@@ -535,7 +535,7 @@ static void rtc_set_time(RTCState *s)
rtc_get_time(s, &tm);
s->base_rtc = mktimegm(&tm);
- s->last_update = qemu_get_clock_ns(rtc_clock);
+ s->last_update = qemu_clock_get_ns(rtc_clock);
rtc_change_mon_event(&tm);
}
@@ -587,10 +587,11 @@ static int update_in_progress(RTCState *s)
if (!rtc_running(s)) {
return 0;
}
- if (qemu_timer_pending(s->update_timer)) {
- int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer);
+ if (timer_pending(s->update_timer)) {
+ int64_t next_update_time = timer_expire_time_ns(s->update_timer);
/* Latch UIP until the timer expires. */
- if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
+ if (qemu_clock_get_ns(rtc_clock) >=
+ (next_update_time - UIP_HOLD_LENGTH)) {
s->cmos_data[RTC_REG_A] |= REG_A_UIP;
return 1;
}
@@ -695,7 +696,7 @@ static void rtc_set_date_from_host(ISADevice *dev)
qemu_get_timedate(&tm, 0);
s->base_rtc = mktimegm(&tm);
- s->last_update = qemu_get_clock_ns(rtc_clock);
+ s->last_update = qemu_clock_get_ns(rtc_clock);
s->offset = 0;
/* set the CMOS date */
@@ -843,7 +844,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
switch (s->lost_tick_policy) {
case LOST_TICK_SLEW:
s->coalesced_timer =
- qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
+ timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
break;
case LOST_TICK_DISCARD:
break;
@@ -853,12 +854,13 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
}
#endif
- s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
- s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s);
+ s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
+ s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
check_update_timer(s);
s->clock_reset_notifier.notify = rtc_notify_clock_reset;
- qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
+ qemu_clock_register_reset_notifier(QEMU_CLOCK_REALTIME,
+ &s->clock_reset_notifier);
s->suspend_notifier.notify = rtc_notify_suspend;
qemu_register_suspend_notifier(&s->suspend_notifier);
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
index ac389d87ee..016207f626 100644
--- a/hw/timer/omap_gptimer.c
+++ b/hw/timer/omap_gptimer.c
@@ -103,7 +103,7 @@ static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
uint64_t distance;
if (timer->st && timer->rate) {
- distance = qemu_get_clock_ns(vm_clock) - timer->time;
+ distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
if (distance >= 0xffffffff - timer->val)
@@ -118,7 +118,7 @@ static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
{
if (timer->st) {
timer->val = omap_gp_timer_read(timer);
- timer->time = qemu_get_clock_ns(vm_clock);
+ timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
}
@@ -129,17 +129,17 @@ static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
if (timer->st && timer->rate) {
expires = muldiv64(0x100000000ll - timer->val,
timer->ticks_per_sec, timer->rate);
- qemu_mod_timer(timer->timer, timer->time + expires);
+ timer_mod(timer->timer, timer->time + expires);
if (timer->ce && timer->match_val >= timer->val) {
matches = muldiv64(timer->match_val - timer->val,
timer->ticks_per_sec, timer->rate);
- qemu_mod_timer(timer->match, timer->time + matches);
+ timer_mod(timer->match, timer->time + matches);
} else
- qemu_del_timer(timer->match);
+ timer_del(timer->match);
} else {
- qemu_del_timer(timer->timer);
- qemu_del_timer(timer->match);
+ timer_del(timer->timer);
+ timer_del(timer->match);
omap_gp_timer_out(timer, timer->scpwm);
}
}
@@ -164,7 +164,7 @@ static void omap_gp_timer_tick(void *opaque)
timer->val = 0;
} else {
timer->val = timer->load_val;
- timer->time = qemu_get_clock_ns(vm_clock);
+ timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
if (timer->trigger == gpt_trigger_overflow ||
@@ -406,7 +406,7 @@ static void omap_gp_timer_write(void *opaque, hwaddr addr,
break;
case 0x28: /* TCRR */
- s->time = qemu_get_clock_ns(vm_clock);
+ s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->val = value;
omap_gp_timer_update(s);
break;
@@ -416,7 +416,7 @@ static void omap_gp_timer_write(void *opaque, hwaddr addr,
break;
case 0x30: /* TTGR */
- s->time = qemu_get_clock_ns(vm_clock);
+ s->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->val = s->load_val;
omap_gp_timer_update(s);
break;
@@ -474,8 +474,8 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
s->ta = ta;
s->irq = irq;
s->clk = fclk;
- s->timer = qemu_new_timer_ns(vm_clock, omap_gp_timer_tick, s);
- s->match = qemu_new_timer_ns(vm_clock, omap_gp_timer_match, s);
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_tick, s);
+ s->match = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_gp_timer_match, s);
s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
omap_gp_timer_reset(s);
omap_gp_timer_clk_setup(s);
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
index a12aca20df..8e50488d17 100644
--- a/hw/timer/omap_synctimer.c
+++ b/hw/timer/omap_synctimer.c
@@ -28,7 +28,7 @@ struct omap_synctimer_s {
/* 32-kHz Sync Timer of the OMAP2 */
static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
- return muldiv64(qemu_get_clock_ns(vm_clock), 0x8000, get_ticks_per_sec());
+ return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 0x8000, get_ticks_per_sec());
}
void omap_synctimer_reset(struct omap_synctimer_s *s)
diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
index d5e2f3e265..65928a4819 100644
--- a/hw/timer/pl031.c
+++ b/hw/timer/pl031.c
@@ -78,7 +78,7 @@ static void pl031_interrupt(void * opaque)
static uint32_t pl031_get_count(PL031State *s)
{
- int64_t now = qemu_get_clock_ns(rtc_clock);
+ int64_t now = qemu_clock_get_ns(rtc_clock);
return s->tick_offset + now / get_ticks_per_sec();
}
@@ -91,11 +91,11 @@ static void pl031_set_alarm(PL031State *s)
ticks = s->mr - pl031_get_count(s);
DPRINTF("Alarm set in %ud ticks\n", ticks);
if (ticks == 0) {
- qemu_del_timer(s->timer);
+ timer_del(s->timer);
pl031_interrupt(s);
} else {
- int64_t now = qemu_get_clock_ns(rtc_clock);
- qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
+ int64_t now = qemu_clock_get_ns(rtc_clock);
+ timer_mod(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
}
}
@@ -201,9 +201,10 @@ static int pl031_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
qemu_get_timedate(&tm, 0);
- s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
+ s->tick_offset = mktimegm(&tm) -
+ qemu_clock_get_ns(rtc_clock) / get_ticks_per_sec();
- s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
+ s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
return 0;
}
@@ -212,8 +213,8 @@ static void pl031_pre_save(void *opaque)
PL031State *s = opaque;
/* tick_offset is base_time - rtc_clock base time. Instead, we want to
- * store the base time relative to the vm_clock for backwards-compatibility. */
- int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
+ * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */
+ int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
}
@@ -221,7 +222,7 @@ static int pl031_post_load(void *opaque, int version_id)
{
PL031State *s = opaque;
- int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
+ int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
pl031_set_alarm(s);
return 0;
diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c
index 4bd2b76cb8..fa9eefd925 100644
--- a/hw/timer/puv3_ost.c
+++ b/hw/timer/puv3_ost.c
@@ -10,6 +10,7 @@
*/
#include "hw/sysbus.h"
#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c
index cdabccdd15..0f546c4121 100644
--- a/hw/timer/pxa2xx_timer.c
+++ b/hw/timer/pxa2xx_timer.c
@@ -123,7 +123,7 @@ static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
for (i = 0; i < 4; i ++) {
new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
get_ticks_per_sec(), s->freq);
- qemu_mod_timer(s->timer[i].qtimer, new_qemu);
+ timer_mod(s->timer[i].qtimer, new_qemu);
}
}
@@ -141,7 +141,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
counter = counters[n];
if (!s->tm4[counter].freq) {
- qemu_del_timer(s->tm4[n].tm.qtimer);
+ timer_del(s->tm4[n].tm.qtimer);
return;
}
@@ -151,7 +151,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
get_ticks_per_sec(), s->tm4[counter].freq);
- qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
+ timer_mod(s->tm4[n].tm.qtimer, new_qemu);
}
static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
@@ -188,7 +188,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
goto badreg;
return s->tm4[tm].tm.value;
case OSCR:
- return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
+ return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
s->lastload, s->freq, get_ticks_per_sec());
case OSCR11: tm ++;
/* fall through */
@@ -211,7 +211,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
if (s->tm4[tm - 1].freq)
s->snapshot = s->tm4[tm - 1].clock + muldiv64(
- qemu_get_clock_ns(vm_clock) -
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
s->tm4[tm - 1].lastload,
s->tm4[tm - 1].freq, get_ticks_per_sec());
else
@@ -220,7 +220,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
if (!s->tm4[tm].freq)
return s->tm4[tm].clock;
- return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
+ return s->tm4[tm].clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
case OIER:
return s->irq_enabled;
@@ -271,7 +271,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
/* fall through */
case OSMR0:
s->timer[tm].value = value;
- pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
+ pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
case OSMR11: tm ++;
/* fall through */
@@ -291,11 +291,11 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].tm.value = value;
- pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
+ pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
break;
case OSCR:
s->oldclock = s->clock;
- s->lastload = qemu_get_clock_ns(vm_clock);
+ s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->clock = value;
pxa2xx_timer_update(s, s->lastload);
break;
@@ -317,7 +317,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
if (!pxa2xx_timer_has_tm4(s))
goto badreg;
s->tm4[tm].oldclock = s->tm4[tm].clock;
- s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
+ s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->tm4[tm].clock = value;
pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
break;
@@ -351,7 +351,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
else {
s->tm4[tm].freq = 0;
- pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
+ pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
}
break;
case OMCR11: tm ++;
@@ -370,7 +370,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset,
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
else {
s->tm4[tm].freq = 0;
- pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
+ pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
}
break;
default:
@@ -411,7 +411,7 @@ static void pxa2xx_timer_tick4(void *opaque)
if (t->control & (1 << 3))
t->clock = 0;
if (t->control & (1 << 6))
- pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
+ pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
if (i->events & 0xff0)
qemu_irq_raise(i->irq4);
}
@@ -422,7 +422,7 @@ static int pxa25x_timer_post_load(void *opaque, int version_id)
int64_t now;
int i;
- now = qemu_get_clock_ns(vm_clock);
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
pxa2xx_timer_update(s, now);
if (pxa2xx_timer_has_tm4(s))
@@ -440,7 +440,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev)
s->irq_enabled = 0;
s->oldclock = 0;
s->clock = 0;
- s->lastload = qemu_get_clock_ns(vm_clock);
+ s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->reset3 = 0;
for (i = 0; i < 4; i ++) {
@@ -448,7 +448,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[i].irq);
s->timer[i].info = s;
s->timer[i].num = i;
- s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
+ s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
pxa2xx_timer_tick, &s->timer[i]);
}
if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
@@ -460,7 +460,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev)
s->tm4[i].tm.num = i + 4;
s->tm4[i].freq = 0;
s->tm4[i].control = 0x0;
- s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
+ s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
pxa2xx_timer_tick4, &s->tm4[i]);
}
}
diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
index 251a10dbfa..07f0670b5d 100644
--- a/hw/timer/sh_timer.c
+++ b/hw/timer/sh_timer.c
@@ -11,6 +11,7 @@
#include "hw/hw.h"
#include "hw/sh4/sh.h"
#include "qemu/timer.h"
+#include "qemu/main-loop.h"
#include "exec/address-spaces.h"
#include "hw/ptimer.h"
diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c
index 33e8f6c15c..f75b914951 100644
--- a/hw/timer/slavio_timer.c
+++ b/hw/timer/slavio_timer.c
@@ -27,6 +27,7 @@
#include "hw/ptimer.h"
#include "hw/sysbus.h"
#include "trace.h"
+#include "qemu/main-loop.h"
/*
* Registers of hardware timer in sun4m.
diff --git a/hw/timer/tusb6010.c b/hw/timer/tusb6010.c
index c48ecf8ee7..bd2a89e020 100644
--- a/hw/timer/tusb6010.c
+++ b/hw/timer/tusb6010.c
@@ -516,11 +516,11 @@ static void tusb_async_writew(void *opaque, hwaddr addr,
case TUSB_DEV_OTG_TIMER:
s->otg_timer_val = value;
if (value & TUSB_DEV_OTG_TIMER_ENABLE)
- qemu_mod_timer(s->otg_timer, qemu_get_clock_ns(vm_clock) +
+ timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
get_ticks_per_sec(), TUSB_DEVCLOCK));
else
- qemu_del_timer(s->otg_timer);
+ timer_del(s->otg_timer);
break;
case TUSB_PRCM_CONF:
@@ -728,8 +728,8 @@ static void tusb6010_power(TUSBState *s, int on)
/* Pull the interrupt down after TUSB6010 comes up. */
s->intr_ok = 0;
tusb_intr_update(s);
- qemu_mod_timer(s->pwr_timer,
- qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 2);
+ timer_mod(s->pwr_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 2);
}
}
@@ -783,8 +783,8 @@ static int tusb6010_init(SysBusDevice *sbd)
DeviceState *dev = DEVICE(sbd);
TUSBState *s = TUSB(dev);
- s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
- s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
+ s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
+ s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
"tusb-async", UINT32_MAX);
sysbus_init_mmio(sbd, &s->iomem[0]);
diff --git a/hw/timer/twl92230.c b/hw/timer/twl92230.c
index b730d853f7..f3ea36503c 100644
--- a/hw/timer/twl92230.c
+++ b/hw/timer/twl92230.c
@@ -72,14 +72,14 @@ static inline void menelaus_update(MenelausState *s)
static inline void menelaus_rtc_start(MenelausState *s)
{
- s->rtc.next += qemu_get_clock_ms(rtc_clock);
- qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
+ s->rtc.next += qemu_clock_get_ms(rtc_clock);
+ timer_mod(s->rtc.hz_tm, s->rtc.next);
}
static inline void menelaus_rtc_stop(MenelausState *s)
{
- qemu_del_timer(s->rtc.hz_tm);
- s->rtc.next -= qemu_get_clock_ms(rtc_clock);
+ timer_del(s->rtc.hz_tm);
+ s->rtc.next -= qemu_clock_get_ms(rtc_clock);
if (s->rtc.next < 1)
s->rtc.next = 1;
}
@@ -102,7 +102,7 @@ static void menelaus_rtc_hz(void *opaque)
s->rtc.next_comp --;
s->rtc.alm_sec --;
s->rtc.next += 1000;
- qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
+ timer_mod(s->rtc.hz_tm, s->rtc.next);
if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
menelaus_rtc_update(s);
if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
@@ -782,7 +782,7 @@ static void menelaus_pre_save(void *opaque)
{
MenelausState *s = opaque;
/* Should be <= 1000 */
- s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rtc_clock);
+ s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock);
}
static int menelaus_post_load(void *opaque, int version_id)
@@ -843,7 +843,7 @@ static int twl92230_init(I2CSlave *i2c)
{
MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c);
- s->rtc.hz_tm = qemu_new_timer_ms(rtc_clock, menelaus_rtc_hz, s);
+ s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s);
/* Three output pins plus one interrupt pin. */
qdev_init_gpio_out(&i2c->qdev, s->out, 4);
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 5f2c9020ea..6113b975bf 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -25,6 +25,7 @@
#include "hw/sysbus.h"
#include "hw/ptimer.h"
#include "qemu/log.h"
+#include "qemu/main-loop.h"
#define D(x)
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-23 04:52:28 +0000