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-rw-r--r--hw/sh4/r2d.c39
-rw-r--r--hw/sh4/sh7750.c26
-rw-r--r--hw/sh4/sh7750_regnames.c5
-rw-r--r--hw/sh4/sh7750_regs.h18
-rw-r--r--hw/sh4/shix.c2
5 files changed, 46 insertions, 44 deletions
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 46f1fae48c..216d6e24a1 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -96,19 +96,19 @@ enum r2d_fpga_irq {
};
static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
- [CF_IDE] = { 1, 1<<9 },
- [CF_CD] = { 2, 1<<8 },
- [PCI_INTA] = { 9, 1<<14 },
- [PCI_INTB] = { 10, 1<<13 },
- [PCI_INTC] = { 3, 1<<12 },
- [PCI_INTD] = { 0, 1<<11 },
- [SM501] = { 4, 1<<10 },
- [KEY] = { 5, 1<<6 },
- [RTC_A] = { 6, 1<<5 },
- [RTC_T] = { 7, 1<<4 },
- [SDCARD] = { 8, 1<<7 },
- [EXT] = { 11, 1<<0 },
- [TP] = { 12, 1<<15 },
+ [CF_IDE] = { 1, 1 << 9 },
+ [CF_CD] = { 2, 1 << 8 },
+ [PCI_INTA] = { 9, 1 << 14 },
+ [PCI_INTB] = { 10, 1 << 13 },
+ [PCI_INTC] = { 3, 1 << 12 },
+ [PCI_INTD] = { 0, 1 << 11 },
+ [SM501] = { 4, 1 << 10 },
+ [KEY] = { 5, 1 << 6 },
+ [RTC_A] = { 6, 1 << 5 },
+ [RTC_T] = { 7, 1 << 4 },
+ [SDCARD] = { 8, 1 << 7 },
+ [EXT] = { 11, 1 << 0 },
+ [TP] = { 12, 1 << 15 },
};
static void update_irl(r2d_fpga_t *fpga)
@@ -306,7 +306,7 @@ static void r2d_init(MachineState *machine)
/* NIC: rtl8139 on-board, and 2 slots. */
for (i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], pci_bus,
- "rtl8139", i==0 ? "2" : NULL);
+ "rtl8139", i == 0 ? "2" : NULL);
/* USB keyboard */
usb_create_simple(usb_bus_find(-1), "usb-kbd");
@@ -321,8 +321,8 @@ static void r2d_init(MachineState *machine)
SDRAM_BASE + LINUX_LOAD_OFFSET,
INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
- exit(1);
+ fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
+ exit(1);
}
/* initialization which should be done by firmware */
@@ -330,7 +330,8 @@ static void r2d_init(MachineState *machine)
MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
- reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
+ /* Start from P2 area */
+ reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
}
if (initrd_filename) {
@@ -341,8 +342,8 @@ static void r2d_init(MachineState *machine)
SDRAM_SIZE - INITRD_LOAD_OFFSET);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
- exit(1);
+ fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
+ exit(1);
}
/* initialization which should be done by firmware */
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 2539924b00..1e61f9f1c8 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -78,7 +78,7 @@ typedef struct SH7750State {
struct intc_desc intc;
} SH7750State;
-static inline int has_bcr3_and_bcr4(SH7750State * s)
+static inline int has_bcr3_and_bcr4(SH7750State *s)
{
return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
}
@@ -87,7 +87,7 @@ static inline int has_bcr3_and_bcr4(SH7750State * s)
* I/O ports
*/
-int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
+int sh7750_register_io_device(SH7750State *s, sh7750_io_device *device)
{
int i;
@@ -102,7 +102,7 @@ int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
static uint16_t portdir(uint32_t v)
{
-#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
+#define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n))
return
EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
@@ -114,7 +114,7 @@ static uint16_t portdir(uint32_t v)
static uint16_t portpullup(uint32_t v)
{
-#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
+#define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n))
return
ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
@@ -123,26 +123,26 @@ static uint16_t portpullup(uint32_t v)
ODDPORTMASK(1) | ODDPORTMASK(0);
}
-static uint16_t porta_lines(SH7750State * s)
+static uint16_t porta_lines(SH7750State *s)
{
return (s->portdira & s->pdtra) | /* CPU */
(s->periph_portdira & s->periph_pdtra) | /* Peripherals */
(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
}
-static uint16_t portb_lines(SH7750State * s)
+static uint16_t portb_lines(SH7750State *s)
{
return (s->portdirb & s->pdtrb) | /* CPU */
(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
}
-static void gen_port_interrupts(SH7750State * s)
+static void gen_port_interrupts(SH7750State *s)
{
/* XXXXX interrupts not generated */
}
-static void porta_changed(SH7750State * s, uint16_t prev)
+static void porta_changed(SH7750State *s, uint16_t prev)
{
uint16_t currenta, changes;
int i, r = 0;
@@ -171,7 +171,7 @@ static void porta_changed(SH7750State * s, uint16_t prev)
gen_port_interrupts(s);
}
-static void portb_changed(SH7750State * s, uint16_t prev)
+static void portb_changed(SH7750State *s, uint16_t prev)
{
uint16_t currentb, changes;
int i, r = 0;
@@ -228,7 +228,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
case SH7750_BCR2_A7:
return s->bcr2;
case SH7750_BCR3_A7:
- if(!has_bcr3_and_bcr4(s))
+ if (!has_bcr3_and_bcr4(s))
error_access("word read", addr);
return s->bcr3;
case SH7750_FRQCR_A7:
@@ -263,7 +263,7 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
case SH7750_BCR1_A7:
return s->bcr1;
case SH7750_BCR4_A7:
- if(!has_bcr3_and_bcr4(s))
+ if (!has_bcr3_and_bcr4(s))
error_access("long read", addr);
return s->bcr4;
case SH7750_WCR1_A7:
@@ -332,7 +332,7 @@ static void sh7750_mem_writew(void *opaque, hwaddr addr,
s->bcr2 = mem_value;
return;
case SH7750_BCR3_A7:
- if(!has_bcr3_and_bcr4(s))
+ if (!has_bcr3_and_bcr4(s))
error_access("word write", addr);
s->bcr3 = mem_value;
return;
@@ -384,7 +384,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
s->bcr1 = mem_value;
return;
case SH7750_BCR4_A7:
- if(!has_bcr3_and_bcr4(s))
+ if (!has_bcr3_and_bcr4(s))
error_access("long write", addr);
s->bcr4 = mem_value;
return;
diff --git a/hw/sh4/sh7750_regnames.c b/hw/sh4/sh7750_regnames.c
index b1f112df3e..37b3acd620 100644
--- a/hw/sh4/sh7750_regnames.c
+++ b/hw/sh4/sh7750_regnames.c
@@ -81,14 +81,15 @@ static regname_t regnames[] = {
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
REGNAME(SH7750_SDMR2_A7)
- REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL}
+ REGNAME(SH7750_SDMR3_A7)
+ { (uint32_t)-1, NULL }
};
const char *regname(uint32_t addr)
{
unsigned int i;
- for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) {
+ for (i = 0; regnames[i].regaddr != (uint32_t)-1; i++) {
if (regnames[i].regaddr == addr)
return regnames[i].regname;
}
diff --git a/hw/sh4/sh7750_regs.h b/hw/sh4/sh7750_regs.h
index bd12b0532d..beb571d5e9 100644
--- a/hw/sh4/sh7750_regs.h
+++ b/hw/sh4/sh7750_regs.h
@@ -1015,7 +1015,7 @@
*/
/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
-#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */
+#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n) * 16)) /* offset */
#define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
#define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
#define SH7750_SAR0 SH7750_SAR(0)
@@ -1028,7 +1028,7 @@
#define SH7750_SAR3_A7 SH7750_SAR_A7(3)
/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
-#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */
+#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n) * 16)) /* offset */
#define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
#define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
#define SH7750_DAR0 SH7750_DAR(0)
@@ -1041,7 +1041,7 @@
#define SH7750_DAR3_A7 SH7750_DAR_A7(3)
/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
-#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */
+#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n) * 16)) /* offset */
#define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
#define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
#define SH7750_DMATCR0_P4 SH7750_DMATCR(0)
@@ -1054,7 +1054,7 @@
#define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3)
/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
-#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */
+#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n) * 16)) /* offset */
#define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
#define SH7750_CHCR0 SH7750_CHCR(0)
@@ -1208,9 +1208,9 @@
#define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
#define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */
-#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */
+#define SH7750_PCTRA_PBNPUP(n) (1 << ((n) * 2 + 1)) /* Bit n is not pulled up */
#define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */
-#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */
+#define SH7750_PCTRA_PBOUT(n) (1 << ((n) * 2)) /* Bit n is an output */
/* Port Data Register A - PDTRA(half) */
#define SH7750_PDTRA_REGOFS 0x800030 /* offset */
@@ -1225,16 +1225,16 @@
#define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
#define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */
-#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */
+#define SH7750_PCTRB_PBNPUP(n) (1 << ((n - 16) * 2 + 1)) /* Bit n is not pulled up */
#define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */
-#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */
+#define SH7750_PCTRB_PBOUT(n) (1 << ((n - 16) * 2)) /* Bit n is an output */
/* Port Data Register B - PDTRB(half) */
#define SH7750_PDTRB_REGOFS 0x800044 /* offset */
#define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
#define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
-#define SH7750_PDTRB_BIT(n) (1 << ((n)-16))
+#define SH7750_PDTRB_BIT(n) (1 << ((n) - 16))
/* GPIO Interrupt Control Register - GPIOIC(half) */
#define SH7750_GPIOIC_REGOFS 0x800048 /* offset */
diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c
index 6b39de417f..aa812512f0 100644
--- a/hw/sh4/shix.c
+++ b/hw/sh4/shix.c
@@ -48,7 +48,7 @@ static void shix_init(MachineState *machine)
MemoryRegion *rom = g_new(MemoryRegion, 1);
MemoryRegion *sdram = g_new(MemoryRegion, 2);
const char *bios_name = machine->firmware ?: BIOS_FILENAME;
-
+
cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
/* Allocate memory space */
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-24 15:26:54 +0000