diff options
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/opentitan.c | 3 | ||||
| -rw-r--r-- | hw/riscv/riscv_hart.c | 3 | ||||
| -rw-r--r-- | hw/riscv/sifive_e.c | 3 | ||||
| -rw-r--r-- | hw/riscv/sifive_u.c | 9 |
4 files changed, 6 insertions, 12 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index bebd3213e1..f6776da8e9 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -61,8 +61,7 @@ static void riscv_opentitan_init(MachineState *machine) /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_IBEX_SOC); - object_property_set_bool(OBJECT(&s->soc), true, "realized", - &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_abort); memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", memmap[IBEX_RAM].size, &error_fatal); diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 56c2be5312..e26c382259 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -48,8 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx, object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); s->harts[idx].env.mhartid = s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); - object_property_set_bool(OBJECT(&s->harts[idx]), true, - "realized", &err); + qdev_realize(DEVICE(&s->harts[idx]), NULL, &err); if (err) { error_propagate(errp, err); return; diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index a9e4482270..1c17d02cf0 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -86,8 +86,7 @@ static void riscv_sifive_e_init(MachineState *machine) /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); - object_property_set_bool(OBJECT(&s->soc), true, "realized", - &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_abort); /* Data Tightly Integrated Memory */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5b86520b24..ea197ab64f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -331,8 +331,7 @@ static void sifive_u_machine_init(MachineState *machine) object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", &error_abort); - object_property_set_bool(OBJECT(&s->soc), true, "realized", - &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_abort); /* register RAM */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", @@ -530,10 +529,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) * CPU must exist and have been parented into the cluster before the * cluster is realized. */ - object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", - &error_abort); - object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", - &error_abort); + qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); + qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); /* boot rom */ memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |