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-rw-r--r--hw/riscv/opentitan.c13
-rw-r--r--hw/riscv/riscv_hart.c7
-rw-r--r--hw/riscv/sifive_clint.c5
-rw-r--r--hw/riscv/sifive_e.c21
-rw-r--r--hw/riscv/sifive_e_prci.c5
-rw-r--r--hw/riscv/sifive_plic.c5
-rw-r--r--hw/riscv/sifive_test.c5
-rw-r--r--hw/riscv/sifive_u.c54
-rw-r--r--hw/riscv/spike.c7
-rw-r--r--hw/riscv/virt.c15
10 files changed, 53 insertions, 84 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index b4fb836466..f6776da8e9 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -60,10 +60,8 @@ static void riscv_opentitan_init(MachineState *machine)
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
- sizeof(s->soc), TYPE_RISCV_IBEX_SOC,
- &error_abort, NULL);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ TYPE_RISCV_IBEX_SOC);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
memmap[IBEX_RAM].size, &error_fatal);
@@ -94,9 +92,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
- object_initialize_child(obj, "cpus", &s->cpus,
- sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
- &error_abort, NULL);
+ object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
}
static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -110,8 +106,7 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
- object_property_set_bool(OBJECT(&s->cpus), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 276a9baca0..e26c382259 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -45,13 +45,10 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
{
Error *err = NULL;
- object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
- sizeof(RISCVCPU), cpu_type,
- &error_abort, NULL);
+ object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
- object_property_set_bool(OBJECT(&s->harts[idx]), true,
- "realized", &err);
+ qdev_realize(DEVICE(&s->harts[idx]), NULL, &err);
if (err) {
error_propagate(errp, err);
return;
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index e933d35092..b11ffa0edc 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -20,6 +20,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
@@ -245,13 +246,13 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
env->timecmp = 0;
}
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_CLINT);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
qdev_prop_set_uint32(dev, "num-harts", num_harts);
qdev_prop_set_uint32(dev, "sip-base", sip_base);
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
qdev_prop_set_uint32(dev, "time-base", time_base);
qdev_prop_set_uint32(dev, "aperture-size", size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 472a98970b..1c17d02cf0 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -85,11 +85,8 @@ static void riscv_sifive_e_init(MachineState *machine)
int i;
/* Initialize SoC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc,
- sizeof(s->soc), TYPE_RISCV_E_SOC,
- &error_abort, NULL);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* Data Tightly Integrated Memory */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
@@ -149,14 +146,11 @@ static void riscv_sifive_e_soc_init(Object *obj)
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj);
- object_initialize_child(obj, "cpus", &s->cpus,
- sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
- &error_abort, NULL);
+ object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
- sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
- &s->gpio, sizeof(s->gpio),
- TYPE_SIFIVE_GPIO);
+ object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
+ TYPE_SIFIVE_GPIO);
}
static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
@@ -170,8 +164,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
- object_property_set_bool(OBJECT(&s->cpus), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
@@ -200,7 +193,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
/* GPIO */
- object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
if (err) {
error_propagate(errp, err);
return;
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index a1c0d44f18..17dfa74715 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
@@ -117,8 +118,8 @@ type_init(sifive_e_prci_register_types)
*/
DeviceState *sifive_e_prci_create(hwaddr addr)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI);
- qdev_init_nofail(dev);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_E_PRCI);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index c1e04cbb98..4f216c5585 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -19,6 +19,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
@@ -494,7 +495,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
uint32_t context_base, uint32_t context_stride,
uint32_t aperture_size)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
assert(enable_stride == (enable_stride & -enable_stride));
assert(context_stride == (context_stride & -context_stride));
qdev_prop_set_string(dev, "hart-config", hart_config);
@@ -507,7 +508,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
qdev_prop_set_uint32(dev, "context-base", context_base);
qdev_prop_set_uint32(dev, "context-stride", context_stride);
qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index 339195c6ff..0c78fb2c93 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
@@ -92,8 +93,8 @@ type_init(sifive_test_register_types)
*/
DeviceState *sifive_test_create(hwaddr addr)
{
- DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST);
- qdev_init_nofail(dev);
+ DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f9fef2be91..ea197ab64f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -328,13 +328,10 @@ static void sifive_u_machine_init(MachineState *machine)
int i;
/* Initialize SoC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc,
- sizeof(s->soc), TYPE_RISCV_U_SOC,
- &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
&error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
@@ -486,38 +483,27 @@ static void sifive_u_soc_instance_init(Object *obj)
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(obj);
- object_initialize_child(obj, "e-cluster", &s->e_cluster,
- sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
- &error_abort, NULL);
+ object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
- object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
- &s->e_cpus, sizeof(s->e_cpus),
- TYPE_RISCV_HART_ARRAY, &error_abort,
- NULL);
+ object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
+ TYPE_RISCV_HART_ARRAY);
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
- object_initialize_child(obj, "u-cluster", &s->u_cluster,
- sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
- &error_abort, NULL);
+ object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
- object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
- &s->u_cpus, sizeof(s->u_cpus),
- TYPE_RISCV_HART_ARRAY, &error_abort,
- NULL);
+ object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
+ TYPE_RISCV_HART_ARRAY);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
- sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
- TYPE_SIFIVE_U_PRCI);
- sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
- TYPE_SIFIVE_U_OTP);
- sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
- TYPE_CADENCE_GEM);
+ object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
+ object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
+ object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
}
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -535,20 +521,16 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
NICInfo *nd = &nd_table[0];
- object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
- &error_abort);
- object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
* CPU must exist and have been parented into the cluster before the
* cluster is realized.
*/
- object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
- &error_abort);
- object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
- &error_abort);
+ qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
+ qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
@@ -605,11 +587,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
- object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->prci), &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
- object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->otp), &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
@@ -622,7 +604,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
&error_abort);
- object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem), &err);
if (err) {
error_propagate(errp, err);
return;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 7bbbdb5036..3c87e04fdc 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -169,14 +169,13 @@ static void spike_board_init(MachineState *machine)
unsigned int smp_cpus = machine->smp.cpus;
/* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_RISCV_HART_ARRAY);
object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
&error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
/* register system main memory (actual RAM) */
memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4e4c494a70..616db6f5ac 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -80,7 +80,7 @@ static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
* Create a single flash device. We use the same parameters as
* the flash devices on the ARM virt board.
*/
- DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+ DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
qdev_prop_set_uint8(dev, "width", 4);
@@ -114,7 +114,7 @@ static void virt_flash_map1(PFlashCFI01 *flash,
assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
@@ -443,9 +443,9 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
qemu_irq irq;
int i;
- dev = qdev_create(NULL, TYPE_GPEX_HOST);
+ dev = qdev_new(TYPE_GPEX_HOST);
- qdev_init_nofail(dev);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_alias = g_new0(MemoryRegion, 1);
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
@@ -485,14 +485,13 @@ static void virt_machine_init(MachineState *machine)
unsigned int smp_cpus = machine->smp.cpus;
/* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_RISCV_HART_ARRAY);
object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
&error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
/* register system main memory (actual RAM) */
memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-12 20:28:14 +0000