aboutsummaryrefslogtreecommitdiff
path: root/hw/riscv/sifive_test.c
diff options
context:
space:
mode:
Diffstat (limited to 'hw/riscv/sifive_test.c')
-rw-r--r--hw/riscv/sifive_test.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index afbb3aaf34..339195c6ff 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -19,10 +19,10 @@
*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/sysbus.h"
+#include "qemu/log.h"
#include "qemu/module.h"
-#include "target/riscv/cpu.h"
+#include "sysemu/runstate.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_test.h"
@@ -42,12 +42,15 @@ static void sifive_test_write(void *opaque, hwaddr addr,
exit(code);
case FINISHER_PASS:
exit(0);
+ case FINISHER_RESET:
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
default:
break;
}
}
- hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
- __func__, (int)addr, val64);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
+ __func__, (int)addr, val64);
}
static const MemoryRegionOps sifive_test_ops = {