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path: root/hw/rdma/vmw/pvrdma_main.c
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Diffstat (limited to 'hw/rdma/vmw/pvrdma_main.c')
-rw-r--r--hw/rdma/vmw/pvrdma_main.c182
1 files changed, 88 insertions, 94 deletions
diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
index d2bdb5ba8c..0b46561bad 100644
--- a/hw/rdma/vmw/pvrdma_main.c
+++ b/hw/rdma/vmw/pvrdma_main.c
@@ -25,6 +25,8 @@
#include "cpu.h"
#include "trace.h"
#include "sysemu/sysemu.h"
+#include "monitor/monitor.h"
+#include "hw/rdma/rdma.h"
#include "../rdma_rm.h"
#include "../rdma_backend.h"
@@ -55,6 +57,26 @@ static Property pvrdma_dev_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static void pvrdma_print_statistics(Monitor *mon, RdmaProvider *obj)
+{
+ PVRDMADev *dev = PVRDMA_DEV(obj);
+ PCIDevice *pdev = PCI_DEVICE(dev);
+
+ monitor_printf(mon, "%s, %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
+ PCI_FUNC(pdev->devfn));
+ monitor_printf(mon, "\tcommands : %" PRId64 "\n",
+ dev->stats.commands);
+ monitor_printf(mon, "\tregs_reads : %" PRId64 "\n",
+ dev->stats.regs_reads);
+ monitor_printf(mon, "\tregs_writes : %" PRId64 "\n",
+ dev->stats.regs_writes);
+ monitor_printf(mon, "\tuar_writes : %" PRId64 "\n",
+ dev->stats.uar_writes);
+ monitor_printf(mon, "\tinterrupts : %" PRId64 "\n",
+ dev->stats.interrupts);
+ rdma_dump_device_counters(mon, &dev->rdma_dev_res);
+}
+
static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
void *ring_state)
{
@@ -69,25 +91,22 @@ static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
uint64_t *dir, *tbl;
int rc = 0;
- pr_dbg("Initializing device ring %s\n", name);
- pr_dbg("pdir_dma=0x%llx\n", (long long unsigned int)dir_addr);
- pr_dbg("num_pages=%d\n", num_pages);
dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
if (!dir) {
- pr_err("Failed to map to page directory\n");
+ rdma_error_report("Failed to map to page directory (ring %s)", name);
rc = -ENOMEM;
goto out;
}
tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
if (!tbl) {
- pr_err("Failed to map to page table\n");
+ rdma_error_report("Failed to map to page table (ring %s)", name);
rc = -ENOMEM;
goto out_free_dir;
}
*ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
if (!*ring_state) {
- pr_err("Failed to map to ring state\n");
+ rdma_error_report("Failed to map to ring state (ring %s)", name);
rc = -ENOMEM;
goto out_free_tbl;
}
@@ -100,7 +119,6 @@ static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
sizeof(struct pvrdma_cqne),
(dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
if (rc) {
- pr_err("Failed to initialize ring\n");
rc = -ENOMEM;
goto out_free_ring_state;
}
@@ -155,11 +173,10 @@ static int load_dsr(PVRDMADev *dev)
free_dsr(dev);
/* Map to DSR */
- pr_dbg("dsr_dma=0x%llx\n", (long long unsigned int)dev->dsr_info.dma);
dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
sizeof(struct pvrdma_device_shared_region));
if (!dev->dsr_info.dsr) {
- pr_err("Failed to map to DSR\n");
+ rdma_error_report("Failed to map to DSR");
rc = -ENOMEM;
goto out;
}
@@ -169,21 +186,19 @@ static int load_dsr(PVRDMADev *dev)
dsr = dsr_info->dsr;
/* Map to command slot */
- pr_dbg("cmd_dma=0x%llx\n", (long long unsigned int)dsr->cmd_slot_dma);
dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
sizeof(union pvrdma_cmd_req));
if (!dsr_info->req) {
- pr_err("Failed to map to command slot address\n");
+ rdma_error_report("Failed to map to command slot address");
rc = -ENOMEM;
goto out_free_dsr;
}
/* Map to response slot */
- pr_dbg("rsp_dma=0x%llx\n", (long long unsigned int)dsr->resp_slot_dma);
dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
sizeof(union pvrdma_cmd_resp));
if (!dsr_info->rsp) {
- pr_err("Failed to map to response slot address\n");
+ rdma_error_report("Failed to map to response slot address");
rc = -ENOMEM;
goto out_free_req;
}
@@ -193,7 +208,6 @@ static int load_dsr(PVRDMADev *dev)
pci_dev, dsr->cq_ring_pages.pdir_dma,
dsr->cq_ring_pages.num_pages);
if (rc) {
- pr_err("Failed to map to initialize CQ ring\n");
rc = -ENOMEM;
goto out_free_rsp;
}
@@ -203,7 +217,6 @@ static int load_dsr(PVRDMADev *dev)
"dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
dsr->async_ring_pages.num_pages);
if (rc) {
- pr_err("Failed to map to initialize event ring\n");
rc = -ENOMEM;
goto out_free_rsp;
}
@@ -230,24 +243,15 @@ static void init_dsr_dev_caps(PVRDMADev *dev)
struct pvrdma_device_shared_region *dsr;
if (dev->dsr_info.dsr == NULL) {
- pr_err("Can't initialized DSR\n");
+ rdma_error_report("Can't initialized DSR");
return;
}
dsr = dev->dsr_info.dsr;
-
dsr->caps.fw_ver = PVRDMA_FW_VERSION;
- pr_dbg("fw_ver=0x%" PRIx64 "\n", dsr->caps.fw_ver);
-
dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
- pr_dbg("mode=%d\n", dsr->caps.mode);
-
dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
- pr_dbg("gid_types=0x%x\n", dsr->caps.gid_types);
-
dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
- pr_dbg("max_uar=%d\n", dsr->caps.max_uar);
-
dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
dsr->caps.max_qp = dev->dev_attr.max_qp;
dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
@@ -257,23 +261,11 @@ static void init_dsr_dev_caps(PVRDMADev *dev)
dsr->caps.max_mr = dev->dev_attr.max_mr;
dsr->caps.max_pd = dev->dev_attr.max_pd;
dsr->caps.max_ah = dev->dev_attr.max_ah;
-
dsr->caps.gid_tbl_len = MAX_GIDS;
- pr_dbg("gid_tbl_len=%d\n", dsr->caps.gid_tbl_len);
-
dsr->caps.sys_image_guid = 0;
- pr_dbg("sys_image_guid=%" PRIx64 "\n", dsr->caps.sys_image_guid);
-
dsr->caps.node_guid = dev->node_guid;
- pr_dbg("node_guid=%" PRIx64 "\n", be64_to_cpu(dsr->caps.node_guid));
-
dsr->caps.phys_port_cnt = MAX_PORTS;
- pr_dbg("phys_port_cnt=%d\n", dsr->caps.phys_port_cnt);
-
dsr->caps.max_pkeys = MAX_PKEYS;
- pr_dbg("max_pkeys=%d\n", dsr->caps.max_pkeys);
-
- pr_dbg("Initialized\n");
}
static void uninit_msix(PCIDevice *pdev, int used_vectors)
@@ -288,7 +280,7 @@ static void uninit_msix(PCIDevice *pdev, int used_vectors)
msix_uninit(pdev, &dev->msix, &dev->msix);
}
-static int init_msix(PCIDevice *pdev, Error **errp)
+static int init_msix(PCIDevice *pdev)
{
PVRDMADev *dev = PVRDMA_DEV(pdev);
int i;
@@ -299,14 +291,14 @@ static int init_msix(PCIDevice *pdev, Error **errp)
RDMA_MSIX_PBA, 0, NULL);
if (rc < 0) {
- error_setg(errp, "Failed to initialize MSI-X");
+ rdma_error_report("Failed to initialize MSI-X");
return rc;
}
for (i = 0; i < RDMA_MAX_INTRS; i++) {
rc = msix_vector_use(PCI_DEVICE(dev), i);
if (rc < 0) {
- error_setg(errp, "Fail mark MSI-X vector %d", i);
+ rdma_error_report("Fail mark MSI-X vector %d", i);
uninit_msix(pdev, i);
return rc;
}
@@ -319,11 +311,12 @@ static void pvrdma_fini(PCIDevice *pdev)
{
PVRDMADev *dev = PVRDMA_DEV(pdev);
- pr_dbg("Closing device %s %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn));
+ notifier_remove(&dev->shutdown_notifier);
pvrdma_qp_ops_fini();
+ rdma_backend_stop(&dev->backend_dev);
+
rdma_rm_fini(&dev->rdma_dev_res, &dev->backend_dev,
dev->backend_eth_device_name);
@@ -335,8 +328,8 @@ static void pvrdma_fini(PCIDevice *pdev)
uninit_msix(pdev, RDMA_MAX_INTRS);
}
- pr_dbg("Device %s %x.%x is down\n", pdev->name, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn));
+ rdma_info_report("Device %s %x.%x is down", pdev->name,
+ PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
}
static void pvrdma_stop(PVRDMADev *dev)
@@ -353,32 +346,28 @@ static void activate_device(PVRDMADev *dev)
{
pvrdma_start(dev);
set_reg_val(dev, PVRDMA_REG_ERR, 0);
- pr_dbg("Device activated\n");
}
static int unquiesce_device(PVRDMADev *dev)
{
- pr_dbg("Device unquiesced\n");
return 0;
}
static void reset_device(PVRDMADev *dev)
{
pvrdma_stop(dev);
-
- pr_dbg("Device reset complete\n");
}
-static uint64_t regs_read(void *opaque, hwaddr addr, unsigned size)
+static uint64_t pvrdma_regs_read(void *opaque, hwaddr addr, unsigned size)
{
PVRDMADev *dev = opaque;
uint32_t val;
- /* pr_dbg("addr=0x%lx, size=%d\n", addr, size); */
+ dev->stats.regs_reads++;
if (get_reg_val(dev, addr, &val)) {
- pr_dbg("Error trying to read REG value from address 0x%x\n",
- (uint32_t)addr);
+ rdma_error_report("Failed to read REG value from address 0x%x",
+ (uint32_t)addr);
return -EINVAL;
}
@@ -387,25 +376,26 @@ static uint64_t regs_read(void *opaque, hwaddr addr, unsigned size)
return val;
}
-static void regs_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+static void pvrdma_regs_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
{
PVRDMADev *dev = opaque;
- /* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
+ dev->stats.regs_writes++;
if (set_reg_val(dev, addr, val)) {
- pr_err("Fail to set REG value, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
- addr, val);
+ rdma_error_report("Failed to set REG value, addr=0x%"PRIx64 ", val=0x%"PRIx64,
+ addr, val);
return;
}
- trace_pvrdma_regs_write(addr, val);
-
switch (addr) {
case PVRDMA_REG_DSRLOW:
+ trace_pvrdma_regs_write(addr, val, "DSRLOW", "");
dev->dsr_info.dma = val;
break;
case PVRDMA_REG_DSRHIGH:
+ trace_pvrdma_regs_write(addr, val, "DSRHIGH", "");
dev->dsr_info.dma |= val << 32;
load_dsr(dev);
init_dsr_dev_caps(dev);
@@ -413,23 +403,27 @@ static void regs_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
case PVRDMA_REG_CTL:
switch (val) {
case PVRDMA_DEVICE_CTL_ACTIVATE:
+ trace_pvrdma_regs_write(addr, val, "CTL", "ACTIVATE");
activate_device(dev);
break;
case PVRDMA_DEVICE_CTL_UNQUIESCE:
+ trace_pvrdma_regs_write(addr, val, "CTL", "UNQUIESCE");
unquiesce_device(dev);
break;
case PVRDMA_DEVICE_CTL_RESET:
+ trace_pvrdma_regs_write(addr, val, "CTL", "URESET");
reset_device(dev);
break;
}
break;
case PVRDMA_REG_IMR:
- pr_dbg("Interrupt mask=0x%" PRIx64 "\n", val);
+ trace_pvrdma_regs_write(addr, val, "INTR_MASK", "");
dev->interrupt_mask = val;
break;
case PVRDMA_REG_REQUEST:
if (val == 0) {
- execute_command(dev);
+ trace_pvrdma_regs_write(addr, val, "REQUEST", "");
+ pvrdma_exec_cmd(dev);
}
break;
default:
@@ -438,8 +432,8 @@ static void regs_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
}
static const MemoryRegionOps regs_ops = {
- .read = regs_read,
- .write = regs_write,
+ .read = pvrdma_regs_read,
+ .write = pvrdma_regs_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = sizeof(uint32_t),
@@ -447,54 +441,60 @@ static const MemoryRegionOps regs_ops = {
},
};
-static uint64_t uar_read(void *opaque, hwaddr addr, unsigned size)
+static uint64_t pvrdma_uar_read(void *opaque, hwaddr addr, unsigned size)
{
return 0xffffffff;
}
-static void uar_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+static void pvrdma_uar_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
{
PVRDMADev *dev = opaque;
- /* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
+ dev->stats.uar_writes++;
switch (addr & 0xFFF) { /* Mask with 0xFFF as each UC gets page */
case PVRDMA_UAR_QP_OFFSET:
- pr_dbg("UAR QP command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
- (uint64_t)addr, val);
if (val & PVRDMA_UAR_QP_SEND) {
+ trace_pvrdma_uar_write(addr, val, "QP", "SEND",
+ val & PVRDMA_UAR_HANDLE_MASK, 0);
pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
}
if (val & PVRDMA_UAR_QP_RECV) {
+ trace_pvrdma_uar_write(addr, val, "QP", "RECV",
+ val & PVRDMA_UAR_HANDLE_MASK, 0);
pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
}
break;
case PVRDMA_UAR_CQ_OFFSET:
- /* pr_dbg("UAR CQ cmd, addr=0x%x, val=0x%lx\n", (uint32_t)addr, val); */
if (val & PVRDMA_UAR_CQ_ARM) {
+ trace_pvrdma_uar_write(addr, val, "CQ", "ARM",
+ val & PVRDMA_UAR_HANDLE_MASK,
+ !!(val & PVRDMA_UAR_CQ_ARM_SOL));
rdma_rm_req_notify_cq(&dev->rdma_dev_res,
val & PVRDMA_UAR_HANDLE_MASK,
!!(val & PVRDMA_UAR_CQ_ARM_SOL));
}
if (val & PVRDMA_UAR_CQ_ARM_SOL) {
- pr_dbg("UAR_CQ_ARM_SOL (%" PRIx64 ")\n",
- val & PVRDMA_UAR_HANDLE_MASK);
+ trace_pvrdma_uar_write(addr, val, "CQ", "ARMSOL - not supported", 0,
+ 0);
}
if (val & PVRDMA_UAR_CQ_POLL) {
- pr_dbg("UAR_CQ_POLL (%" PRIx64 ")\n", val & PVRDMA_UAR_HANDLE_MASK);
+ trace_pvrdma_uar_write(addr, val, "CQ", "POLL",
+ val & PVRDMA_UAR_HANDLE_MASK, 0);
pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
}
break;
default:
- pr_err("Unsupported command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
- addr, val);
+ rdma_error_report("Unsupported command, addr=0x%"PRIx64", val=0x%"PRIx64,
+ addr, val);
break;
}
}
static const MemoryRegionOps uar_ops = {
- .read = uar_read,
- .write = uar_write,
+ .read = pvrdma_uar_read,
+ .write = pvrdma_uar_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = sizeof(uint32_t),
@@ -551,11 +551,9 @@ static void init_dev_caps(PVRDMADev *dev)
(wr_sz + sizeof(struct pvrdma_sge) *
dev->dev_attr.max_sge) - TARGET_PAGE_SIZE;
/* First page is ring state ^^^^ */
- pr_dbg("max_qp_wr=%d\n", dev->dev_attr.max_qp_wr);
dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
TARGET_PAGE_SIZE; /* First page is ring state */
- pr_dbg("max_cqe=%d\n", dev->dev_attr.max_cqe);
}
static int pvrdma_check_ram_shared(Object *obj, void *opaque)
@@ -585,10 +583,8 @@ static void pvrdma_realize(PCIDevice *pdev, Error **errp)
bool ram_shared = false;
PCIDevice *func0;
- init_pr_dbg();
-
- pr_dbg("Initializing device %s %x.%x\n", pdev->name,
- PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
+ rdma_info_report("Initializing device %s %x.%x", pdev->name,
+ PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
if (TARGET_PAGE_SIZE != getpagesize()) {
error_setg(errp, "Target page size must be the same as host page size");
@@ -597,9 +593,7 @@ static void pvrdma_realize(PCIDevice *pdev, Error **errp)
func0 = pci_get_function_0(pdev);
/* Break if not vmxnet3 device in slot 0 */
- if (strcmp(object_get_typename(&func0->qdev.parent_obj), TYPE_VMXNET3)) {
- pr_dbg("func0 type is %s\n",
- object_get_typename(&func0->qdev.parent_obj));
+ if (strcmp(object_get_typename(OBJECT(func0)), TYPE_VMXNET3)) {
error_setg(errp, "Device on %x.0 must be %s", PCI_SLOT(pdev->devfn),
TYPE_VMXNET3);
return;
@@ -626,21 +620,21 @@ static void pvrdma_realize(PCIDevice *pdev, Error **errp)
init_regs(pdev);
- rc = init_msix(pdev, errp);
+ rc = init_msix(pdev);
if (rc) {
goto out;
}
rc = rdma_backend_init(&dev->backend_dev, pdev, &dev->rdma_dev_res,
dev->backend_device_name, dev->backend_port_num,
- &dev->dev_attr, &dev->mad_chr, errp);
+ &dev->dev_attr, &dev->mad_chr);
if (rc) {
goto out;
}
init_dev_caps(dev);
- rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr, errp);
+ rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr);
if (rc) {
goto out;
}
@@ -650,28 +644,25 @@ static void pvrdma_realize(PCIDevice *pdev, Error **errp)
goto out;
}
+ memset(&dev->stats, 0, sizeof(dev->stats));
+
dev->shutdown_notifier.notify = pvrdma_shutdown_notifier;
qemu_register_shutdown_notifier(&dev->shutdown_notifier);
out:
if (rc) {
pvrdma_fini(pdev);
- error_append_hint(errp, "Device fail to load\n");
+ error_append_hint(errp, "Device failed to load\n");
}
}
-static void pvrdma_exit(PCIDevice *pdev)
-{
- pvrdma_fini(pdev);
-}
-
static void pvrdma_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ RdmaProviderClass *ir = INTERFACE_RDMA_PROVIDER_CLASS(klass);
k->realize = pvrdma_realize;
- k->exit = pvrdma_exit;
k->vendor_id = PCI_VENDOR_ID_VMWARE;
k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
k->revision = 0x00;
@@ -680,6 +671,8 @@ static void pvrdma_class_init(ObjectClass *klass, void *data)
dc->desc = "RDMA Device";
dc->props = pvrdma_dev_properties;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
+
+ ir->print_statistics = pvrdma_print_statistics;
}
static const TypeInfo pvrdma_info = {
@@ -689,6 +682,7 @@ static const TypeInfo pvrdma_info = {
.class_init = pvrdma_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { INTERFACE_RDMA_PROVIDER },
{ }
}
};
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-25 12:11:30 +0000