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Diffstat (limited to 'hw/pxa2xx_pcmcia.c')
-rw-r--r--hw/pxa2xx_pcmcia.c95
1 files changed, 42 insertions, 53 deletions
diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
index 74c6817baf..dc522dcf43 100644
--- a/hw/pxa2xx_pcmcia.c
+++ b/hw/pxa2xx_pcmcia.c
@@ -11,16 +11,20 @@
#include "pcmcia.h"
#include "pxa.h"
+
struct PXA2xxPCMCIAState {
PCMCIASocket slot;
PCMCIACardState *card;
+ MemoryRegion common_iomem;
+ MemoryRegion attr_iomem;
+ MemoryRegion iomem;
qemu_irq irq;
qemu_irq cd_irq;
};
-static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
- target_phys_addr_t offset)
+static uint64_t pxa2xx_pcmcia_common_read(void *opaque,
+ target_phys_addr_t offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -31,8 +35,8 @@ static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
return 0;
}
-static void pxa2xx_pcmcia_common_write(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -41,8 +45,8 @@ static void pxa2xx_pcmcia_common_write(void *opaque,
}
}
-static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
- target_phys_addr_t offset)
+static uint64_t pxa2xx_pcmcia_attr_read(void *opaque,
+ target_phys_addr_t offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -53,8 +57,8 @@ static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
return 0;
}
-static void pxa2xx_pcmcia_attr_write(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -63,8 +67,8 @@ static void pxa2xx_pcmcia_attr_write(void *opaque,
}
}
-static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
- target_phys_addr_t offset)
+static uint64_t pxa2xx_pcmcia_io_read(void *opaque,
+ target_phys_addr_t offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -75,8 +79,8 @@ static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
return 0;
}
-static void pxa2xx_pcmcia_io_write(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+static void pxa2xx_pcmcia_io_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -85,40 +89,22 @@ static void pxa2xx_pcmcia_io_write(void *opaque,
}
}
-static CPUReadMemoryFunc * const pxa2xx_pcmcia_common_readfn[] = {
- pxa2xx_pcmcia_common_read,
- pxa2xx_pcmcia_common_read,
- pxa2xx_pcmcia_common_read,
-};
-
-static CPUWriteMemoryFunc * const pxa2xx_pcmcia_common_writefn[] = {
- pxa2xx_pcmcia_common_write,
- pxa2xx_pcmcia_common_write,
- pxa2xx_pcmcia_common_write,
-};
-
-static CPUReadMemoryFunc * const pxa2xx_pcmcia_attr_readfn[] = {
- pxa2xx_pcmcia_attr_read,
- pxa2xx_pcmcia_attr_read,
- pxa2xx_pcmcia_attr_read,
-};
-
-static CPUWriteMemoryFunc * const pxa2xx_pcmcia_attr_writefn[] = {
- pxa2xx_pcmcia_attr_write,
- pxa2xx_pcmcia_attr_write,
- pxa2xx_pcmcia_attr_write,
+static const MemoryRegionOps pxa2xx_pcmcia_common_ops = {
+ .read = pxa2xx_pcmcia_common_read,
+ .write = pxa2xx_pcmcia_common_write,
+ .endianness = DEVICE_NATIVE_ENDIAN
};
-static CPUReadMemoryFunc * const pxa2xx_pcmcia_io_readfn[] = {
- pxa2xx_pcmcia_io_read,
- pxa2xx_pcmcia_io_read,
- pxa2xx_pcmcia_io_read,
+static const MemoryRegionOps pxa2xx_pcmcia_attr_ops = {
+ .read = pxa2xx_pcmcia_attr_read,
+ .write = pxa2xx_pcmcia_attr_write,
+ .endianness = DEVICE_NATIVE_ENDIAN
};
-static CPUWriteMemoryFunc * const pxa2xx_pcmcia_io_writefn[] = {
- pxa2xx_pcmcia_io_write,
- pxa2xx_pcmcia_io_write,
- pxa2xx_pcmcia_io_write,
+static const MemoryRegionOps pxa2xx_pcmcia_io_ops = {
+ .read = pxa2xx_pcmcia_io_read,
+ .write = pxa2xx_pcmcia_io_write,
+ .endianness = DEVICE_NATIVE_ENDIAN
};
static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
@@ -130,30 +116,33 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
qemu_set_irq(s->irq, level);
}
-PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
+PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
+ target_phys_addr_t base)
{
- int iomemtype;
PXA2xxPCMCIAState *s;
s = (PXA2xxPCMCIAState *)
g_malloc0(sizeof(PXA2xxPCMCIAState));
/* Socket I/O Memory Space */
- iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,
- pxa2xx_pcmcia_io_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
+ memory_region_init_io(&s->iomem, &pxa2xx_pcmcia_io_ops, s,
+ "pxa2xx-pcmcia-io", 0x04000000);
+ memory_region_add_subregion(sysmem, base | 0x00000000,
+ &s->iomem);
/* Then next 64 MB is reserved */
/* Socket Attribute Memory Space */
- iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,
- pxa2xx_pcmcia_attr_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
+ memory_region_init_io(&s->attr_iomem, &pxa2xx_pcmcia_attr_ops, s,
+ "pxa2xx-pcmcia-attribute", 0x04000000);
+ memory_region_add_subregion(sysmem, base | 0x08000000,
+ &s->attr_iomem);
/* Socket Common Memory Space */
- iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,
- pxa2xx_pcmcia_common_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);
+ memory_region_init_io(&s->common_iomem, &pxa2xx_pcmcia_common_ops, s,
+ "pxa2xx-pcmcia-common", 0x04000000);
+ memory_region_add_subregion(sysmem, base | 0x0c000000,
+ &s->common_iomem);
if (base == 0x30000000)
s->slot.slot_string = "PXA PC Card Socket 1";