diff options
Diffstat (limited to 'hw/pxa2xx_gpio.c')
| -rw-r--r-- | hw/pxa2xx_gpio.c | 150 |
1 files changed, 73 insertions, 77 deletions
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index 0d034462d2..789965d88b 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -8,15 +8,18 @@ */ #include "hw.h" +#include "sysbus.h" #include "pxa.h" #define PXA2XX_GPIO_BANKS 4 +typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; struct PXA2xxGPIOInfo { - qemu_irq *pic; + SysBusDevice busdev; + qemu_irq irq0, irq1, irqX; int lines; + int ncpu; CPUState *cpu_env; - qemu_irq *in; /* XXX: GNU C vectors are more suitable */ uint32_t ilevel[PXA2XX_GPIO_BANKS]; @@ -66,19 +69,19 @@ static struct { static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) { if (s->status[0] & (1 << 0)) - qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]); + qemu_irq_raise(s->irq0); else - qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]); + qemu_irq_lower(s->irq0); if (s->status[0] & (1 << 1)) - qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]); + qemu_irq_raise(s->irq1); else - qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]); + qemu_irq_lower(s->irq1); if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) - qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]); + qemu_irq_raise(s->irqX); else - qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]); + qemu_irq_lower(s->irqX); } /* Bitmap of pins used as standby and sleep wake-up sources. */ @@ -249,96 +252,89 @@ static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = { pxa2xx_gpio_write }; -static void pxa2xx_gpio_save(QEMUFile *f, void *opaque) -{ - PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; - int i; - - qemu_put_be32(f, s->lines); - - for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { - qemu_put_be32s(f, &s->ilevel[i]); - qemu_put_be32s(f, &s->olevel[i]); - qemu_put_be32s(f, &s->dir[i]); - qemu_put_be32s(f, &s->rising[i]); - qemu_put_be32s(f, &s->falling[i]); - qemu_put_be32s(f, &s->status[i]); - qemu_put_be32s(f, &s->gafr[i * 2 + 0]); - qemu_put_be32s(f, &s->gafr[i * 2 + 1]); - - qemu_put_be32s(f, &s->prev_level[i]); - } -} - -static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id) +DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, + CPUState *env, qemu_irq *pic, int lines) { - PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; - int i; + DeviceState *dev; - if (qemu_get_be32(f) != s->lines) - return -EINVAL; + dev = qdev_create(NULL, "pxa2xx-gpio"); + qdev_prop_set_int32(dev, "lines", lines); + qdev_prop_set_int32(dev, "ncpu", env->cpu_index); + qdev_init_nofail(dev); - for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { - qemu_get_be32s(f, &s->ilevel[i]); - qemu_get_be32s(f, &s->olevel[i]); - qemu_get_be32s(f, &s->dir[i]); - qemu_get_be32s(f, &s->rising[i]); - qemu_get_be32s(f, &s->falling[i]); - qemu_get_be32s(f, &s->status[i]); - qemu_get_be32s(f, &s->gafr[i * 2 + 0]); - qemu_get_be32s(f, &s->gafr[i * 2 + 1]); - - qemu_get_be32s(f, &s->prev_level[i]); - } + sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); + sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[PXA2XX_PIC_GPIO_0]); + sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[PXA2XX_PIC_GPIO_1]); + sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[PXA2XX_PIC_GPIO_X]); - return 0; + return dev; } -PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base, - CPUState *env, qemu_irq *pic, int lines) +static int pxa2xx_gpio_initfn(SysBusDevice *dev) { int iomemtype; PXA2xxGPIOInfo *s; - s = (PXA2xxGPIOInfo *) - qemu_mallocz(sizeof(PXA2xxGPIOInfo)); - memset(s, 0, sizeof(PXA2xxGPIOInfo)); - s->pic = pic; - s->lines = lines; - s->cpu_env = env; - s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines); + s = FROM_SYSBUS(PXA2xxGPIOInfo, dev); - iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn, - pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00001000, iomemtype); + s->cpu_env = qemu_get_cpu(s->ncpu); - register_savevm(NULL, "pxa2xx_gpio", 0, 0, - pxa2xx_gpio_save, pxa2xx_gpio_load, s); - - return s; -} + qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines); + qdev_init_gpio_out(&dev->qdev, s->handler, s->lines); -qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s) -{ - return s->in; -} + iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn, + pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); -void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s, - int line, qemu_irq handler) -{ - if (line >= s->lines) { - printf("%s: No GPIO pin %i\n", __FUNCTION__, line); - return; - } + sysbus_init_mmio(dev, 0x1000, iomemtype); + sysbus_init_irq(dev, &s->irq0); + sysbus_init_irq(dev, &s->irq1); + sysbus_init_irq(dev, &s->irqX); - s->handler[line] = handler; + return 0; } /* * Registers a callback to notify on GPLR reads. This normally * shouldn't be needed but it is used for the hack on Spitz machines. */ -void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler) +void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler) { + PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, sysbus_from_qdev(dev)); s->read_notify = handler; } + +static const VMStateDescription vmstate_pxa2xx_gpio_regs = { + .name = "pxa2xx-gpio", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_INT32(lines, PXA2xxGPIOInfo), + VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), + VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), + VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), + VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), + VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), + VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), + VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2), + VMSTATE_END_OF_LIST(), + }, +}; + +static SysBusDeviceInfo pxa2xx_gpio_info = { + .init = pxa2xx_gpio_initfn, + .qdev.name = "pxa2xx-gpio", + .qdev.desc = "PXA2xx GPIO controller", + .qdev.size = sizeof(PXA2xxGPIOInfo), + .qdev.props = (Property []) { + DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), + DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0), + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void pxa2xx_gpio_register(void) +{ + sysbus_register_withprop(&pxa2xx_gpio_info); +} +device_init(pxa2xx_gpio_register); |