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-rw-r--r--hw/ppc/e500.c32
-rw-r--r--hw/ppc/mac_newworld.c40
-rw-r--r--hw/ppc/mac_oldworld.c20
-rw-r--r--hw/ppc/pnv.c4
-rw-r--r--hw/ppc/ppc440_uc.c8
-rw-r--r--hw/ppc/prep.c9
-rw-r--r--hw/ppc/sam460ex.c4
-rw-r--r--hw/ppc/spapr.c8
-rw-r--r--hw/ppc/spapr_irq.c4
-rw-r--r--hw/ppc/spapr_vio.c4
-rw-r--r--hw/ppc/virtex_ml507.c9
11 files changed, 72 insertions, 70 deletions
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 2a0b66a152..06f4a38266 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -743,12 +743,12 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
- dev = qdev_create(NULL, TYPE_OPENPIC);
+ dev = qdev_new(TYPE_OPENPIC);
object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
k = 0;
@@ -768,10 +768,10 @@ static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
DeviceState *dev;
CPUState *cs;
- dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
+ dev = qdev_new(TYPE_KVM_OPENPIC);
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
- object_property_set_bool(OBJECT(dev), true, "realized", &err);
+ qdev_realize_and_unref(dev, NULL, &err);
if (err) {
error_propagate(errp, err);
object_unparent(OBJECT(dev));
@@ -913,10 +913,10 @@ void ppce500_init(MachineState *machine)
/* Register Memory */
memory_region_add_subregion(address_space_mem, 0, machine->ram);
- dev = qdev_create(NULL, "e500-ccsr");
+ dev = qdev_new("e500-ccsr");
object_property_add_child(qdev_get_machine(), "e500-ccsr",
OBJECT(dev));
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
@@ -937,9 +937,9 @@ void ppce500_init(MachineState *machine)
serial_hd(1), DEVICE_BIG_ENDIAN);
}
/* I2C */
- dev = qdev_create(NULL, "mpc-i2c");
+ dev = qdev_new("mpc-i2c");
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
@@ -948,18 +948,18 @@ void ppce500_init(MachineState *machine)
/* General Utility device */
- dev = qdev_create(NULL, "mpc8544-guts");
- qdev_init_nofail(dev);
+ dev = qdev_new("mpc8544-guts");
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
sysbus_mmio_get_region(s, 0));
/* PCI */
- dev = qdev_create(NULL, "e500-pcihost");
+ dev = qdev_new("e500-pcihost");
object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
@@ -985,9 +985,9 @@ void ppce500_init(MachineState *machine)
if (pmc->has_mpc8xxx_gpio) {
qemu_irq poweroff_irq;
- dev = qdev_create(NULL, "mpc8xxx_gpio");
+ dev = qdev_new("mpc8xxx_gpio");
s = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
sysbus_mmio_get_region(s, 0));
@@ -999,11 +999,11 @@ void ppce500_init(MachineState *machine)
/* Platform Bus Device */
if (pmc->has_platform_bus) {
- dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
s = SYS_BUS_DEVICE(pms->pbus_dev);
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 3507f26f6e..69281d7834 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -242,8 +242,8 @@ static void ppc_core99_init(MachineState *machine)
}
/* UniN init */
- dev = qdev_create(NULL, TYPE_UNI_NORTH);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_UNI_NORTH);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(get_system_memory(), 0xf8000000,
sysbus_mmio_get_region(s, 0));
@@ -288,9 +288,9 @@ static void ppc_core99_init(MachineState *machine)
}
}
- pic_dev = qdev_create(NULL, TYPE_OPENPIC);
+ pic_dev = qdev_new(TYPE_OPENPIC);
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
- qdev_init_nofail(pic_dev);
+ qdev_realize_and_unref(pic_dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(pic_dev);
k = 0;
for (i = 0; i < smp_cpus; i++) {
@@ -303,10 +303,10 @@ static void ppc_core99_init(MachineState *machine)
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
/* Uninorth AGP bus */
- dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
+ dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
@@ -322,29 +322,29 @@ static void ppc_core99_init(MachineState *machine)
} else {
/* Use values found on a real PowerMac */
/* Uninorth AGP bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
+ dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
/* Uninorth internal bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf4800000);
sysbus_mmio_map(s, 1, 0xf4c00000);
/* Uninorth main bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
@@ -403,13 +403,13 @@ static void ppc_core99_init(MachineState *machine)
}
adb_bus = qdev_get_child_bus(dev, "adb.0");
- dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
+ dev = qdev_new(TYPE_ADB_KEYBOARD);
qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
- dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
+ dev = qdev_new(TYPE_ADB_MOUSE);
qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
}
if (machine->usb) {
@@ -441,22 +441,22 @@ static void ppc_core99_init(MachineState *machine)
move the NVRAM out of ROM again for KVM */
nvram_addr = 0xFFE00000;
}
- dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
+ dev = qdev_new(TYPE_MACIO_NVRAM);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 1);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
nvr = MACIO_NVRAM(dev);
pmac_format_nvram_partition(nvr, 0x2000);
/* No PCI init: the BIOS will do it */
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 0b4c1c6373..cfc2eae1d9 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -222,8 +222,8 @@ static void ppc_heathrow_init(MachineState *machine)
}
/* XXX: we register only 1 output pin for heathrow PIC */
- pic_dev = qdev_create(NULL, TYPE_HEATHROW);
- qdev_init_nofail(pic_dev);
+ pic_dev = qdev_new(TYPE_HEATHROW);
+ qdev_realize_and_unref(pic_dev, NULL, &error_fatal);
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
@@ -252,11 +252,11 @@ static void ppc_heathrow_init(MachineState *machine)
}
/* Grackle PCI host bridge */
- dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, GRACKLE_BASE);
sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
@@ -295,10 +295,10 @@ static void ppc_heathrow_init(MachineState *machine)
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
- dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
- qdev_init_nofail(dev);
- dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_ADB_KEYBOARD);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
+ dev = qdev_new(TYPE_ADB_MOUSE);
+ qdev_realize_and_unref(dev, adb_bus, &error_fatal);
if (machine_usb(machine)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
@@ -309,13 +309,13 @@ static void ppc_heathrow_init(MachineState *machine)
/* No PCI init: the BIOS will do it */
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 9d1a11adb7..e3b6f0b884 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -729,12 +729,12 @@ static void pnv_init(MachineState *machine)
/*
* Create our simple PNOR device
*/
- dev = qdev_create(NULL, TYPE_PNV_PNOR);
+ dev = qdev_new(TYPE_PNV_PNOR);
if (pnor) {
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
&error_abort);
}
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
pnv->pnor = PNV_PNOR(dev);
/* load skiboot firmware */
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index dc318c7aa7..c1cf8d0f46 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -1367,13 +1367,13 @@ void ppc460ex_pcie_init(CPUPPCState *env)
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST);
+ dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
- dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST);
+ dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
}
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 9266453dd9..c7af0e16c3 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -35,6 +35,7 @@
#include "hw/pci/pci_host.h"
#include "hw/ppc/ppc.h"
#include "hw/boards.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "hw/irq.h"
@@ -268,7 +269,7 @@ static void ibm_40p_init(MachineState *machine)
qemu_register_reset(ppc_prep_reset, cpu);
/* PCI host */
- dev = qdev_create(NULL, "raven-pcihost");
+ dev = qdev_new("raven-pcihost");
if (!bios_name) {
bios_name = "openbios-ppc";
}
@@ -276,7 +277,7 @@ static void ibm_40p_init(MachineState *machine)
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
pcihost = SYS_BUS_DEVICE(dev);
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
if (!pci_bus) {
error_report("could not create PCI host controller");
@@ -338,13 +339,13 @@ static void ibm_40p_init(MachineState *machine)
}
/* Prepare firmware configuration for OpenBIOS */
- dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ dev = qdev_new(TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 42a8c9fb7f..503bd21728 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -370,10 +370,10 @@ static void sam460ex_init(MachineState *machine)
/* USB */
sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
- dev = qdev_create(NULL, "sysbus-ohci");
+ dev = qdev_new("sysbus-ohci");
qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
qdev_prop_set_uint32(dev, "num-ports", 6);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
sbdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
sysbus_connect_irq(sbdev, 0, uic[2][30]);
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 6a315c0dc8..1228aeb4b0 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1712,7 +1712,7 @@ static void spapr_machine_reset(MachineState *machine)
static void spapr_create_nvram(SpaprMachineState *spapr)
{
- DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
+ DeviceState *dev = qdev_new("spapr-nvram");
DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) {
@@ -1720,7 +1720,7 @@ static void spapr_create_nvram(SpaprMachineState *spapr)
&error_fatal);
}
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal);
spapr->nvram = (struct SpaprNvram *)dev;
}
@@ -2640,9 +2640,9 @@ static PCIHostState *spapr_create_default_phb(void)
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
+ dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "index", 0);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
return PCI_HOST_BRIDGE(dev);
}
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 0c594aa72e..f2ade64e7d 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -325,7 +325,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
DeviceState *dev;
int i;
- dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
+ dev = qdev_new(TYPE_SPAPR_XIVE);
qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BASE);
/*
* 8 XIVE END structures per CPU. One for each available
@@ -334,7 +334,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric",
&error_abort);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
spapr->xive = SPAPR_XIVE(dev);
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index 0b085eabe4..61558db1bf 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -576,8 +576,8 @@ SpaprVioBus *spapr_vio_bus_init(void)
DeviceState *dev;
/* Create bridge device */
- dev = qdev_create(NULL, TYPE_SPAPR_VIO_BRIDGE);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_SPAPR_VIO_BRIDGE);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
/* Create bus on bridge device */
qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 0dacfcd236..f28a69c0f9 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -36,6 +36,7 @@
#include "sysemu/device_tree.h"
#include "hw/loader.h"
#include "elf.h"
+#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/option.h"
@@ -228,9 +229,9 @@ static void virtex_init(MachineState *machine)
64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
- dev = qdev_create(NULL, "xlnx.xps-intc");
+ dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 0);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
for (i = 0; i < 32; i++) {
@@ -241,10 +242,10 @@ static void virtex_init(MachineState *machine)
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 62 Mhz. */
- dev = qdev_create(NULL, "xlnx.xps-timer");
+ dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-30 07:34:32 +0000