4 files changed, 8 insertions, 4 deletions
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 1aaa5154d1..a2e60b4896 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -288,8 +288,8 @@ static int ppce500_load_device_tree(MachineState *machine,
     int len;
     uint32_t pci_ranges[14] =
         {
-            0x2000000, 0x0, 0xc0000000,
-            0x0, 0xc0000000,
+            0x2000000, 0x0, params->pci_mmio_bus_base,
+            params->pci_mmio_base >> 32, params->pci_mmio_base,
             0x0, 0x20000000,
 
             0x1000000, 0x0, 0x0,
@@ -915,8 +915,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
     if (!pci_bus)
         printf("couldn't create PCI controller!\n");
 
-    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base);
-
     if (pci_bus) {
         /* Register network interfaces. */
         for (i = 0; i < nb_nics; i++) {
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index d96f72d484..ef224ea5e6 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -19,6 +19,8 @@ typedef struct PPCE500Params {
     int platform_bus_num_irqs;
     hwaddr ccsrbar_base;
     hwaddr pci_pio_base;
+    hwaddr pci_mmio_base;
+    hwaddr pci_mmio_bus_base;
     hwaddr spin_base;
 } PPCE500Params;
 
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 1b8a68d223..14b14eaa7d 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -43,6 +43,8 @@ static void e500plat_init(MachineState *machine)
         .platform_bus_num_irqs = 10,
         .ccsrbar_base = 0xFE0000000ULL,
         .pci_pio_base = 0xFE1000000ULL,
+        .pci_mmio_base = 0xC00000000ULL,
+        .pci_mmio_bus_base = 0xE0000000ULL,
         .spin_base = 0xFEF000000ULL,
     };
 
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index fb74b3ff80..3a3b141e43 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -35,6 +35,8 @@ static void mpc8544ds_init(MachineState *machine)
         .fixup_devtree = mpc8544ds_fixup_devtree,
         .mpic_version = OPENPIC_MODEL_FSL_MPIC_20,
         .ccsrbar_base = 0xE0000000ULL,
+        .pci_mmio_base = 0xC0000000ULL,
+        .pci_mmio_bus_base = 0xC0000000ULL,
         .pci_pio_base = 0xE1000000ULL,
         .spin_base = 0xEF000000ULL,
     };