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Diffstat (limited to 'hw/ppc/ppc4xx_devs.c')
-rw-r--r--hw/ppc/ppc4xx_devs.c145
1 files changed, 72 insertions, 73 deletions
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f4d7ae9567..7d40c1b68a 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -459,32 +459,10 @@ enum {
MAL0_RCBS1 = 0x1E1,
};
-typedef struct ppc4xx_mal_t ppc4xx_mal_t;
-struct ppc4xx_mal_t {
- qemu_irq irqs[4];
- uint32_t cfg;
- uint32_t esr;
- uint32_t ier;
- uint32_t txcasr;
- uint32_t txcarr;
- uint32_t txeobisr;
- uint32_t txdeir;
- uint32_t rxcasr;
- uint32_t rxcarr;
- uint32_t rxeobisr;
- uint32_t rxdeir;
- uint32_t *txctpr;
- uint32_t *rxctpr;
- uint32_t *rcbs;
- uint8_t txcnum;
- uint8_t rxcnum;
-};
-
-static void ppc4xx_mal_reset(void *opaque)
+static void ppc4xx_mal_reset(DeviceState *dev)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
- mal = opaque;
mal->cfg = 0x0007C000;
mal->esr = 0x00000000;
mal->ier = 0x00000000;
@@ -498,10 +476,9 @@ static void ppc4xx_mal_reset(void *opaque)
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = opaque;
uint32_t ret;
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
ret = mal->cfg;
@@ -555,13 +532,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = opaque;
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x80000000) {
- ppc4xx_mal_reset(mal);
+ ppc4xx_mal_reset(DEVICE(mal));
}
mal->cfg = val & 0x00FFC087;
break;
@@ -612,59 +588,76 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
}
}
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4])
+static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
int i;
- assert(txcnum <= 32 && rxcnum <= 32);
- mal = g_malloc0(sizeof(*mal));
- mal->txcnum = txcnum;
- mal->rxcnum = rxcnum;
- mal->txctpr = g_new0(uint32_t, txcnum);
- mal->rxctpr = g_new0(uint32_t, rxcnum);
- mal->rcbs = g_new0(uint32_t, rxcnum);
- for (i = 0; i < 4; i++) {
- mal->irqs[i] = irqs[i];
+ if (mal->txcnum > 32 || mal->rxcnum > 32) {
+ error_setg(errp, "invalid TXC/RXC number");
+ return;
+ }
+
+ mal->txctpr = g_new0(uint32_t, mal->txcnum);
+ mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
+ mal->rcbs = g_new0(uint32_t, mal->rxcnum);
+
+ for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]);
}
- qemu_register_reset(&ppc4xx_mal_reset, mal);
- ppc_dcr_register(env, MAL0_CFG,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_ESR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_IER,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- for (i = 0; i < txcnum; i++) {
- ppc_dcr_register(env, MAL0_TXCTP0R + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+
+ ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->txcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
- ppc_dcr_register(env, MAL0_RXCTP0R + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->rxcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
- ppc_dcr_register(env, MAL0_RCBS0 + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->rxcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
}
}
+static void ppc4xx_mal_finalize(Object *obj)
+{
+ Ppc4xxMalState *mal = PPC4xx_MAL(obj);
+
+ g_free(mal->rcbs);
+ g_free(mal->rxctpr);
+ g_free(mal->txctpr);
+}
+
+static Property ppc4xx_mal_properties[] = {
+ DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
+ DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_mal_realize;
+ dc->reset = ppc4xx_mal_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_mal_properties);
+}
+
/* PPC4xx_DCR_DEVICE */
void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
@@ -696,6 +689,12 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
+ .name = TYPE_PPC4xx_MAL,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxMalState),
+ .instance_finalize = ppc4xx_mal_finalize,
+ .class_init = ppc4xx_mal_class_init,
+ }, {
.name = TYPE_PPC4xx_DCR_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc4xxDcrDeviceState),
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-24 21:16:38 +0000