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-rw-r--r--hw/pcie_port.c12
1 files changed, 1 insertions, 11 deletions
diff --git a/hw/pcie_port.c b/hw/pcie_port.c
index 8a36f5cfc7..d6350e5e73 100644
--- a/hw/pcie_port.c
+++ b/hw/pcie_port.c
@@ -27,23 +27,13 @@ void pcie_port_init_reg(PCIDevice *d)
pci_set_word(d->config + PCI_STATUS, 0);
pci_set_word(d->config + PCI_SEC_STATUS, 0);
- /* Unlike conventional pci bridge, some bits are hardwared to 0. */
+ /* Unlike conventional pci bridge, some bits are hardwired to 0. */
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_SERR |
PCI_BRIDGE_CTL_BUS_RESET);
-
- /* 7.5.3.5 Prefetchable Memory Base Limit
- * The Prefetchable Memory Base and Prefetchable Memory Limit registers
- * must indicate that 64-bit addresses are supported, as defined in
- * PCI-to-PCI Bridge Architecture Specification, Revision 1.2.
- */
- pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
- PCI_PREF_RANGE_TYPE_64);
- pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
- PCI_PREF_RANGE_TYPE_64);
}
/**************************************************************************