diff options
Diffstat (limited to 'hw/pci-host/q35.c')
| -rw-r--r-- | hw/pci-host/q35.c | 31 |
1 files changed, 24 insertions, 7 deletions
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 24df6b55cb..8c3ee535ff 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -40,12 +40,12 @@ static int q35_host_init(SysBusDevice *dev) PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev); - memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci, + memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci, "pci-conf-idx", 4); sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); - memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci, + memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci, "pci-conf-data", 4); sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); @@ -63,6 +63,13 @@ static int q35_host_init(SysBusDevice *dev) return 0; } +static const char *q35_host_root_bus_path(PCIHostState *host_bridge, + PCIBus *rootbus) +{ + /* For backwards compat with old device paths */ + return "0000"; +} + static Property mch_props[] = { DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), @@ -73,7 +80,9 @@ static void q35_host_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); + hc->root_bus_path = q35_host_root_bus_path; k->init = q35_host_init; dc->props = mch_props; dc->fw_name = "pci"; @@ -244,8 +253,16 @@ static int mch_init(PCIDevice *d) hwaddr pci_hole64_size; MCHPCIState *mch = MCH_PCI_DEVICE(d); + /* Leave enough space for the biggest MCFG BAR */ + /* TODO: this matches current bios behaviour, but + * it's not a power of two, which means an MTRR + * can't cover it exactly. + */ + mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + + MCH_HOST_BRIDGE_PCIEXBAR_MAX; + /* setup pci memory regions */ - memory_region_init_alias(&mch->pci_hole, "pci-hole", + memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", mch->pci_address_space, mch->below_4g_mem_size, 0x100000000ULL - mch->below_4g_mem_size); @@ -253,7 +270,7 @@ static int mch_init(PCIDevice *d) &mch->pci_hole); pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : ((uint64_t)1 << 62)); - memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64", + memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", mch->pci_address_space, 0x100000000ULL + mch->above_4g_mem_size, pci_hole64_size); @@ -264,15 +281,15 @@ static int mch_init(PCIDevice *d) } /* smram */ cpu_smm_register(&mch_set_smm, mch); - memory_region_init_alias(&mch->smram_region, "smram-region", + memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", mch->pci_address_space, 0xa0000, 0x20000); memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, &mch->smram_region, 1); memory_region_set_enabled(&mch->smram_region, false); - init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space, + init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); for (i = 0; i < 12; ++i) { - init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space, + init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } |