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Diffstat (limited to 'hw/omap_dss.c')
-rw-r--r--hw/omap_dss.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/hw/omap_dss.c b/hw/omap_dss.c
index 12d288052d..044f2d2428 100644
--- a/hw/omap_dss.c
+++ b/hw/omap_dss.c
@@ -59,7 +59,7 @@ struct omap_dss_s {
int nx;
int ny;
- a_target_phys_addr addr[3];
+ target_phys_addr_t addr[3];
uint32_t attr;
uint32_t tresh;
@@ -167,7 +167,7 @@ void omap_dss_reset(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
-static uint32_t omap_diss_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -200,7 +200,7 @@ static uint32_t omap_diss_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_diss_write(void *opaque, a_target_phys_addr addr,
+static void omap_diss_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -242,7 +242,7 @@ static CPUWriteMemoryFunc * const omap_diss1_writefn[] = {
omap_diss_write,
};
-static uint32_t omap_disc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -362,7 +362,7 @@ static uint32_t omap_disc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_disc_write(void *opaque, a_target_phys_addr addr,
+static void omap_disc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -488,11 +488,11 @@ static void omap_disc_write(void *opaque, a_target_phys_addr addr,
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
- s->dispc.l[0].addr[0] = (a_target_phys_addr) value;
+ s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
- s->dispc.l[0].addr[1] = (a_target_phys_addr) value;
+ s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
@@ -529,7 +529,7 @@ static void omap_disc_write(void *opaque, a_target_phys_addr addr,
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
- s->dispc.l[0].addr[2] = (a_target_phys_addr) value;
+ s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
s->dispc.invalidate = 1;
break;
@@ -594,11 +594,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
static void omap_rfbi_transfer_start(struct omap_dss_s *s)
{
void *data;
- a_target_phys_addr len;
- a_target_phys_addr data_addr;
+ target_phys_addr_t len;
+ target_phys_addr_t data_addr;
int pitch;
static void *bounce_buffer;
- static a_target_phys_addr bounce_len;
+ static target_phys_addr_t bounce_len;
if (!s->rfbi.enable || s->rfbi.busy)
return;
@@ -655,7 +655,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
-static uint32_t omap_rfbi_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -717,7 +717,7 @@ static uint32_t omap_rfbi_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_rfbi_write(void *opaque, a_target_phys_addr addr,
+static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -853,7 +853,7 @@ static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = {
omap_rfbi_write,
};
-static uint32_t omap_venc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
{
switch (addr) {
case 0x00: /* REV_ID */
@@ -908,7 +908,7 @@ static uint32_t omap_venc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_venc_write(void *opaque, a_target_phys_addr addr,
+static void omap_venc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
switch (addr) {
@@ -972,7 +972,7 @@ static CPUWriteMemoryFunc * const omap_venc1_writefn[] = {
omap_venc_write,
};
-static uint32_t omap_im3_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
{
switch (addr) {
case 0x0a8: /* SBIMERRLOGA */
@@ -993,7 +993,7 @@ static uint32_t omap_im3_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_im3_write(void *opaque, a_target_phys_addr addr,
+static void omap_im3_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
switch (addr) {
@@ -1023,7 +1023,7 @@ static CPUWriteMemoryFunc * const omap_im3_writefn[] = {
};
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
- a_target_phys_addr l3_base,
+ target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)