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path: root/hw/nvram/fw_cfg.c
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Diffstat (limited to 'hw/nvram/fw_cfg.c')
-rw-r--r--hw/nvram/fw_cfg.c79
1 files changed, 19 insertions, 60 deletions
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index e881e3b812..5bd904487f 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -37,17 +37,6 @@
#define FW_CFG_FILE_SLOTS_DFLT 0x20
-#define FW_CFG_NAME "fw_cfg"
-#define FW_CFG_PATH "/machine/" FW_CFG_NAME
-
-#define TYPE_FW_CFG "fw_cfg"
-#define TYPE_FW_CFG_IO "fw_cfg_io"
-#define TYPE_FW_CFG_MEM "fw_cfg_mem"
-
-#define FW_CFG(obj) OBJECT_CHECK(FWCfgState, (obj), TYPE_FW_CFG)
-#define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_IO)
-#define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM)
-
/* FW_CFG_VERSION bits */
#define FW_CFG_VERSION 0x01
#define FW_CFG_VERSION_DMA 0x02
@@ -61,51 +50,12 @@
#define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
-typedef struct FWCfgEntry {
+struct FWCfgEntry {
uint32_t len;
bool allow_write;
uint8_t *data;
void *callback_opaque;
FWCfgReadCallback read_callback;
-} FWCfgEntry;
-
-struct FWCfgState {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- uint16_t file_slots;
- FWCfgEntry *entries[2];
- int *entry_order;
- FWCfgFiles *files;
- uint16_t cur_entry;
- uint32_t cur_offset;
- Notifier machine_ready;
-
- int fw_cfg_order_override;
-
- bool dma_enabled;
- dma_addr_t dma_addr;
- AddressSpace *dma_as;
- MemoryRegion dma_iomem;
-};
-
-struct FWCfgIoState {
- /*< private >*/
- FWCfgState parent_obj;
- /*< public >*/
-
- MemoryRegion comb_iomem;
-};
-
-struct FWCfgMemState {
- /*< private >*/
- FWCfgState parent_obj;
- /*< public >*/
-
- MemoryRegion ctl_iomem, data_iomem;
- uint32_t data_width;
- MemoryRegionOps wide_data_ops;
};
#define JPG_FILE 0
@@ -909,17 +859,16 @@ static void fw_cfg_machine_ready(struct Notifier *n, void *data)
-static void fw_cfg_init1(DeviceState *dev)
+static void fw_cfg_common_realize(DeviceState *dev, Error **errp)
{
FWCfgState *s = FW_CFG(dev);
MachineState *machine = MACHINE(qdev_get_machine());
uint32_t version = FW_CFG_VERSION;
- assert(!object_resolve_path(FW_CFG_PATH, NULL));
-
- object_property_add_child(OBJECT(machine), FW_CFG_NAME, OBJECT(s), NULL);
-
- qdev_init_nofail(dev);
+ if (!fw_cfg_find()) {
+ error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG);
+ return;
+ }
fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16);
@@ -952,7 +901,9 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
qdev_prop_set_bit(dev, "dma_enabled", false);
}
- fw_cfg_init1(dev);
+ object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
+ OBJECT(dev), NULL);
+ qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
ios = FW_CFG_IO(dev);
@@ -990,7 +941,9 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
qdev_prop_set_bit(dev, "dma_enabled", false);
}
- fw_cfg_init1(dev);
+ object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
+ OBJECT(dev), NULL);
+ qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sbd, 0, ctl_addr);
@@ -1017,9 +970,11 @@ FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
FWCfgState *fw_cfg_find(void)
{
- return FW_CFG(object_resolve_path(FW_CFG_PATH, NULL));
+ /* Returns NULL unless there is exactly one fw_cfg device */
+ return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
}
+
static void fw_cfg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1091,6 +1046,8 @@ static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
&fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
sizeof(dma_addr_t));
}
+
+ fw_cfg_common_realize(dev, errp);
}
static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
@@ -1157,6 +1114,8 @@ static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
sizeof(dma_addr_t));
sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
}
+
+ fw_cfg_common_realize(dev, errp);
}
static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)