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-rw-r--r--hw/net/allwinner-sun8i-emac.c18
-rw-r--r--hw/net/ftgmac100.c25
-rw-r--r--hw/net/imx_fec.c32
-rw-r--r--hw/net/npcm7xx_emc.c20
4 files changed, 60 insertions, 35 deletions
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
index ff611f18fb..ecc0245fe8 100644
--- a/hw/net/allwinner-sun8i-emac.c
+++ b/hw/net/allwinner-sun8i-emac.c
@@ -350,7 +350,8 @@ static void allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
FrameDescriptor *desc,
uint32_t phys_addr)
{
- dma_memory_read(&s->dma_as, phys_addr, desc, sizeof(*desc));
+ dma_memory_read(&s->dma_as, phys_addr, desc, sizeof(*desc),
+ MEMTXATTRS_UNSPECIFIED);
}
static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
@@ -402,7 +403,8 @@ static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
FrameDescriptor *desc,
uint32_t phys_addr)
{
- dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc));
+ dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc),
+ MEMTXATTRS_UNSPECIFIED);
}
static bool allwinner_sun8i_emac_can_receive(NetClientState *nc)
@@ -460,7 +462,8 @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
<< RX_DESC_STATUS_FRM_LEN_SHIFT;
}
- dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes);
+ dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes,
+ MEMTXATTRS_UNSPECIFIED);
allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr);
trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
desc_bytes);
@@ -512,7 +515,8 @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
desc.status |= TX_DESC_STATUS_LENGTH_ERR;
break;
}
- dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, bytes);
+ dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes,
+ bytes, MEMTXATTRS_UNSPECIFIED);
packet_bytes += bytes;
desc.status &= ~DESC_STATUS_CTL;
allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr);
@@ -634,7 +638,8 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
break;
case REG_TX_CUR_BUF: /* Transmit Current Buffer */
if (s->tx_desc_curr != 0) {
- dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc));
+ dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc),
+ MEMTXATTRS_UNSPECIFIED);
value = desc.addr;
} else {
value = 0;
@@ -647,7 +652,8 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
break;
case REG_RX_CUR_BUF: /* Receive Current Buffer */
if (s->rx_desc_curr != 0) {
- dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc));
+ dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc),
+ MEMTXATTRS_UNSPECIFIED);
value = desc.addr;
} else {
value = 0;
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 25685ba3a9..83ef0a783e 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -453,7 +453,8 @@ static void do_phy_ctl(FTGMAC100State *s)
static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
{
- if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
+ if (dma_memory_read(&address_space_memory, addr,
+ bd, sizeof(*bd), MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%"
HWADDR_PRIx "\n", __func__, addr);
return -1;
@@ -473,7 +474,8 @@ static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
lebd.des1 = cpu_to_le32(bd->des1);
lebd.des2 = cpu_to_le32(bd->des2);
lebd.des3 = cpu_to_le32(bd->des3);
- if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))) {
+ if (dma_memory_write(&address_space_memory, addr,
+ &lebd, sizeof(lebd), MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%"
HWADDR_PRIx "\n", __func__, addr);
return -1;
@@ -554,7 +556,8 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
len = sizeof(s->frame) - frame_size;
}
- if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
+ if (dma_memory_read(&address_space_memory, bd.des3,
+ ptr, len, MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
__func__, bd.des3);
s->isr |= FTGMAC100_INT_AHB_ERR;
@@ -1030,20 +1033,24 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
- dma_memory_write(&address_space_memory, buf_addr, buf, 12);
- dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16,
- buf_len - 16);
+ dma_memory_write(&address_space_memory, buf_addr, buf, 12,
+ MEMTXATTRS_UNSPECIFIED);
+ dma_memory_write(&address_space_memory, buf_addr + 12,
+ buf + 16, buf_len - 16,
+ MEMTXATTRS_UNSPECIFIED);
} else {
- dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
+ dma_memory_write(&address_space_memory, buf_addr, buf,
+ buf_len, MEMTXATTRS_UNSPECIFIED);
}
} else {
bd.des1 = 0;
- dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len,
+ MEMTXATTRS_UNSPECIFIED);
}
buf += buf_len;
if (size < 4) {
dma_memory_write(&address_space_memory, buf_addr + buf_len,
- crc_ptr, 4 - size);
+ crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED);
crc_ptr += 4 - size;
}
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 9c7035bc94..0db9aaf76a 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -387,19 +387,22 @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
{
- dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
+ dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd),
+ MEMTXATTRS_UNSPECIFIED);
trace_imx_fec_read_bd(addr, bd->flags, bd->length, bd->data);
}
static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr)
{
- dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd));
+ dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd),
+ MEMTXATTRS_UNSPECIFIED);
}
static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr)
{
- dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
+ dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd),
+ MEMTXATTRS_UNSPECIFIED);
trace_imx_enet_read_bd(addr, bd->flags, bd->length, bd->data,
bd->option, bd->status);
@@ -407,7 +410,8 @@ static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr)
static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
{
- dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd));
+ dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd),
+ MEMTXATTRS_UNSPECIFIED);
}
static void imx_eth_update(IMXFECState *s)
@@ -474,7 +478,8 @@ static void imx_fec_do_tx(IMXFECState *s)
len = ENET_MAX_FRAME_SIZE - frame_size;
s->regs[ENET_EIR] |= ENET_INT_BABT;
}
- dma_memory_read(&address_space_memory, bd.data, ptr, len);
+ dma_memory_read(&address_space_memory, bd.data, ptr, len,
+ MEMTXATTRS_UNSPECIFIED);
ptr += len;
frame_size += len;
if (bd.flags & ENET_BD_L) {
@@ -555,7 +560,8 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
len = ENET_MAX_FRAME_SIZE - frame_size;
s->regs[ENET_EIR] |= ENET_INT_BABT;
}
- dma_memory_read(&address_space_memory, bd.data, ptr, len);
+ dma_memory_read(&address_space_memory, bd.data, ptr, len,
+ MEMTXATTRS_UNSPECIFIED);
ptr += len;
frame_size += len;
if (bd.flags & ENET_BD_L) {
@@ -1103,11 +1109,12 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
buf_len += size - 4;
}
buf_addr = bd.data;
- dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len,
+ MEMTXATTRS_UNSPECIFIED);
buf += buf_len;
if (size < 4) {
dma_memory_write(&address_space_memory, buf_addr + buf_len,
- crc_ptr, 4 - size);
+ crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED);
crc_ptr += 4 - size;
}
bd.flags &= ~ENET_BD_E;
@@ -1210,8 +1217,8 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
*/
const uint8_t zeros[2] = { 0 };
- dma_memory_write(&address_space_memory, buf_addr,
- zeros, sizeof(zeros));
+ dma_memory_write(&address_space_memory, buf_addr, zeros,
+ sizeof(zeros), MEMTXATTRS_UNSPECIFIED);
buf_addr += sizeof(zeros);
buf_len -= sizeof(zeros);
@@ -1220,11 +1227,12 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
shift16 = false;
}
- dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len,
+ MEMTXATTRS_UNSPECIFIED);
buf += buf_len;
if (size < 4) {
dma_memory_write(&address_space_memory, buf_addr + buf_len,
- crc_ptr, 4 - size);
+ crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED);
crc_ptr += 4 - size;
}
bd.flags &= ~ENET_BD_E;
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
index 545b2b7410..9a2328935c 100644
--- a/hw/net/npcm7xx_emc.c
+++ b/hw/net/npcm7xx_emc.c
@@ -200,7 +200,8 @@ static void emc_update_irq_from_reg_change(NPCM7xxEMCState *emc)
static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc)
{
- if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) {
+ if (dma_memory_read(&address_space_memory, addr, desc,
+ sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%"
HWADDR_PRIx "\n", __func__, addr);
return -1;
@@ -221,7 +222,7 @@ static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr)
le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa);
if (dma_memory_write(&address_space_memory, addr, &le_desc,
- sizeof(le_desc))) {
+ sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%"
HWADDR_PRIx "\n", __func__, addr);
return -1;
@@ -231,7 +232,8 @@ static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *desc, dma_addr_t addr)
static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc)
{
- if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc))) {
+ if (dma_memory_read(&address_space_memory, addr, desc,
+ sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%"
HWADDR_PRIx "\n", __func__, addr);
return -1;
@@ -252,7 +254,7 @@ static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *desc, dma_addr_t addr)
le_desc.reserved = cpu_to_le32(desc->reserved);
le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa);
if (dma_memory_write(&address_space_memory, addr, &le_desc,
- sizeof(le_desc))) {
+ sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%"
HWADDR_PRIx "\n", __func__, addr);
return -1;
@@ -366,7 +368,8 @@ static void emc_try_send_next_packet(NPCM7xxEMCState *emc)
buf = malloced_buf;
}
- if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)) {
+ if (dma_memory_read(&address_space_memory, next_buf_addr, buf,
+ length, MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n",
__func__, next_buf_addr);
emc_set_mista(emc, REG_MISTA_TXBERR);
@@ -551,10 +554,11 @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
buf_addr = rx_desc.rxbsa;
emc->regs[REG_CRXBSA] = buf_addr;
- if (dma_memory_write(&address_space_memory, buf_addr, buf, len) ||
+ if (dma_memory_write(&address_space_memory, buf_addr, buf,
+ len, MEMTXATTRS_UNSPECIFIED) ||
(!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) &&
- dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr,
- 4))) {
+ dma_memory_write(&address_space_memory, buf_addr + len,
+ crc_ptr, 4, MEMTXATTRS_UNSPECIFIED))) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n",
__func__);
emc_set_mista(emc, REG_MISTA_RXBERR);
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-13 02:07:05 +0000